[BUG] `define Change Color

[2018boyan]

Thanks for your wonderful work. Vscode has a helpful function that works well on C/C++. It could change color for unused "define" and be useful to check code.

But I find that for Verilog, it could not work

Is it a bug? Am I wrong on some config? Or it does not achieve on verilog-hdl now. If so, do you have a plan to do it and maybe not grey but other striking colors for that unused code of define? Thanks in advance!