[BUG] Syntax highlight error when using interface in System Verilog port declaration

[RasmusGOlsen]

Describe the bug
The interface is highlighted as an error in the following code snippet.

module a (
    input  logic                  clk,
    interface                     intf,
    input logic [intf.WIDTH-1:0]  din
);

endmodule: a

Environment (please complete the following information):

• OS: Ubuntu 22.04
• VS Code version 1.95.3
• Extension version 1.15.5
• color theme Dark Modern

Steps to reproduce
Steps to reproduce the behavior:

1. Copy and Paste code snippet into VSCode
2. Select System Verilog as language mode

Expected behavior
The syntax is valid System Verilog and should not highlight an error.

Actual behavior