From 1d0510210b62bcec5868e630cfa1199ec023ea3c Mon Sep 17 00:00:00 2001
From: Thomas <thomas@pop-os.localdomain>
Date: Tue, 21 Jan 2025 21:10:31 +0000
Subject: [PATCH] Copying over work from local cop

- New files for VAMS Highlighting
- Updates to main json
- Update change log
- Update README
---
 CHANGELOG.md                          |   5 +
 README.md                             |   1 +
 configs/verilogams.configuration.json |  64 +++++
 package.json                          |  28 ++
 snippets/verilogams.json              |  79 ++++++
 syntaxes/verilogams.tmLanguage.json   | 393 ++++++++++++++++++++++++++
 6 files changed, 570 insertions(+)
 create mode 100644 configs/verilogams.configuration.json
 create mode 100644 snippets/verilogams.json
 create mode 100644 syntaxes/verilogams.tmLanguage.json

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 3a0e40ab..5c47aa18 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -3,6 +3,11 @@
 All notable changes to this project will be documented in this file.
 
 The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)\
+## [1.15.6] - 2025-01-22
+
+### Unreleased
+
+- Added Verilog-AMS syntax highlighting
 
 ## [1.15.5] - 2024-11-09
 
diff --git a/README.md b/README.md
index 127d980f..679bbcf4 100644
--- a/README.md
+++ b/README.md
@@ -18,6 +18,7 @@ Install it from [VS Code Marketplace](https://marketplace.visualstudio.com/items
   - SystemVerilog
   - Bluespec SystemVerilog
   - VHDL
+  - Verilog-AMS
   - Vivado UCF constraints
   - Synopsys Design Constraints
   - Verilog Filelists (dot-F files)
diff --git a/configs/verilogams.configuration.json b/configs/verilogams.configuration.json
new file mode 100644
index 00000000..bc801bda
--- /dev/null
+++ b/configs/verilogams.configuration.json
@@ -0,0 +1,64 @@
+{
+  "comments": {
+    "lineComment": "//",
+    "blockComment": ["/*", "*/"]
+  },
+
+  "brackets": [
+    ["{", "}"],
+    ["[", "]"],
+    ["(", ")"],
+    ["fork", "join"],
+    ["case", "endcase"],
+    ["casex", "endcase"],
+    ["casez", "endcase"],
+    ["config", "endconfig"],
+    ["begin", "end"],
+    ["connectrules", "endconnectrules"],
+    ["discipline", "enddiscipline"],
+    ["function", "endfunction"],
+    ["generate", "endgenerate"],
+    ["module", "endmodule"],
+    ["connectmodule","endmodule"],
+    ["macromodule", "endmodule"],
+    ["nature", "endnature"],
+    ["paramset", "endparamset"],
+    ["primitive", "endprimitive"],
+    ["specify", "endspecify"],
+    ["table", "endtable"],
+    ["task", "endtask"]
+  ],
+
+  "autoClosingPairs": [
+    { "open": "{", "close": "}" },
+    { "open": "[", "close": "]" },
+    { "open": "(", "close": ")" },
+    { "open": "\"", "close": "\"", "notIn": ["string"] },
+    { "open": "/*", "close": " */", "notIn": ["string"] },
+    { "open": "begin", "close": "\nend", "notIn": ["string"] },
+    { "open": "fork", "close": "\njoin", "notIn": ["string"] }
+  ],
+
+  "surroundingPairs": [
+    ["{", "}"],
+    ["[", "]"],
+    ["(", ")"],
+    ["'", "'"],
+    ["\"", "\""],
+    ["`", "`"]
+  ],
+
+  "folding": {
+    "offSide": true,
+    "markers": {
+      "start": "^\\s*[//]*region",
+      "end": "^\\s*[//]*endregion"
+    }
+  },
+
+  "wordPattern": "(-?\\d*\\.\\d\\w*)|([^\\`\\~\\!\\@\\#\\%\\^\\&\\*\\(\\)\\-\\=\\+\\[\\{\\]\\}\\\\\\|\\;\\:\\'\\\"\\,\\.\\<\\>\\/\\?\\s]+)",
+  "indentationRules": {
+    "increaseIndentPattern": "(begin$)",
+    "decreaseIndentPattern": "(end$)"
+  }
+}
diff --git a/package.json b/package.json
index 0b5e7808..efb923c2 100644
--- a/package.json
+++ b/package.json
@@ -38,6 +38,21 @@
         ],
         "configuration": "./configs/verilog.configuration.json"
       },
+      {
+        "id": "verilogams",
+        "aliases": [
+          "Verilog-AMS",
+          "verilog-ams",
+          "vams",
+          "VAMS",
+          "verilogams"
+        ],
+        "extensions": [
+          ".vams",
+          ".va"
+        ],
+        "configuration": "./configs/verilogams.configuration.json"
+      },
       {
         "id": "systemverilog",
         "aliases": [
@@ -139,6 +154,11 @@
         "scopeName": "source.verilog",
         "path": "./syntaxes/verilog.tmLanguage.json"
       },
+      {
+        "language": "verilogams",
+        "scopeName": "source.verilogams",
+        "path": "./syntaxes/verilogams.tmLanguage.json"
+      },
       {
         "language": "systemverilog",
         "scopeName": "source.systemverilog",
@@ -196,6 +216,14 @@
         "language": "verilog",
         "path": "./snippets/verilog.json"
       },
+      {
+        "language": "verilogams",
+        "path": "./snippets/verilogams.json"
+      },
+      {
+        "language": "verilogams",
+        "path": "./snippets/verilog.json"
+      },
       {
         "language": "systemverilog",
         "path": "./snippets/verilog.json"
diff --git a/snippets/verilogams.json b/snippets/verilogams.json
new file mode 100644
index 00000000..ee492800
--- /dev/null
+++ b/snippets/verilogams.json
@@ -0,0 +1,79 @@
+{
+    "ddt": {
+        "prefix": ["dd", "ddt"],
+        "body": [
+            "ddt ( ${1:exp}, ${2:[tol]} )"
+        ],
+        "description": "Time Derivative Operator"
+    },
+    "ddx": {
+        "prefix": ["dd", "ddx"],
+        "body": [
+            "ddx ( ${1:exp}, ${2:[unknown]} )"
+        ],
+        "description": "Symbolic Derivative Operator"
+    },
+    "idt": {
+        "prefix": ["id", "idt"],
+        "body": [
+            "idt ( ${1:exp[}, ${2:ic[}, ${3:assert[}, ${4:tol]]]} )"
+        ],
+        "description": "Time Integral Operator"
+    },
+    "idtmod": {
+        "prefix": ["idtm", "idtmod"],
+        "body": [
+            "idtmod ( ${1:exp[}, ${2:ic[}, ${3:modulus[}, ${4:offset[}, ${5:tol]]]]} )"
+        ],
+        "description": "Circular Integral Operator"
+    },
+    "absdelay": {
+        "prefix": ["abs", "absdelay"],
+        "body": [
+            "absdelay ( ${1:exp}, ${2:td[}, ${3:max_delay]} )"
+        ],
+        "description": "Absolute Delay Operator"
+    },
+    "transition": {
+        "prefix": ["trans", "transition"],
+        "body": [
+            "transition ( ${1:exp[}, ${2:td[}, ${3:rise_time[}, ${4:fall_time[}, ${3:time_tol]]]]})"
+        ],
+        "description": "Transition Filter"
+    },
+    "slew": {
+        "prefix": ["sl", "slew"],
+        "body": [
+            "slew ( ${1:exp[}, ${2:max_pos_slew_rate[}, ${3:max_neg_slew_rate]]})"
+        ],
+        "description": "Slew Filter"
+    },
+    "last_crossing": {
+        "prefix": ["sl", "slew"],
+        "body": [
+            "slew ( ${1:exp[}, ${2:direction]})"
+        ],
+        "description": "Last Crossing Function"
+    },
+    "limexp": {
+        "prefix": ["lim", "limexp"],
+        "body": [
+            "limexp ( ${1:exp})"
+        ],
+        "description": "Limited Exponential"
+    },
+    "laplace": {
+        "prefix": ["lap", "laplace"],
+        "body": [
+            "laplace_${1:zp/zd/np/nd} ( ${2:exp}, ${3:Zero}, ${4:Pole [}, ${5:tol]})"
+        ],
+        "description": "Laplace Transform Filters"
+    },
+    "zfilter": {
+        "prefix": ["z", "zi"],
+        "body": [
+            "zi_${1:zp/zd/np/nd} ( ${2:exp}, ${3:Zero}, ${4:Pole }, ${5:period[}, ${6:transition time[}, ${7:time first transition]]})"
+        ],
+        "description": "Z Transform Filters"
+    }
+}
\ No newline at end of file
diff --git a/syntaxes/verilogams.tmLanguage.json b/syntaxes/verilogams.tmLanguage.json
new file mode 100644
index 00000000..4eba8db5
--- /dev/null
+++ b/syntaxes/verilogams.tmLanguage.json
@@ -0,0 +1,393 @@
+{
+  "fileTypes": ["va", "vams"],
+  "name": "Verilogams",
+  "scopeName": "source.verilogams",
+
+  "patterns": [
+    {"include": "#comments"},
+    {"include": "#module_pattern"},
+    {"include": "#keywords"},
+    {"include": "#constants"},
+    {"include": "#strings"},
+    {"include": "#operators"}
+  ],
+  "repository": {
+    "comments": {
+      "patterns": [
+        {
+          "begin": "(^[ \\t]+)?(?=//)",
+          "beginCaptures": {
+            "1": {
+              "name": "punctuation.whitespace.comment.leading.verilogams"
+            }
+          },
+          "end": "(?!\\G)",
+          "patterns": [
+            {
+              "begin": "//",
+              "beginCaptures": {
+                "0": {
+                  "name": "punctuation.definition.comment.verilogams"
+                }
+              },
+              "end": "\\n",
+              "name": "comment.line.double-slash.verilogams"
+            }
+          ]
+        },
+        {
+          "begin": "/\\*",
+          "end": "\\*/",
+          "name": "comment.block.c-style.verilogams"
+        }
+      ]
+    },
+    "constants": {
+      "patterns": [
+        {
+          "match": "`(?!(celldefine|endcelldefine|default_nettype|define|undef|ifdef|ifndef|else|endif|include|resetall|timescale|unconnected_drive|nounconnected_drive))[a-z_A-Z][a-zA-Z0-9_$]*",
+          "name": "variable.other.constant.verilogams"
+        },
+        {
+          "match": "[0-9]*'[bBoOdDhH][a-fA-F0-9_xXzZ]+\\b",
+          "name": "constant.numeric.sized_integer.verilogams"
+        },
+        {
+          "captures": {
+            "1": {
+              "name": "constant.numeric.integer.verilogams"
+            },
+            "2": {
+              "name": "punctuation.separator.range.verilogams"
+            },
+            "3": {
+              "name": "constant.numeric.integer.verilogams"
+            }
+          },
+          "match": "\\b(\\d+)(:)(\\d+)\\b",
+          "name": "meta.block.numeric.range.verilogams"
+        },
+        {
+          "match": "\\b\\d[\\d_]*(?i:e\\d+)?(?:M|K|k|m|u|n|p|f|a)?\\b",
+          "name": "constant.numeric.integer.verilogams"
+        },
+        {
+          "match": "\\b\\d+\\.\\d+(?i:e-?\\d+)?(?:M|K|k|m|u|n|p|f|a)?\\b",
+          "name": "constant.numeric.real.verilogams"
+        },
+        {
+          "match": "#\\d+",
+          "name": "constant.numeric.delay.verilogams"
+        },
+        {
+          "match": "\\b[01xXzZ]+\\b",
+          "name": "constant.numeric.logic.verilogams"
+        }
+      ]
+    },
+    "instantiation_patterns": {
+      "patterns": [
+        {
+          "include": "#keywords"
+        },
+        {
+          "begin": "^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s+([a-zA-Z][a-zA-Z0-9_]*)(?<!begin|if)\\s*(?=\\(|$)",
+          "beginCaptures": {
+            "1": {
+              "name": "entity.name.tag.module.reference.verilogams"
+            },
+            "2": {
+              "name": "entity.name.tag.module.identifier.verilogams"
+            }
+          },
+          "end": ";",
+          "endCaptures": {
+            "0": {
+              "name": "punctuation.terminator.expression.verilogams"
+            }
+          },
+          "name": "meta.block.instantiation.parameterless.verilogams",
+          "patterns": [
+            {
+              "include": "#comments"
+            },
+            {
+              "include": "#constants"
+            },
+            {
+              "include": "#strings"
+            }
+          ]
+        },
+        {
+          "begin": "^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s*(#)(?=\\s*\\()",
+          "beginCaptures": {
+            "1": {
+              "name": "entity.name.tag.module.reference.verilogams"
+            }
+          },
+          "end": ";",
+          "endCaptures": {
+            "0": {
+              "name": "punctuation.terminator.expression.verilogams"
+            }
+          },
+          "name": "meta.block.instantiation.with.parameters.verilogams",
+          "patterns": [
+            {
+              "include": "#parenthetical_list"
+            },
+            {
+              "match": "[a-zA-Z][a-zA-Z0-9_]*",
+              "name": "entity.name.tag.module.identifier.verilogams"
+            }
+          ]
+        }
+      ]
+    },
+    "keywords": {
+      "patterns": [
+        {
+          "match": "\\b(always|and|assign|attribute|begin|buf|bufif0|bufif1|case[xz]?|cmos|deassign|default|defparam|disable|edge|else|end(attribute|case|function|generate|module|primitive|specify|table|task)?|event|for|force|forever|fork|function|generate|genvar|highz(01)|if(none)?|initial|inout|input|integer|join|localparam|medium|module|large|macromodule|nand|negedge|nmos|nor|not|notif(01)|or|output|parameter|pmos|posedge|primitive|pull0|pull1|pulldown|pullup|rcmos|real|realtime|reg|release|repeat|rnmos|rpmos|rtran|rtranif(01)|scalared|signed|small|specify|specparam|strength|strong0|strong1|supply0|supply1|table|task|time|tran|tranif(01)|tri(01)?|tri(and|or|reg)|unsigned|vectored|wait|wand|weak(01)|while|wire|wor|xnor|xor)\\b",
+          "name": "keyword.other.verilogams"
+        },
+        {
+          "match": "^\\s*`((cell)?define|default_(decay_time|nettype|trireg_strength)|delay_mode_(path|unit|zero)|ifdef|ifndef|include|end(if|celldefine)|else|(no)?unconnected_drive|resetall|timescale|undef)\\b",
+          "name": "keyword.other.compiler.directive.verilogams"
+        },
+        {
+          "match": "\\$(f(open|close)|readmem(b|h)|timeformat|printtimescale|stop|finish|(s|real)?time|realtobits|bitstoreal|rtoi|itor|(f)?(display|write(h|b)))\\b",
+          "name": "support.function.system.console.tasks.verilogams"
+        },
+        {
+          "match": "\\$(random|dist_(chi_square|erlang|exponential|normal|poisson|t|uniform))\\b",
+          "name": "support.function.system.random_number.tasks.verilogams"
+        },
+        {
+          "match": "\\$((a)?sync\\$((n)?and|(n)or)\\$(array|plane))\\b",
+          "name": "support.function.system.pld_modeling.tasks.verilogams"
+        },
+        {
+          "match": "\\$(q_(initialize|add|remove|full|exam))\\b",
+          "name": "support.function.system.stochastic.tasks.verilogams"
+        },
+        {
+          "match": "\\$(hold|nochange|period|recovery|setup(hold)?|skew|width)\\b",
+          "name": "support.function.system.timing.tasks.verilogams"
+        },
+        {
+          "match": "\\$(dump(file|vars|off|on|all|limit|flush))\\b",
+          "name": "support.function.system.vcd.tasks.verilogams"
+        },
+        {
+          "match": "\\$(countdrivers|list|input|scope|showscopes|(no)?(key|log)|reset(_count|_value)?|(inc)?save|restart|showvars|getpattern|sreadmem(b|h)|scale)",
+          "name": "support.function.non-standard.tasks.verilogams"
+        },
+        {
+          "match": "\\b((un)?signed)\\b",
+          "name": "storage.modifier.primitive.verilogams"},
+        {
+          "match": "\\b(automatic|genvar|input|output|inout|w?real|reg|integer|string|(real)?time|event|wire)\\b",
+          "name": "storage.type.primitive.verilogams"
+        },
+        {
+          "match": "\\b(analog)\\b",
+          "name": "keyword.other.verilogams"
+        },
+        {
+          "match": "\\b(parameter|from|exclude|localparam)\\b",
+          "name": "storage.modifier.specifier.verilogams"
+        },
+        {
+          "match": "\\b(specparam|defparam|aliasparam)\\b",
+          "name": "keyword.other.parameter.verilogams"
+        },
+        {
+          "match": "\\b(discrete|electrical|voltage|current|branch)\\b",
+          "name": "storage.type.primitive.analog.verilogams"
+        },
+        {
+          "match": "\\b(r?cmos|r?[np]mos|buf(if)?[01]?|r?tran(if)?[01]?|not(if)?[01]?|n?and|x?[xn]?or)\\b",
+          "name": "support.function.inbuilt.primitive.gate_and_switch.verilogams"
+        },
+        {
+          "match":"\\b((end)?specify|(no)?showcancelled|pulsestyle_on(event|detect))\\b",
+          "name": "keyword.other.specify.verilogams"
+        },
+        {
+          "match":"\\b(for|if(none)?|repeat|wait|else|forever|while)\\b",
+          "name": "keyword.control.verilogams"
+        },
+        {
+          "match":"\\b(potential|flow|domain|idt_nature|ddt_nature|access|units|net_resolution|abstol|merge|split|resolveto|continuous|connect)\\b",
+          "name": "storage.type.connectmodules.verilogams"
+        },
+        {
+          "match":"\\b(tri([01]|or|and|reg)?|wand|wor|uwire)\\b",
+          "name": "storage.type.other.verilogams"
+        },
+        {
+          "match":"\\b((strong|weak|pull|supply|highz)[01]|pull(up|down))\\b",
+          "name": "constant.language.other.verilogams"
+        },
+        {
+          "match":"\\b(small|medium|large|inf|ground)\\b",
+          "name": "constant.language.other.verilogams"
+        },
+        {
+          "match":"\\b(library|design|instance|cell|liblist|incdir|force|release|assert|assign|deassign|default|scalared|edge|disable|table|vectored|use)\\b",
+          "name": "keyword.other.verilogams"
+        }
+      ]
+    },
+    "analog_keywords": {
+      "patterns": [
+        {
+          "match": "\\$(display|monitor|write|strobe|bound_step|discontinuity|abstime|simprobe|limit|mfactor|xposition|yposition|angle|hflip|vflip|param_given|port_connected|analog_node_alias|analog_port_alias|table_model)\\b",
+          "name": "support.function.system.console.tasks.verilogams"
+        }
+      ]
+    },
+    "module_pattern": {
+      "patterns": [
+        {
+          "begin": "\\b(module)\\s+([a-zA-Z][a-zA-Z0-9_]*)",
+          "beginCaptures": {
+            "1": {
+              "name": "storage.type.module.verilogams"
+            },
+            "2": {
+              "name": "entity.name.type.module.verilogams"
+            }
+          },
+          "end": "\\bendmodule\\b",
+          "endCaptures": {
+            "0": {
+              "name": "storage.type.module.verilogams"
+            }
+          },
+          "name": "meta.block.module.verilogams",
+          "patterns": [
+            {
+              "include": "#comments"
+            },
+            {
+              "include": "#keywords"
+            },
+            {
+              "include": "#constants"
+            },
+            {
+              "include": "#strings"
+            },
+            {
+              "include": "#instantiation_patterns"
+            },
+            {
+              "include": "#operators"
+            },
+            {"include": "#fuction_keywords"},
+            {"include": "#analog_keywords"}
+          ]
+        }
+      ]
+    },
+    "operators": {
+      "patterns": [
+        {
+          "match": "\\+|-|\\*|/|%|(<|>)=?|(!|=)?==?|!|&&?|\\|\\|?|\\^?~|~\\^?",
+          "name": "keyword.operator.verilogams"
+        }
+      ]
+    },
+    "parenthetical_list": {
+      "patterns": [
+        {
+          "begin": "\\(",
+          "beginCaptures": {
+            "0": {
+              "name": "punctuation.section.list.verilogams"
+            }
+          },
+          "end": "\\)",
+          "endCaptures": {
+            "0": {
+              "name": "punctuation.section.list.verilogams"
+            }
+          },
+          "name": "meta.block.parenthetical_list.verilogams",
+          "patterns": [
+            {
+              "include": "#parenthetical_list"
+            },
+            {
+              "include": "#comments"
+            },
+            {
+              "include": "#keywords"
+            },
+            {
+              "include": "#constants"
+            },
+            {
+              "include": "#strings"
+            }
+          ]
+        }
+      ]
+    },
+    "fuction_keywords":{
+      "patterns": [
+        {
+          "match": "\\b(ddt|ddx|idtmod|idt|absdelay|transition|slew|last_crossing|limexp)\\b",
+          "name": "support.function.anaOperator.verilogams"
+        },
+        {
+          "match":"\\b(laplace_[n|z][d|p]|zi_[n|z][d|p])\\b",
+          "name":"support.function.anaOperator.verilogams"
+        },
+        {
+          "match":"\\b(a?cosh?|a?sinh?|a?tan[2h]?|hypot)\\b",
+          "name":"support.function.maths.trig.verilogams"
+        },
+        {
+          "match":"\\b(exp|sqrt|ln|pow|log|abs)\\b",
+          "name":"support.function.maths.exp.verilogams"
+        },
+        {
+          "match":"\\b(min|max|ceil|floor)\\b",
+          "name":"support.function.maths.minmax.verilogams"
+        },
+        {
+          "match":"\\b((white_|flicker_)?noise|noise(_table(_log)?)?)\\b",
+          "name":"support.function.analog.noise.verilogams"
+        },
+        {
+          "match":"\\b(ac_stim|analysis)\\b",
+          "name":"support.function.analog.verilogams"
+        },
+        {
+          "match":"\\b(cross|above|timer|absdelta|initial_step|final_step|driver_update)\\b",
+          "name":"support.function.anaEvent.verilogams"
+        }
+
+      ]
+    },
+    "strings": {
+      "patterns": [
+        {
+          "begin": "\"",
+          "end": "\"",
+          "name": "string.quoted.double.verilogams",
+          "patterns": [
+            {
+              "match": "\\\\.",
+              "name": "constant.character.escape.verilogams"
+            }
+          ]
+        }
+      ]
+    }
+  }
+
+}