sim.vcd

$date
	Sun May  8 18:01:42 2022
$end
$version
	Icarus Verilog
$end
$timescale
	10ps
$end
$scope module riscv_tb $end
$var reg 1 ! clk $end
$var reg 1 " rstn $end
$var integer 32 # i [31:0] $end
$scope module my_cpu $end
$var wire 1 ! clk $end
$var wire 1 " rstn $end
$var wire 1 $ stall $end
$var wire 1 % flush $end
$var wire 32 & WB_writedata [31:0] $end
$var wire 1 ' WB_reg_write $end
$var wire 5 ( WB_rd [4:0] $end
$var wire 32 ) WB_pc_plus_4 [31:0] $end
$var wire 1 * WB_mem_to_reg $end
$var wire 32 + WB_mem_readdata [31:0] $end
$var wire 2 , WB_jump [1:0] $end
$var wire 32 - WB_alu_result [31:0] $end
$var wire 32 . NEXT_PC [31:0] $end
$var wire 32 / MEM_target [31:0] $end
$var wire 1 0 MEM_taken $end
$var wire 1 1 MEM_reg_write $end
$var wire 5 2 MEM_rd [4:0] $end
$var wire 32 3 MEM_pc_plus_4 [31:0] $end
$var wire 32 4 MEM_mem_writedata [31:0] $end
$var wire 1 5 MEM_mem_write $end
$var wire 1 6 MEM_mem_to_reg $end
$var wire 32 7 MEM_mem_readdata [31:0] $end
$var wire 1 8 MEM_mem_read $end
$var wire 2 9 MEM_jump [1:0] $end
$var wire 3 : MEM_funct3 [2:0] $end
$var wire 32 ; MEM_alu_result [31:0] $end
$var wire 32 < IF_pc_plus_4 [31:0] $end
$var wire 32 = IF_inst [31:0] $end
$var wire 1 > ID_reg_write $end
$var wire 32 ? ID_readdata2 [31:0] $end
$var wire 32 @ ID_readdata1 [31:0] $end
$var wire 32 A ID_pc_plus_4 [31:0] $end
$var wire 1 B ID_mem_write $end
$var wire 1 C ID_mem_to_reg $end
$var wire 1 D ID_mem_read $end
$var wire 2 E ID_jump [1:0] $end
$var wire 32 F ID_inst [31:0] $end
$var wire 32 G ID_imm [31:0] $end
$var wire 1 H ID_branch $end
$var wire 1 I ID_alu_src $end
$var wire 2 J ID_alu_op [1:0] $end
$var wire 32 K ID_PC [31:0] $end
$var wire 32 L EX_target_base [31:0] $end
$var wire 32 M EX_target [31:0] $end
$var wire 1 N EX_taken $end
$var wire 5 O EX_rs2 [4:0] $end
$var wire 5 P EX_rs1 [4:0] $end
$var wire 1 Q EX_reg_write $end
$var wire 32 R EX_readdata2 [31:0] $end
$var wire 32 S EX_readdata1 [31:0] $end
$var wire 5 T EX_rd [4:0] $end
$var wire 32 U EX_pc_plus_4 [31:0] $end
$var wire 7 V EX_opcode [6:0] $end
$var wire 32 W EX_mem_writedata [31:0] $end
$var wire 1 X EX_mem_write $end
$var wire 1 Y EX_mem_to_reg $end
$var wire 1 Z EX_mem_read $end
$var wire 2 [ EX_jump [1:0] $end
$var wire 32 \ EX_imm [31:0] $end
$var wire 2 ] EX_fwd_b [1:0] $end
$var wire 2 ^ EX_fwd_a [1:0] $end
$var wire 7 _ EX_funct7 [6:0] $end
$var wire 3 ` EX_funct3 [2:0] $end
$var wire 1 a EX_check $end
$var wire 1 b EX_branch $end
$var wire 1 c EX_alu_src $end
$var wire 32 d EX_alu_result [31:0] $end
$var wire 2 e EX_alu_op [1:0] $end
$var wire 32 f EX_alu_in_b [31:0] $end
$var wire 32 g EX_alu_in_a [31:0] $end
$var wire 4 h EX_alu_func [3:0] $end
$var wire 32 i EX_PC [31:0] $end
$var reg 32 j PC [31:0] $end
$scope module m_alu $end
$var wire 32 k in_b [31:0] $end
$var wire 32 l in_a [31:0] $end
$var wire 4 m alu_func [3:0] $end
$var reg 1 a check $end
$var reg 32 n result [31:0] $end
$upscope $end
$scope module m_alu_control $end
$var wire 7 o funct7 [6:0] $end
$var wire 3 p funct3 [2:0] $end
$var wire 4 q funct [3:0] $end
$var wire 2 r alu_op [1:0] $end
$var reg 4 s alu_func [3:0] $end
$upscope $end
$scope module m_branch_control $end
$var wire 1 a check $end
$var wire 1 b branch $end
$var reg 1 N taken $end
$upscope $end
$scope module m_branch_target_adder $end
$var wire 32 t in_b [31:0] $end
$var wire 32 u in_a [31:0] $end
$var reg 32 v result [31:0] $end
$upscope $end
$scope module m_control $end
$var wire 7 w opcode [6:0] $end
$var wire 1 > reg_write $end
$var wire 1 B mem_write $end
$var wire 1 C mem_to_reg $end
$var wire 1 D mem_read $end
$var wire 2 x jump [1:0] $end
$var wire 1 H branch $end
$var wire 1 I alu_src $end
$var wire 2 y alu_op [1:0] $end
$var reg 10 z controls [9:0] $end
$upscope $end
$scope module m_data_memory $end
$var wire 1 ! clk $end
$var wire 2 { maskmode [1:0] $end
$var wire 1 | sext $end
$var wire 32 } write_data [31:0] $end
$var wire 1 5 mem_write $end
$var wire 1 8 mem_read $end
$var wire 8 ~ address_internal [7:0] $end
$var wire 32 !" address [31:0] $end
$var reg 32 "" read_data [31:0] $end
$upscope $end
$scope module m_exmem_reg $end
$var wire 1 ! clk $end
$var wire 32 #" ex_alu_result [31:0] $end
$var wire 32 $" ex_pc_target [31:0] $end
$var wire 1 N ex_taken $end
$var wire 1 % flush $end
$var wire 32 %" ex_writedata [31:0] $end
$var wire 1 Q ex_regwrite $end
$var wire 5 &" ex_rd [4:0] $end
$var wire 32 '" ex_pc_plus_4 [31:0] $end
$var wire 1 X ex_memwrite $end
$var wire 1 Y ex_memtoreg $end
$var wire 1 Z ex_memread $end
$var wire 2 (" ex_jump [1:0] $end
$var wire 3 )" ex_funct3 [2:0] $end
$var reg 32 *" mem_alu_result [31:0] $end
$var reg 3 +" mem_funct3 [2:0] $end
$var reg 2 ," mem_jump [1:0] $end
$var reg 1 8 mem_memread $end
$var reg 1 6 mem_memtoreg $end
$var reg 1 5 mem_memwrite $end
$var reg 32 -" mem_pc_plus_4 [31:0] $end
$var reg 32 ." mem_pc_target [31:0] $end
$var reg 5 /" mem_rd [4:0] $end
$var reg 1 1 mem_regwrite $end
$var reg 1 0 mem_taken $end
$var reg 32 0" mem_writedata [31:0] $end
$upscope $end
$scope module m_forwarding $end
$var wire 5 1" MEM_rd [4:0] $end
$var wire 1 1 MEM_reg_write $end
$var wire 1 ' WB_reg_write $end
$var wire 5 2" WB_rd [4:0] $end
$var wire 5 3" EX_rs2 [4:0] $end
$var wire 5 4" EX_rs1 [4:0] $end
$var reg 2 5" fwd_a [1:0] $end
$var reg 2 6" fwd_b [1:0] $end
$upscope $end
$scope module m_hazard $end
$var wire 7 7" ID_opcode [6:0] $end
$var wire 5 8" ID_rs1 [4:0] $end
$var wire 5 9" ID_rs2 [4:0] $end
$var wire 1 0 taken $end
$var wire 1 Q EX_reg_write $end
$var wire 5 :" EX_rd [4:0] $end
$var wire 7 ;" EX_opcode [6:0] $end
$var reg 1 % flush $end
$var reg 1 <" is_EX_load $end
$var reg 1 $ stall $end
$var reg 1 =" use_rs1 $end
$var reg 1 >" use_rs2 $end
$upscope $end
$scope module m_idex_reg $end
$var wire 1 ! clk $end
$var wire 1 % flush $end
$var wire 2 ?" id_aluop [1:0] $end
$var wire 1 I id_alusrc $end
$var wire 1 H id_branch $end
$var wire 3 @" id_funct3 [2:0] $end
$var wire 7 A" id_funct7 [6:0] $end
$var wire 2 B" id_jump [1:0] $end
$var wire 1 D id_memread $end
$var wire 1 C id_memtoreg $end
$var wire 1 B id_memwrite $end
$var wire 7 C" id_opcode [6:0] $end
$var wire 5 D" id_rd [4:0] $end
$var wire 1 > id_regwrite $end
$var wire 5 E" id_rs1 [4:0] $end
$var wire 5 F" id_rs2 [4:0] $end
$var wire 1 $ stall $end
$var wire 32 G" id_sextimm [31:0] $end
$var wire 32 H" id_readdata2 [31:0] $end
$var wire 32 I" id_readdata1 [31:0] $end
$var wire 32 J" id_pc_plus_4 [31:0] $end
$var wire 32 K" id_PC [31:0] $end
$var reg 32 L" ex_PC [31:0] $end
$var reg 2 M" ex_aluop [1:0] $end
$var reg 1 c ex_alusrc $end
$var reg 1 b ex_branch $end
$var reg 3 N" ex_funct3 [2:0] $end
$var reg 7 O" ex_funct7 [6:0] $end
$var reg 2 P" ex_jump [1:0] $end
$var reg 1 Z ex_memread $end
$var reg 1 Y ex_memtoreg $end
$var reg 1 X ex_memwrite $end
$var reg 7 Q" ex_opcode [6:0] $end
$var reg 32 R" ex_pc_plus_4 [31:0] $end
$var reg 5 S" ex_rd [4:0] $end
$var reg 32 T" ex_readdata1 [31:0] $end
$var reg 32 U" ex_readdata2 [31:0] $end
$var reg 1 Q ex_regwrite $end
$var reg 5 V" ex_rs1 [4:0] $end
$var reg 5 W" ex_rs2 [4:0] $end
$var reg 32 X" ex_sextimm [31:0] $end
$upscope $end
$scope module m_ifid_reg $end
$var wire 1 ! clk $end
$var wire 1 % flush $end
$var wire 32 Y" if_PC [31:0] $end
$var wire 1 $ stall $end
$var wire 32 Z" if_pc_plus_4 [31:0] $end
$var wire 32 [" if_instruction [31:0] $end
$var reg 32 \" id_PC [31:0] $end
$var reg 32 ]" id_instruction [31:0] $end
$var reg 32 ^" id_pc_plus_4 [31:0] $end
$upscope $end
$scope module m_immediate_generator $end
$var wire 32 _" instruction [31:0] $end
$var wire 7 `" opcode [6:0] $end
$var reg 32 a" sextimm [31:0] $end
$upscope $end
$scope module m_instruction_memory $end
$var wire 32 b" address [31:0] $end
$var reg 32 c" instruction [31:0] $end
$upscope $end
$scope module m_memwb_reg $end
$var wire 1 ! clk $end
$var wire 32 d" mem_alu_result [31:0] $end
$var wire 2 e" mem_jump [1:0] $end
$var wire 1 6 mem_memtoreg $end
$var wire 32 f" mem_pc_plus_4 [31:0] $end
$var wire 5 g" mem_rd [4:0] $end
$var wire 32 h" mem_readdata [31:0] $end
$var wire 1 1 mem_regwrite $end
$var reg 32 i" wb_alu_result [31:0] $end
$var reg 2 j" wb_jump [1:0] $end
$var reg 1 * wb_memtoreg $end
$var reg 32 k" wb_pc_plus_4 [31:0] $end
$var reg 5 l" wb_rd [4:0] $end
$var reg 32 m" wb_readdata [31:0] $end
$var reg 1 ' wb_regwrite $end
$upscope $end
$scope module m_pc_plus_4_adder $end
$var wire 32 n" in_a [31:0] $end
$var wire 32 o" in_b [31:0] $end
$var reg 32 p" result [31:0] $end
$upscope $end
$scope module m_register_file $end
$var wire 1 ! clk $end
$var wire 32 q" readdata1 [31:0] $end
$var wire 32 r" readdata2 [31:0] $end
$var wire 5 s" readreg1 [4:0] $end
$var wire 5 t" readreg2 [4:0] $end
$var wire 1 ' wen $end
$var wire 5 u" writereg [4:0] $end
$var wire 32 v" writedata [31:0] $end
$upscope $end
$scope module mem_writedata_select $end
$var wire 32 w" in1 [31:0] $end
$var wire 32 x" in2 [31:0] $end
$var wire 2 y" select [1:0] $end
$var wire 32 z" in3 [31:0] $end
$var reg 32 {" out [31:0] $end
$upscope $end
$scope module mux_PC_source $end
$var wire 32 |" in1 [31:0] $end
$var wire 32 }" in2 [31:0] $end
$var wire 32 ~" in3 [31:0] $end
$var wire 32 !# in4 [31:0] $end
$var wire 2 "# select [1:0] $end
$var reg 32 ## out [31:0] $end
$upscope $end
$scope module mux_WriteBack $end
$var wire 32 $# in1 [31:0] $end
$var wire 32 %# in2 [31:0] $end
$var wire 32 &# in3 [31:0] $end
$var wire 2 '# select [1:0] $end
$var reg 32 (# out [31:0] $end
$upscope $end
$scope module mux_alu_in_1 $end
$var wire 32 )# in1 [31:0] $end
$var wire 32 *# in2 [31:0] $end
$var wire 32 +# in3 [31:0] $end
$var wire 2 ,# select [1:0] $end
$var reg 32 -# out [31:0] $end
$upscope $end
$scope module mux_alu_in_2 $end
$var wire 32 .# in1 [31:0] $end
$var wire 32 /# in2 [31:0] $end
$var wire 32 0# in3 [31:0] $end
$var wire 32 1# in4 [31:0] $end
$var wire 2 2# select [1:0] $end
$var reg 32 3# out [31:0] $end
$upscope $end
$scope module mux_target_base_selector $end
$var wire 32 4# in1 [31:0] $end
$var wire 32 5# in2 [31:0] $end
$var wire 1 6# select $end
$var reg 32 7# out [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 7#
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bx0 5#
bx 4#
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bx 2#
bx 1#
bx 0#
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bx .#
bx -#
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$end
#500
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b10000 ##
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b10011 `"
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b10 D"
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b10 E"
b1111110 A"
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b1100100 @
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b1111 m
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b1000 \"
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b1000 O
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