From a6e478d20061c16e3bcc3aed30112d474d1ad9df Mon Sep 17 00:00:00 2001
From: Maxim Vezenov <mvezenov@gmail.com>
Date: Tue, 21 Jan 2025 21:39:36 +0000
Subject: [PATCH 1/4] mapping of instructions in loop invariant pass should
 account for post order

---
 .../src/ssa/opt/loop_invariant.rs             |    13 +-
 .../regression_7128/Nargo.toml                |     6 +
 .../regression_7128/Prover.toml               |     1 +
 .../regression_7128/src/main.nr               |    26 +
 .../regression_7128/Nargo.toml                |     6 +
 .../regression_7128/Prover.toml               |     1 +
 .../regression_7128/src/main.nr               |    26 +
 .../execution_success/regression_7128/ssa.txt | 19189 ++++++++++++++++
 8 files changed, 19260 insertions(+), 8 deletions(-)
 create mode 100644 test_programs/execution_failure/regression_7128/Nargo.toml
 create mode 100644 test_programs/execution_failure/regression_7128/Prover.toml
 create mode 100644 test_programs/execution_failure/regression_7128/src/main.nr
 create mode 100644 test_programs/execution_success/regression_7128/Nargo.toml
 create mode 100644 test_programs/execution_success/regression_7128/Prover.toml
 create mode 100644 test_programs/execution_success/regression_7128/src/main.nr
 create mode 100644 test_programs/execution_success/regression_7128/ssa.txt

diff --git a/compiler/noirc_evaluator/src/ssa/opt/loop_invariant.rs b/compiler/noirc_evaluator/src/ssa/opt/loop_invariant.rs
index 224916c95e9..796879738b1 100644
--- a/compiler/noirc_evaluator/src/ssa/opt/loop_invariant.rs
+++ b/compiler/noirc_evaluator/src/ssa/opt/loop_invariant.rs
@@ -12,12 +12,7 @@ use fxhash::{FxHashMap as HashMap, FxHashSet as HashSet};
 
 use crate::ssa::{
     ir::{
-        basic_block::BasicBlockId,
-        function::Function,
-        function_inserter::FunctionInserter,
-        instruction::{binary::eval_constant_binary_op, BinaryOp, Instruction, InstructionId},
-        types::Type,
-        value::ValueId,
+        basic_block::BasicBlockId, function::Function, function_inserter::FunctionInserter, instruction::{binary::eval_constant_binary_op, BinaryOp, Instruction, InstructionId}, post_order::PostOrder, types::Type, value::ValueId
     },
     Ssa,
 };
@@ -272,8 +267,10 @@ impl<'f> LoopInvariantContext<'f> {
     /// correct new value IDs based upon the `FunctionInserter` internal map.
     /// Leaving out this mapping could lead to instructions with values that do not exist.
     fn map_dependent_instructions(&mut self) {
-        let blocks = self.inserter.function.reachable_blocks();
-        for block in blocks {
+        let mut block_order = PostOrder::with_function(self.inserter.function).into_vec();
+        block_order.reverse(); 
+
+        for block in block_order {
             for instruction_id in self.inserter.function.dfg[block].take_instructions() {
                 self.inserter.push_instruction(instruction_id, block);
             }
diff --git a/test_programs/execution_failure/regression_7128/Nargo.toml b/test_programs/execution_failure/regression_7128/Nargo.toml
new file mode 100644
index 00000000000..4d7b621526a
--- /dev/null
+++ b/test_programs/execution_failure/regression_7128/Nargo.toml
@@ -0,0 +1,6 @@
+[package]
+name = "regression_7128"
+type = "bin"
+authors = [""]
+
+[dependencies]
\ No newline at end of file
diff --git a/test_programs/execution_failure/regression_7128/Prover.toml b/test_programs/execution_failure/regression_7128/Prover.toml
new file mode 100644
index 00000000000..dd9b68d125e
--- /dev/null
+++ b/test_programs/execution_failure/regression_7128/Prover.toml
@@ -0,0 +1 @@
+in0 = "1"
diff --git a/test_programs/execution_failure/regression_7128/src/main.nr b/test_programs/execution_failure/regression_7128/src/main.nr
new file mode 100644
index 00000000000..291f6498a66
--- /dev/null
+++ b/test_programs/execution_failure/regression_7128/src/main.nr
@@ -0,0 +1,26 @@
+fn main(in0: Field) -> pub Field {
+    let mut out0 : Field = 0;
+    let mut tmp1 : Field = 0;
+
+    if ((out0 == out0) & true) // <== changing out0 to in0 or removing
+    {                          //     the comparison changes the result
+        let in0_as_bytes : [u8; 32] = in0.to_be_bytes();
+        let mut result : [u8; 32] = 0.to_be_bytes();
+        for i in 0..32 {
+            result[i] = (in0_as_bytes[i] ^ result[i]);
+        }
+        tmp1 = std::field::bytes32_to_field(result);
+    }
+
+    let mut tmp2 : Field = 0; // <== moving this to the top of main,
+    if (0.lt(in0))            //     changes the result
+    {
+        tmp2 = 1;
+    }
+
+    out0 = (tmp2 - tmp1);
+
+    assert(out0 != 0, "soundness violation"); 
+
+    out0
+}
\ No newline at end of file
diff --git a/test_programs/execution_success/regression_7128/Nargo.toml b/test_programs/execution_success/regression_7128/Nargo.toml
new file mode 100644
index 00000000000..4d7b621526a
--- /dev/null
+++ b/test_programs/execution_success/regression_7128/Nargo.toml
@@ -0,0 +1,6 @@
+[package]
+name = "regression_7128"
+type = "bin"
+authors = [""]
+
+[dependencies]
\ No newline at end of file
diff --git a/test_programs/execution_success/regression_7128/Prover.toml b/test_programs/execution_success/regression_7128/Prover.toml
new file mode 100644
index 00000000000..dd9b68d125e
--- /dev/null
+++ b/test_programs/execution_success/regression_7128/Prover.toml
@@ -0,0 +1 @@
+in0 = "1"
diff --git a/test_programs/execution_success/regression_7128/src/main.nr b/test_programs/execution_success/regression_7128/src/main.nr
new file mode 100644
index 00000000000..4c2a9e62a7f
--- /dev/null
+++ b/test_programs/execution_success/regression_7128/src/main.nr
@@ -0,0 +1,26 @@
+fn main(in0: Field) -> pub Field {
+    let mut out0 : Field = 0;
+    let mut tmp1 : Field = 0;
+
+    if ((out0 == out0) & true) // <== changing out0 to in0 or removing
+    {                          //     the comparison changes the result
+        let in0_as_bytes : [u8; 32] = in0.to_be_bytes();
+        let mut result : [u8; 32] = 0.to_be_bytes();
+        for i in 0..32 {
+            result[i] = (in0_as_bytes[i] ^ result[i]);
+        }
+        tmp1 = std::field::bytes32_to_field(result);
+    }
+
+    let mut tmp2 : Field = 0; // <== moving this to the top of main,
+    if (0.lt(in0))            //     changes the result
+    {
+        tmp2 = 1;
+    }
+
+    out0 = (tmp2 - tmp1);
+
+    assert(out0 == 0, "completeness violation");
+
+    out0
+}
\ No newline at end of file
diff --git a/test_programs/execution_success/regression_7128/ssa.txt b/test_programs/execution_success/regression_7128/ssa.txt
new file mode 100644
index 00000000000..7665d52c992
--- /dev/null
+++ b/test_programs/execution_success/regression_7128/ssa.txt
@@ -0,0 +1,19189 @@
+After Initial SSA:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v6 = allocate -> &mut Field
+    store Field 0 at v6
+    v8 = allocate -> &mut Field
+    store Field 0 at v8
+    v9 = load v6 -> Field
+    v10 = load v6 -> Field
+    v11 = eq v9, v10
+    v13 = unchecked_mul v11, u1 1
+    jmpif v13 then: b1, else: b4
+  b1():
+    v15 = call f1(v4) -> [u8; 32]
+    v17 = call f1(Field 0) -> [u8; 32]
+    v18 = allocate -> &mut [u8; 32]
+    store v17 at v18
+    jmp b2(u32 0)
+  b2(v5: u32):
+    v21 = lt v5, u32 32
+    jmpif v21 then: b7, else: b3
+  b3():
+    v22 = load v18 -> [u8; 32]
+    v24 = call f2(v22) -> Field
+    store v24 at v8
+    jmp b4()
+  b4():
+    v25 = allocate -> &mut Field
+    store Field 0 at v25
+    v27 = call f3(Field 0, v4) -> u1
+    jmpif v27 then: b5, else: b6
+  b5():
+    store Field 1 at v25
+    jmp b6()
+  b6():
+    v29 = load v25 -> Field
+    v30 = load v8 -> Field
+    v31 = sub v29, v30
+    store v31 at v6
+    v32 = load v6 -> Field
+    return v32
+  b7():
+    v33 = load v18 -> [u8; 32]
+    v34 = array_get v15, index v5 -> u8
+    v35 = load v18 -> [u8; 32]
+    v36 = array_get v35, index v5 -> u8
+    v37 = xor v34, v36
+    v38 = array_set v33, index v5, value v37
+    v40 = unchecked_add v5, u32 1
+    store v38 at v18
+    v41 = unchecked_add v5, u32 1
+    jmp b2(v41)
+}
+acir(inline) fn to_be_bytes f1 {
+  b0(v4: Field):
+    v8 = call f18(v4, u32 256) -> [u8; 32]
+    v38 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v39 = allocate -> &mut u1
+    store u1 0 at v39
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v43 = lt v5, u32 32
+    jmpif v43 then: b3, else: b2
+  b2():
+    v44 = load v39 -> u1
+    constrain v44 == u1 1
+    return v8
+  b3():
+    v46 = load v39 -> u1
+    v47 = not v46
+    jmpif v47 then: b4, else: b7
+  b4():
+    v48 = array_get v8, index v5 -> u8
+    v49 = lt v5, u32 32
+    constrain v49 == u1 1, "Index out of bounds"
+    v50 = array_get v38, index v5 -> u8
+    v51 = eq v48, v50
+    v52 = not v51
+    jmpif v52 then: b5, else: b6
+  b5():
+    v53 = array_get v8, index v5 -> u8
+    v54 = lt v5, u32 32
+    constrain v54 == u1 1, "Index out of bounds"
+    v55 = array_get v38, index v5 -> u8
+    v56 = lt v53, v55
+    constrain v56 == u1 1
+    store u1 1 at v39
+    jmp b6()
+  b6():
+    jmp b7()
+  b7():
+    v58 = unchecked_add v5, u32 1
+    jmp b1(v58)
+}
+acir(inline) fn bytes32_to_field f2 {
+  b0(v4: [u8; 32]):
+    v6 = allocate -> &mut Field
+    store Field 1 at v6
+    v8 = allocate -> &mut Field
+    store Field 0 at v8
+    v10 = allocate -> &mut Field
+    store Field 0 at v10
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v13 = lt v5, u32 16
+    jmpif v13 then: b3, else: b2
+  b2():
+    v14 = load v10 -> Field
+    v15 = load v8 -> Field
+    v16 = load v6 -> Field
+    v17 = mul v15, v16
+    v18 = add v14, v17
+    return v18
+  b3():
+    v19 = load v8 -> Field
+    v21 = sub u32 15, v5
+    v22 = array_get v4, index v21 -> u8
+    v23 = cast v22 as Field
+    v24 = load v6 -> Field
+    v25 = mul v23, v24
+    v26 = add v19, v25
+    store v26 at v8
+    v27 = load v10 -> Field
+    v29 = sub u32 31, v5
+    v30 = array_get v4, index v29 -> u8
+    v31 = cast v30 as Field
+    v32 = load v6 -> Field
+    v33 = mul v31, v32
+    v34 = add v27, v33
+    store v34 at v10
+    v35 = load v6 -> Field
+    v37 = mul v35, Field 256
+    store v37 at v6
+    v39 = unchecked_add v5, u32 1
+    jmp b1(v39)
+}
+acir(inline) fn lt f3 {
+  b0(v4: Field, v5: Field):
+    v8 = call f4() -> u1
+    jmpif v8 then: b2, else: b1
+  b1():
+    v10 = call f6(v4, v5) -> u1
+    jmp b3(v10)
+  b2():
+    v12 = call f5(v4, v5) -> u1
+    jmp b3(v12)
+  b3(v6: u1):
+    return v6
+}
+acir(inline) fn is_bn254 f4 {
+  b0():
+    return u1 1
+}
+acir(inline) fn lt f5 {
+  b0(v4: Field, v5: Field):
+    v7 = call f9(v5, v4) -> u1
+    return v7
+}
+acir(inline) fn lt_fallback f6 {
+  b0(v4: Field, v5: Field):
+    v8 = call f7(v4) -> [u8; 32]
+    v10 = call f7(v5) -> [u8; 32]
+    v11 = allocate -> &mut u1
+    store u1 0 at v11
+    v13 = allocate -> &mut u1
+    store u1 0 at v13
+    jmp b1(u32 0)
+  b1(v6: u32):
+    v16 = lt v6, u32 32
+    jmpif v16 then: b3, else: b2
+  b2():
+    v17 = load v11 -> u1
+    return v17
+  b3():
+    v18 = load v13 -> u1
+    v19 = not v18
+    jmpif v19 then: b4, else: b7
+  b4():
+    v21 = sub u32 31, v6
+    v22 = array_get v8, index v21 -> u8
+    v23 = sub u32 31, v6
+    v24 = array_get v10, index v23 -> u8
+    v25 = eq v22, v24
+    v26 = not v25
+    jmpif v26 then: b5, else: b6
+  b5():
+    v27 = lt v22, v24
+    store v27 at v11
+    store u1 1 at v13
+    jmp b6()
+  b6():
+    jmp b7()
+  b7():
+    v30 = unchecked_add v6, u32 1
+    jmp b1(v30)
+}
+acir(inline) fn to_le_bytes f7 {
+  b0(v4: Field):
+    v8 = call f8(v4, u32 256) -> [u8; 32]
+    v38 = make_array [u8 1, u8 0, u8 0, u8 240, u8 147, u8 245, u8 225, u8 67, u8 145, u8 112, u8 185, u8 121, u8 72, u8 232, u8 51, u8 40, u8 93, u8 88, u8 129, u8 129, u8 182, u8 69, u8 80, u8 184, u8 41, u8 160, u8 49, u8 225, u8 114, u8 78, u8 100, u8 48] : [u8]
+    v39 = allocate -> &mut u1
+    store u1 0 at v39
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v43 = lt v5, u32 32
+    jmpif v43 then: b3, else: b2
+  b2():
+    v44 = load v39 -> u1
+    constrain v44 == u1 1
+    return v8
+  b3():
+    v46 = load v39 -> u1
+    v47 = not v46
+    jmpif v47 then: b4, else: b7
+  b4():
+    v49 = sub u32 31, v5
+    v50 = array_get v8, index v49 -> u8
+    v51 = sub u32 31, v5
+    v52 = lt v51, u32 32
+    constrain v52 == u1 1, "Index out of bounds"
+    v53 = array_get v38, index v51 -> u8
+    v54 = eq v50, v53
+    v55 = not v54
+    jmpif v55 then: b5, else: b6
+  b5():
+    v56 = sub u32 31, v5
+    v57 = array_get v8, index v56 -> u8
+    v58 = sub u32 31, v5
+    v59 = lt v58, u32 32
+    constrain v59 == u1 1, "Index out of bounds"
+    v60 = array_get v38, index v58 -> u8
+    v61 = lt v57, v60
+    constrain v61 == u1 1
+    store u1 1 at v39
+    jmp b6()
+  b6():
+    jmp b7()
+  b7():
+    v63 = unchecked_add v5, u32 1
+    jmp b1(v63)
+}
+acir(inline) fn to_le_radix f8 {
+  b0(v4: Field, v5: u32):
+    call assert_constant(v5)
+    v8 = call to_le_radix(v4, v5) -> [u8; 32]
+    return v8
+}
+acir(inline) fn gt f9 {
+  b0(v4: Field, v5: Field):
+    v8 = eq v4, v5
+    jmpif v8 then: b5, else: b1
+  b1():
+    v10 = call f10(v4, v5) -> u1
+    jmpif v10 then: b3, else: b2
+  b2():
+    call f11(v4, v5)
+    jmp b4(u1 1)
+  b3():
+    call f11(v5, v4)
+    jmp b4(u1 0)
+  b4(v6: u1):
+    jmp b6(v6)
+  b5():
+    jmp b6(u1 0)
+  b6(v7: u1):
+    return v7
+}
+brillig(inline) fn field_less_than f10 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+acir(inline) fn assert_gt f11 {
+  b0(v4: Field, v5: Field):
+    v7, v8 = call f12(v4) -> (Field, Field)
+    v10, v11 = call f12(v5) -> (Field, Field)
+    call f13(v7, v8, v10, v11)
+    return
+}
+acir(inline) fn decompose f12 {
+  b0(v4: Field):
+    v6, v7 = call f16(v4) -> (Field, Field)
+    call f15(v6)
+    call f15(v7)
+    v10 = mul Field 340282366920938463463374607431768211456, v7
+    v11 = add v6, v10
+    v12 = eq v4, v11
+    constrain v4 == v11
+    call f13(Field 53438638232309528389504892708671455233, Field 64323764613183177041862057485226039389, v6, v7)
+    return v6, v7
+}
+acir(inline) fn assert_gt_limbs f13 {
+  b0(v4: Field, v5: Field, v6: Field, v7: Field):
+    v9 = call f14(v4, v6) -> u1
+    v10 = sub v4, v6
+    v12 = sub v10, Field 1
+    v13 = cast v9 as Field
+    v14 = mul v13, Field 340282366920938463463374607431768211456
+    v15 = add v12, v14
+    v16 = sub v5, v7
+    v17 = cast v9 as Field
+    v18 = sub v16, v17
+    call f15(v15)
+    call f15(v18)
+    return
+}
+brillig(inline) fn lte_hint f14 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f10(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+acir(inline) fn assert_max_bit_size f15 {
+  b0(v4: Field):
+    range_check v4 to 128 bits
+    return
+}
+brillig(inline) fn decompose_hint f16 {
+  b0(v4: Field):
+    v6, v7 = call f17(v4) -> (Field, Field)
+    return v6, v7
+}
+brillig(inline) fn compute_decomposition f17 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    store v4 at v5
+    v6 = load v5 -> Field
+    v7 = truncate v6 to 64 bits, max_bit_size: 254
+    v8 = cast v7 as u64
+    v9 = cast v7 as Field
+    v10 = load v5 -> Field
+    v11 = sub v10, v9
+    v12 = div v11, Field 18446744073709551616
+    store v12 at v5
+    v13 = load v5 -> Field
+    v14 = truncate v13 to 64 bits, max_bit_size: 254
+    v15 = cast v14 as u64
+    v16 = cast v14 as Field
+    v17 = load v5 -> Field
+    v18 = sub v17, v16
+    v19 = div v18, Field 18446744073709551616
+    v20 = mul v16, Field 18446744073709551616
+    v21 = add v20, v9
+    return v21, v19
+}
+acir(inline) fn to_be_radix f18 {
+  b0(v4: Field, v5: u32):
+    call assert_constant(v5)
+    v8 = call to_be_radix(v4, v5) -> [u8; 32]
+    return v8
+}
+
+After Removing Unreachable Functions:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v6 = allocate -> &mut Field
+    store Field 0 at v6
+    v8 = allocate -> &mut Field
+    store Field 0 at v8
+    v9 = load v6 -> Field
+    v10 = load v6 -> Field
+    v11 = eq v9, v10
+    v13 = unchecked_mul v11, u1 1
+    jmpif v13 then: b1, else: b4
+  b1():
+    v15 = call f1(v4) -> [u8; 32]
+    v17 = call f1(Field 0) -> [u8; 32]
+    v18 = allocate -> &mut [u8; 32]
+    store v17 at v18
+    jmp b2(u32 0)
+  b2(v5: u32):
+    v21 = lt v5, u32 32
+    jmpif v21 then: b7, else: b3
+  b3():
+    v22 = load v18 -> [u8; 32]
+    v24 = call f2(v22) -> Field
+    store v24 at v8
+    jmp b4()
+  b4():
+    v25 = allocate -> &mut Field
+    store Field 0 at v25
+    v27 = call f3(Field 0, v4) -> u1
+    jmpif v27 then: b5, else: b6
+  b5():
+    store Field 1 at v25
+    jmp b6()
+  b6():
+    v29 = load v25 -> Field
+    v30 = load v8 -> Field
+    v31 = sub v29, v30
+    store v31 at v6
+    v32 = load v6 -> Field
+    return v32
+  b7():
+    v33 = load v18 -> [u8; 32]
+    v34 = array_get v15, index v5 -> u8
+    v35 = load v18 -> [u8; 32]
+    v36 = array_get v35, index v5 -> u8
+    v37 = xor v34, v36
+    v38 = array_set v33, index v5, value v37
+    v40 = unchecked_add v5, u32 1
+    store v38 at v18
+    v41 = unchecked_add v5, u32 1
+    jmp b2(v41)
+}
+acir(inline) fn to_be_bytes f1 {
+  b0(v4: Field):
+    v8 = call f18(v4, u32 256) -> [u8; 32]
+    v38 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v39 = allocate -> &mut u1
+    store u1 0 at v39
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v43 = lt v5, u32 32
+    jmpif v43 then: b3, else: b2
+  b2():
+    v44 = load v39 -> u1
+    constrain v44 == u1 1
+    return v8
+  b3():
+    v46 = load v39 -> u1
+    v47 = not v46
+    jmpif v47 then: b4, else: b7
+  b4():
+    v48 = array_get v8, index v5 -> u8
+    v49 = lt v5, u32 32
+    constrain v49 == u1 1, "Index out of bounds"
+    v50 = array_get v38, index v5 -> u8
+    v51 = eq v48, v50
+    v52 = not v51
+    jmpif v52 then: b5, else: b6
+  b5():
+    v53 = array_get v8, index v5 -> u8
+    v54 = lt v5, u32 32
+    constrain v54 == u1 1, "Index out of bounds"
+    v55 = array_get v38, index v5 -> u8
+    v56 = lt v53, v55
+    constrain v56 == u1 1
+    store u1 1 at v39
+    jmp b6()
+  b6():
+    jmp b7()
+  b7():
+    v58 = unchecked_add v5, u32 1
+    jmp b1(v58)
+}
+acir(inline) fn bytes32_to_field f2 {
+  b0(v4: [u8; 32]):
+    v6 = allocate -> &mut Field
+    store Field 1 at v6
+    v8 = allocate -> &mut Field
+    store Field 0 at v8
+    v10 = allocate -> &mut Field
+    store Field 0 at v10
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v13 = lt v5, u32 16
+    jmpif v13 then: b3, else: b2
+  b2():
+    v14 = load v10 -> Field
+    v15 = load v8 -> Field
+    v16 = load v6 -> Field
+    v17 = mul v15, v16
+    v18 = add v14, v17
+    return v18
+  b3():
+    v19 = load v8 -> Field
+    v21 = sub u32 15, v5
+    v22 = array_get v4, index v21 -> u8
+    v23 = cast v22 as Field
+    v24 = load v6 -> Field
+    v25 = mul v23, v24
+    v26 = add v19, v25
+    store v26 at v8
+    v27 = load v10 -> Field
+    v29 = sub u32 31, v5
+    v30 = array_get v4, index v29 -> u8
+    v31 = cast v30 as Field
+    v32 = load v6 -> Field
+    v33 = mul v31, v32
+    v34 = add v27, v33
+    store v34 at v10
+    v35 = load v6 -> Field
+    v37 = mul v35, Field 256
+    store v37 at v6
+    v39 = unchecked_add v5, u32 1
+    jmp b1(v39)
+}
+acir(inline) fn lt f3 {
+  b0(v4: Field, v5: Field):
+    v8 = call f4() -> u1
+    jmpif v8 then: b2, else: b1
+  b1():
+    v10 = call f6(v4, v5) -> u1
+    jmp b3(v10)
+  b2():
+    v12 = call f5(v4, v5) -> u1
+    jmp b3(v12)
+  b3(v6: u1):
+    return v6
+}
+acir(inline) fn is_bn254 f4 {
+  b0():
+    return u1 1
+}
+acir(inline) fn lt f5 {
+  b0(v4: Field, v5: Field):
+    v7 = call f9(v5, v4) -> u1
+    return v7
+}
+acir(inline) fn lt_fallback f6 {
+  b0(v4: Field, v5: Field):
+    v8 = call f7(v4) -> [u8; 32]
+    v10 = call f7(v5) -> [u8; 32]
+    v11 = allocate -> &mut u1
+    store u1 0 at v11
+    v13 = allocate -> &mut u1
+    store u1 0 at v13
+    jmp b1(u32 0)
+  b1(v6: u32):
+    v16 = lt v6, u32 32
+    jmpif v16 then: b3, else: b2
+  b2():
+    v17 = load v11 -> u1
+    return v17
+  b3():
+    v18 = load v13 -> u1
+    v19 = not v18
+    jmpif v19 then: b4, else: b7
+  b4():
+    v21 = sub u32 31, v6
+    v22 = array_get v8, index v21 -> u8
+    v23 = sub u32 31, v6
+    v24 = array_get v10, index v23 -> u8
+    v25 = eq v22, v24
+    v26 = not v25
+    jmpif v26 then: b5, else: b6
+  b5():
+    v27 = lt v22, v24
+    store v27 at v11
+    store u1 1 at v13
+    jmp b6()
+  b6():
+    jmp b7()
+  b7():
+    v30 = unchecked_add v6, u32 1
+    jmp b1(v30)
+}
+acir(inline) fn to_le_bytes f7 {
+  b0(v4: Field):
+    v8 = call f8(v4, u32 256) -> [u8; 32]
+    v38 = make_array [u8 1, u8 0, u8 0, u8 240, u8 147, u8 245, u8 225, u8 67, u8 145, u8 112, u8 185, u8 121, u8 72, u8 232, u8 51, u8 40, u8 93, u8 88, u8 129, u8 129, u8 182, u8 69, u8 80, u8 184, u8 41, u8 160, u8 49, u8 225, u8 114, u8 78, u8 100, u8 48] : [u8]
+    v39 = allocate -> &mut u1
+    store u1 0 at v39
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v43 = lt v5, u32 32
+    jmpif v43 then: b3, else: b2
+  b2():
+    v44 = load v39 -> u1
+    constrain v44 == u1 1
+    return v8
+  b3():
+    v46 = load v39 -> u1
+    v47 = not v46
+    jmpif v47 then: b4, else: b7
+  b4():
+    v49 = sub u32 31, v5
+    v50 = array_get v8, index v49 -> u8
+    v51 = sub u32 31, v5
+    v52 = lt v51, u32 32
+    constrain v52 == u1 1, "Index out of bounds"
+    v53 = array_get v38, index v51 -> u8
+    v54 = eq v50, v53
+    v55 = not v54
+    jmpif v55 then: b5, else: b6
+  b5():
+    v56 = sub u32 31, v5
+    v57 = array_get v8, index v56 -> u8
+    v58 = sub u32 31, v5
+    v59 = lt v58, u32 32
+    constrain v59 == u1 1, "Index out of bounds"
+    v60 = array_get v38, index v58 -> u8
+    v61 = lt v57, v60
+    constrain v61 == u1 1
+    store u1 1 at v39
+    jmp b6()
+  b6():
+    jmp b7()
+  b7():
+    v63 = unchecked_add v5, u32 1
+    jmp b1(v63)
+}
+acir(inline) fn to_le_radix f8 {
+  b0(v4: Field, v5: u32):
+    call assert_constant(v5)
+    v8 = call to_le_radix(v4, v5) -> [u8; 32]
+    return v8
+}
+acir(inline) fn gt f9 {
+  b0(v4: Field, v5: Field):
+    v8 = eq v4, v5
+    jmpif v8 then: b5, else: b1
+  b1():
+    v10 = call f10(v4, v5) -> u1
+    jmpif v10 then: b3, else: b2
+  b2():
+    call f11(v4, v5)
+    jmp b4(u1 1)
+  b3():
+    call f11(v5, v4)
+    jmp b4(u1 0)
+  b4(v6: u1):
+    jmp b6(v6)
+  b5():
+    jmp b6(u1 0)
+  b6(v7: u1):
+    return v7
+}
+brillig(inline) fn field_less_than f10 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+acir(inline) fn assert_gt f11 {
+  b0(v4: Field, v5: Field):
+    v7, v8 = call f12(v4) -> (Field, Field)
+    v10, v11 = call f12(v5) -> (Field, Field)
+    call f13(v7, v8, v10, v11)
+    return
+}
+acir(inline) fn decompose f12 {
+  b0(v4: Field):
+    v6, v7 = call f16(v4) -> (Field, Field)
+    call f15(v6)
+    call f15(v7)
+    v10 = mul Field 340282366920938463463374607431768211456, v7
+    v11 = add v6, v10
+    v12 = eq v4, v11
+    constrain v4 == v11
+    call f13(Field 53438638232309528389504892708671455233, Field 64323764613183177041862057485226039389, v6, v7)
+    return v6, v7
+}
+acir(inline) fn assert_gt_limbs f13 {
+  b0(v4: Field, v5: Field, v6: Field, v7: Field):
+    v9 = call f14(v4, v6) -> u1
+    v10 = sub v4, v6
+    v12 = sub v10, Field 1
+    v13 = cast v9 as Field
+    v14 = mul v13, Field 340282366920938463463374607431768211456
+    v15 = add v12, v14
+    v16 = sub v5, v7
+    v17 = cast v9 as Field
+    v18 = sub v16, v17
+    call f15(v15)
+    call f15(v18)
+    return
+}
+brillig(inline) fn lte_hint f14 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f10(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+acir(inline) fn assert_max_bit_size f15 {
+  b0(v4: Field):
+    range_check v4 to 128 bits
+    return
+}
+brillig(inline) fn decompose_hint f16 {
+  b0(v4: Field):
+    v6, v7 = call f17(v4) -> (Field, Field)
+    return v6, v7
+}
+brillig(inline) fn compute_decomposition f17 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    store v4 at v5
+    v6 = load v5 -> Field
+    v7 = truncate v6 to 64 bits, max_bit_size: 254
+    v8 = cast v7 as u64
+    v9 = cast v7 as Field
+    v10 = load v5 -> Field
+    v11 = sub v10, v9
+    v12 = div v11, Field 18446744073709551616
+    store v12 at v5
+    v13 = load v5 -> Field
+    v14 = truncate v13 to 64 bits, max_bit_size: 254
+    v15 = cast v14 as u64
+    v16 = cast v14 as Field
+    v17 = load v5 -> Field
+    v18 = sub v17, v16
+    v19 = div v18, Field 18446744073709551616
+    v20 = mul v16, Field 18446744073709551616
+    v21 = add v20, v9
+    return v21, v19
+}
+acir(inline) fn to_be_radix f18 {
+  b0(v4: Field, v5: u32):
+    call assert_constant(v5)
+    v8 = call to_be_radix(v4, v5) -> [u8; 32]
+    return v8
+}
+
+After Defunctionalization:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v6 = allocate -> &mut Field
+    store Field 0 at v6
+    v8 = allocate -> &mut Field
+    store Field 0 at v8
+    v9 = load v6 -> Field
+    v10 = load v6 -> Field
+    v11 = eq v9, v10
+    v13 = unchecked_mul v11, u1 1
+    jmpif v13 then: b1, else: b4
+  b1():
+    v15 = call f1(v4) -> [u8; 32]
+    v17 = call f1(Field 0) -> [u8; 32]
+    v18 = allocate -> &mut [u8; 32]
+    store v17 at v18
+    jmp b2(u32 0)
+  b2(v5: u32):
+    v21 = lt v5, u32 32
+    jmpif v21 then: b7, else: b3
+  b3():
+    v22 = load v18 -> [u8; 32]
+    v24 = call f2(v22) -> Field
+    store v24 at v8
+    jmp b4()
+  b4():
+    v25 = allocate -> &mut Field
+    store Field 0 at v25
+    v27 = call f3(Field 0, v4) -> u1
+    jmpif v27 then: b5, else: b6
+  b5():
+    store Field 1 at v25
+    jmp b6()
+  b6():
+    v29 = load v25 -> Field
+    v30 = load v8 -> Field
+    v31 = sub v29, v30
+    store v31 at v6
+    v32 = load v6 -> Field
+    return v32
+  b7():
+    v33 = load v18 -> [u8; 32]
+    v34 = array_get v15, index v5 -> u8
+    v35 = load v18 -> [u8; 32]
+    v36 = array_get v35, index v5 -> u8
+    v37 = xor v34, v36
+    v38 = array_set v33, index v5, value v37
+    v40 = unchecked_add v5, u32 1
+    store v38 at v18
+    v41 = unchecked_add v5, u32 1
+    jmp b2(v41)
+}
+acir(inline) fn to_be_bytes f1 {
+  b0(v4: Field):
+    v8 = call f18(v4, u32 256) -> [u8; 32]
+    v38 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v39 = allocate -> &mut u1
+    store u1 0 at v39
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v43 = lt v5, u32 32
+    jmpif v43 then: b3, else: b2
+  b2():
+    v44 = load v39 -> u1
+    constrain v44 == u1 1
+    return v8
+  b3():
+    v46 = load v39 -> u1
+    v47 = not v46
+    jmpif v47 then: b4, else: b7
+  b4():
+    v48 = array_get v8, index v5 -> u8
+    v49 = lt v5, u32 32
+    constrain v49 == u1 1, "Index out of bounds"
+    v50 = array_get v38, index v5 -> u8
+    v51 = eq v48, v50
+    v52 = not v51
+    jmpif v52 then: b5, else: b6
+  b5():
+    v53 = array_get v8, index v5 -> u8
+    v54 = lt v5, u32 32
+    constrain v54 == u1 1, "Index out of bounds"
+    v55 = array_get v38, index v5 -> u8
+    v56 = lt v53, v55
+    constrain v56 == u1 1
+    store u1 1 at v39
+    jmp b6()
+  b6():
+    jmp b7()
+  b7():
+    v58 = unchecked_add v5, u32 1
+    jmp b1(v58)
+}
+acir(inline) fn bytes32_to_field f2 {
+  b0(v4: [u8; 32]):
+    v6 = allocate -> &mut Field
+    store Field 1 at v6
+    v8 = allocate -> &mut Field
+    store Field 0 at v8
+    v10 = allocate -> &mut Field
+    store Field 0 at v10
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v13 = lt v5, u32 16
+    jmpif v13 then: b3, else: b2
+  b2():
+    v14 = load v10 -> Field
+    v15 = load v8 -> Field
+    v16 = load v6 -> Field
+    v17 = mul v15, v16
+    v18 = add v14, v17
+    return v18
+  b3():
+    v19 = load v8 -> Field
+    v21 = sub u32 15, v5
+    v22 = array_get v4, index v21 -> u8
+    v23 = cast v22 as Field
+    v24 = load v6 -> Field
+    v25 = mul v23, v24
+    v26 = add v19, v25
+    store v26 at v8
+    v27 = load v10 -> Field
+    v29 = sub u32 31, v5
+    v30 = array_get v4, index v29 -> u8
+    v31 = cast v30 as Field
+    v32 = load v6 -> Field
+    v33 = mul v31, v32
+    v34 = add v27, v33
+    store v34 at v10
+    v35 = load v6 -> Field
+    v37 = mul v35, Field 256
+    store v37 at v6
+    v39 = unchecked_add v5, u32 1
+    jmp b1(v39)
+}
+acir(inline) fn lt f3 {
+  b0(v4: Field, v5: Field):
+    v8 = call f4() -> u1
+    jmpif v8 then: b2, else: b1
+  b1():
+    v10 = call f6(v4, v5) -> u1
+    jmp b3(v10)
+  b2():
+    v12 = call f5(v4, v5) -> u1
+    jmp b3(v12)
+  b3(v6: u1):
+    return v6
+}
+acir(inline) fn is_bn254 f4 {
+  b0():
+    return u1 1
+}
+acir(inline) fn lt f5 {
+  b0(v4: Field, v5: Field):
+    v7 = call f9(v5, v4) -> u1
+    return v7
+}
+acir(inline) fn lt_fallback f6 {
+  b0(v4: Field, v5: Field):
+    v8 = call f7(v4) -> [u8; 32]
+    v10 = call f7(v5) -> [u8; 32]
+    v11 = allocate -> &mut u1
+    store u1 0 at v11
+    v13 = allocate -> &mut u1
+    store u1 0 at v13
+    jmp b1(u32 0)
+  b1(v6: u32):
+    v16 = lt v6, u32 32
+    jmpif v16 then: b3, else: b2
+  b2():
+    v17 = load v11 -> u1
+    return v17
+  b3():
+    v18 = load v13 -> u1
+    v19 = not v18
+    jmpif v19 then: b4, else: b7
+  b4():
+    v21 = sub u32 31, v6
+    v22 = array_get v8, index v21 -> u8
+    v23 = sub u32 31, v6
+    v24 = array_get v10, index v23 -> u8
+    v25 = eq v22, v24
+    v26 = not v25
+    jmpif v26 then: b5, else: b6
+  b5():
+    v27 = lt v22, v24
+    store v27 at v11
+    store u1 1 at v13
+    jmp b6()
+  b6():
+    jmp b7()
+  b7():
+    v30 = unchecked_add v6, u32 1
+    jmp b1(v30)
+}
+acir(inline) fn to_le_bytes f7 {
+  b0(v4: Field):
+    v8 = call f8(v4, u32 256) -> [u8; 32]
+    v38 = make_array [u8 1, u8 0, u8 0, u8 240, u8 147, u8 245, u8 225, u8 67, u8 145, u8 112, u8 185, u8 121, u8 72, u8 232, u8 51, u8 40, u8 93, u8 88, u8 129, u8 129, u8 182, u8 69, u8 80, u8 184, u8 41, u8 160, u8 49, u8 225, u8 114, u8 78, u8 100, u8 48] : [u8]
+    v39 = allocate -> &mut u1
+    store u1 0 at v39
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v43 = lt v5, u32 32
+    jmpif v43 then: b3, else: b2
+  b2():
+    v44 = load v39 -> u1
+    constrain v44 == u1 1
+    return v8
+  b3():
+    v46 = load v39 -> u1
+    v47 = not v46
+    jmpif v47 then: b4, else: b7
+  b4():
+    v49 = sub u32 31, v5
+    v50 = array_get v8, index v49 -> u8
+    v51 = sub u32 31, v5
+    v52 = lt v51, u32 32
+    constrain v52 == u1 1, "Index out of bounds"
+    v53 = array_get v38, index v51 -> u8
+    v54 = eq v50, v53
+    v55 = not v54
+    jmpif v55 then: b5, else: b6
+  b5():
+    v56 = sub u32 31, v5
+    v57 = array_get v8, index v56 -> u8
+    v58 = sub u32 31, v5
+    v59 = lt v58, u32 32
+    constrain v59 == u1 1, "Index out of bounds"
+    v60 = array_get v38, index v58 -> u8
+    v61 = lt v57, v60
+    constrain v61 == u1 1
+    store u1 1 at v39
+    jmp b6()
+  b6():
+    jmp b7()
+  b7():
+    v63 = unchecked_add v5, u32 1
+    jmp b1(v63)
+}
+acir(inline) fn to_le_radix f8 {
+  b0(v4: Field, v5: u32):
+    call assert_constant(v5)
+    v8 = call to_le_radix(v4, v5) -> [u8; 32]
+    return v8
+}
+acir(inline) fn gt f9 {
+  b0(v4: Field, v5: Field):
+    v8 = eq v4, v5
+    jmpif v8 then: b5, else: b1
+  b1():
+    v10 = call f10(v4, v5) -> u1
+    jmpif v10 then: b3, else: b2
+  b2():
+    call f11(v4, v5)
+    jmp b4(u1 1)
+  b3():
+    call f11(v5, v4)
+    jmp b4(u1 0)
+  b4(v6: u1):
+    jmp b6(v6)
+  b5():
+    jmp b6(u1 0)
+  b6(v7: u1):
+    return v7
+}
+brillig(inline) fn field_less_than f10 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+acir(inline) fn assert_gt f11 {
+  b0(v4: Field, v5: Field):
+    v7, v8 = call f12(v4) -> (Field, Field)
+    v10, v11 = call f12(v5) -> (Field, Field)
+    call f13(v7, v8, v10, v11)
+    return
+}
+acir(inline) fn decompose f12 {
+  b0(v4: Field):
+    v6, v7 = call f16(v4) -> (Field, Field)
+    call f15(v6)
+    call f15(v7)
+    v10 = mul Field 340282366920938463463374607431768211456, v7
+    v11 = add v6, v10
+    v12 = eq v4, v11
+    constrain v4 == v11
+    call f13(Field 53438638232309528389504892708671455233, Field 64323764613183177041862057485226039389, v6, v7)
+    return v6, v7
+}
+acir(inline) fn assert_gt_limbs f13 {
+  b0(v4: Field, v5: Field, v6: Field, v7: Field):
+    v9 = call f14(v4, v6) -> u1
+    v10 = sub v4, v6
+    v12 = sub v10, Field 1
+    v13 = cast v9 as Field
+    v14 = mul v13, Field 340282366920938463463374607431768211456
+    v15 = add v12, v14
+    v16 = sub v5, v7
+    v17 = cast v9 as Field
+    v18 = sub v16, v17
+    call f15(v15)
+    call f15(v18)
+    return
+}
+brillig(inline) fn lte_hint f14 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f10(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+acir(inline) fn assert_max_bit_size f15 {
+  b0(v4: Field):
+    range_check v4 to 128 bits
+    return
+}
+brillig(inline) fn decompose_hint f16 {
+  b0(v4: Field):
+    v6, v7 = call f17(v4) -> (Field, Field)
+    return v6, v7
+}
+brillig(inline) fn compute_decomposition f17 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    store v4 at v5
+    v6 = load v5 -> Field
+    v7 = truncate v6 to 64 bits, max_bit_size: 254
+    v8 = cast v7 as u64
+    v9 = cast v7 as Field
+    v10 = load v5 -> Field
+    v11 = sub v10, v9
+    v12 = div v11, Field 18446744073709551616
+    store v12 at v5
+    v13 = load v5 -> Field
+    v14 = truncate v13 to 64 bits, max_bit_size: 254
+    v15 = cast v14 as u64
+    v16 = cast v14 as Field
+    v17 = load v5 -> Field
+    v18 = sub v17, v16
+    v19 = div v18, Field 18446744073709551616
+    v20 = mul v16, Field 18446744073709551616
+    v21 = add v20, v9
+    return v21, v19
+}
+acir(inline) fn to_be_radix f18 {
+  b0(v4: Field, v5: u32):
+    call assert_constant(v5)
+    v8 = call to_be_radix(v4, v5) -> [u8; 32]
+    return v8
+}
+
+After Removing Paired rc_inc & rc_decs:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v6 = allocate -> &mut Field
+    store Field 0 at v6
+    v8 = allocate -> &mut Field
+    store Field 0 at v8
+    v9 = load v6 -> Field
+    v10 = load v6 -> Field
+    v11 = eq v9, v10
+    v13 = unchecked_mul v11, u1 1
+    jmpif v13 then: b1, else: b4
+  b1():
+    v15 = call f1(v4) -> [u8; 32]
+    v17 = call f1(Field 0) -> [u8; 32]
+    v18 = allocate -> &mut [u8; 32]
+    store v17 at v18
+    jmp b2(u32 0)
+  b2(v5: u32):
+    v21 = lt v5, u32 32
+    jmpif v21 then: b7, else: b3
+  b3():
+    v22 = load v18 -> [u8; 32]
+    v24 = call f2(v22) -> Field
+    store v24 at v8
+    jmp b4()
+  b4():
+    v25 = allocate -> &mut Field
+    store Field 0 at v25
+    v27 = call f3(Field 0, v4) -> u1
+    jmpif v27 then: b5, else: b6
+  b5():
+    store Field 1 at v25
+    jmp b6()
+  b6():
+    v29 = load v25 -> Field
+    v30 = load v8 -> Field
+    v31 = sub v29, v30
+    store v31 at v6
+    v32 = load v6 -> Field
+    return v32
+  b7():
+    v33 = load v18 -> [u8; 32]
+    v34 = array_get v15, index v5 -> u8
+    v35 = load v18 -> [u8; 32]
+    v36 = array_get v35, index v5 -> u8
+    v37 = xor v34, v36
+    v38 = array_set v33, index v5, value v37
+    v40 = unchecked_add v5, u32 1
+    store v38 at v18
+    v41 = unchecked_add v5, u32 1
+    jmp b2(v41)
+}
+acir(inline) fn to_be_bytes f1 {
+  b0(v4: Field):
+    v8 = call f18(v4, u32 256) -> [u8; 32]
+    v38 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v39 = allocate -> &mut u1
+    store u1 0 at v39
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v43 = lt v5, u32 32
+    jmpif v43 then: b3, else: b2
+  b2():
+    v44 = load v39 -> u1
+    constrain v44 == u1 1
+    return v8
+  b3():
+    v46 = load v39 -> u1
+    v47 = not v46
+    jmpif v47 then: b4, else: b7
+  b4():
+    v48 = array_get v8, index v5 -> u8
+    v49 = lt v5, u32 32
+    constrain v49 == u1 1, "Index out of bounds"
+    v50 = array_get v38, index v5 -> u8
+    v51 = eq v48, v50
+    v52 = not v51
+    jmpif v52 then: b5, else: b6
+  b5():
+    v53 = array_get v8, index v5 -> u8
+    v54 = lt v5, u32 32
+    constrain v54 == u1 1, "Index out of bounds"
+    v55 = array_get v38, index v5 -> u8
+    v56 = lt v53, v55
+    constrain v56 == u1 1
+    store u1 1 at v39
+    jmp b6()
+  b6():
+    jmp b7()
+  b7():
+    v58 = unchecked_add v5, u32 1
+    jmp b1(v58)
+}
+acir(inline) fn bytes32_to_field f2 {
+  b0(v4: [u8; 32]):
+    v6 = allocate -> &mut Field
+    store Field 1 at v6
+    v8 = allocate -> &mut Field
+    store Field 0 at v8
+    v10 = allocate -> &mut Field
+    store Field 0 at v10
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v13 = lt v5, u32 16
+    jmpif v13 then: b3, else: b2
+  b2():
+    v14 = load v10 -> Field
+    v15 = load v8 -> Field
+    v16 = load v6 -> Field
+    v17 = mul v15, v16
+    v18 = add v14, v17
+    return v18
+  b3():
+    v19 = load v8 -> Field
+    v21 = sub u32 15, v5
+    v22 = array_get v4, index v21 -> u8
+    v23 = cast v22 as Field
+    v24 = load v6 -> Field
+    v25 = mul v23, v24
+    v26 = add v19, v25
+    store v26 at v8
+    v27 = load v10 -> Field
+    v29 = sub u32 31, v5
+    v30 = array_get v4, index v29 -> u8
+    v31 = cast v30 as Field
+    v32 = load v6 -> Field
+    v33 = mul v31, v32
+    v34 = add v27, v33
+    store v34 at v10
+    v35 = load v6 -> Field
+    v37 = mul v35, Field 256
+    store v37 at v6
+    v39 = unchecked_add v5, u32 1
+    jmp b1(v39)
+}
+acir(inline) fn lt f3 {
+  b0(v4: Field, v5: Field):
+    v8 = call f4() -> u1
+    jmpif v8 then: b2, else: b1
+  b1():
+    v10 = call f6(v4, v5) -> u1
+    jmp b3(v10)
+  b2():
+    v12 = call f5(v4, v5) -> u1
+    jmp b3(v12)
+  b3(v6: u1):
+    return v6
+}
+acir(inline) fn is_bn254 f4 {
+  b0():
+    return u1 1
+}
+acir(inline) fn lt f5 {
+  b0(v4: Field, v5: Field):
+    v7 = call f9(v5, v4) -> u1
+    return v7
+}
+acir(inline) fn lt_fallback f6 {
+  b0(v4: Field, v5: Field):
+    v8 = call f7(v4) -> [u8; 32]
+    v10 = call f7(v5) -> [u8; 32]
+    v11 = allocate -> &mut u1
+    store u1 0 at v11
+    v13 = allocate -> &mut u1
+    store u1 0 at v13
+    jmp b1(u32 0)
+  b1(v6: u32):
+    v16 = lt v6, u32 32
+    jmpif v16 then: b3, else: b2
+  b2():
+    v17 = load v11 -> u1
+    return v17
+  b3():
+    v18 = load v13 -> u1
+    v19 = not v18
+    jmpif v19 then: b4, else: b7
+  b4():
+    v21 = sub u32 31, v6
+    v22 = array_get v8, index v21 -> u8
+    v23 = sub u32 31, v6
+    v24 = array_get v10, index v23 -> u8
+    v25 = eq v22, v24
+    v26 = not v25
+    jmpif v26 then: b5, else: b6
+  b5():
+    v27 = lt v22, v24
+    store v27 at v11
+    store u1 1 at v13
+    jmp b6()
+  b6():
+    jmp b7()
+  b7():
+    v30 = unchecked_add v6, u32 1
+    jmp b1(v30)
+}
+acir(inline) fn to_le_bytes f7 {
+  b0(v4: Field):
+    v8 = call f8(v4, u32 256) -> [u8; 32]
+    v38 = make_array [u8 1, u8 0, u8 0, u8 240, u8 147, u8 245, u8 225, u8 67, u8 145, u8 112, u8 185, u8 121, u8 72, u8 232, u8 51, u8 40, u8 93, u8 88, u8 129, u8 129, u8 182, u8 69, u8 80, u8 184, u8 41, u8 160, u8 49, u8 225, u8 114, u8 78, u8 100, u8 48] : [u8]
+    v39 = allocate -> &mut u1
+    store u1 0 at v39
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v43 = lt v5, u32 32
+    jmpif v43 then: b3, else: b2
+  b2():
+    v44 = load v39 -> u1
+    constrain v44 == u1 1
+    return v8
+  b3():
+    v46 = load v39 -> u1
+    v47 = not v46
+    jmpif v47 then: b4, else: b7
+  b4():
+    v49 = sub u32 31, v5
+    v50 = array_get v8, index v49 -> u8
+    v51 = sub u32 31, v5
+    v52 = lt v51, u32 32
+    constrain v52 == u1 1, "Index out of bounds"
+    v53 = array_get v38, index v51 -> u8
+    v54 = eq v50, v53
+    v55 = not v54
+    jmpif v55 then: b5, else: b6
+  b5():
+    v56 = sub u32 31, v5
+    v57 = array_get v8, index v56 -> u8
+    v58 = sub u32 31, v5
+    v59 = lt v58, u32 32
+    constrain v59 == u1 1, "Index out of bounds"
+    v60 = array_get v38, index v58 -> u8
+    v61 = lt v57, v60
+    constrain v61 == u1 1
+    store u1 1 at v39
+    jmp b6()
+  b6():
+    jmp b7()
+  b7():
+    v63 = unchecked_add v5, u32 1
+    jmp b1(v63)
+}
+acir(inline) fn to_le_radix f8 {
+  b0(v4: Field, v5: u32):
+    call assert_constant(v5)
+    v8 = call to_le_radix(v4, v5) -> [u8; 32]
+    return v8
+}
+acir(inline) fn gt f9 {
+  b0(v4: Field, v5: Field):
+    v8 = eq v4, v5
+    jmpif v8 then: b5, else: b1
+  b1():
+    v10 = call f10(v4, v5) -> u1
+    jmpif v10 then: b3, else: b2
+  b2():
+    call f11(v4, v5)
+    jmp b4(u1 1)
+  b3():
+    call f11(v5, v4)
+    jmp b4(u1 0)
+  b4(v6: u1):
+    jmp b6(v6)
+  b5():
+    jmp b6(u1 0)
+  b6(v7: u1):
+    return v7
+}
+brillig(inline) fn field_less_than f10 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+acir(inline) fn assert_gt f11 {
+  b0(v4: Field, v5: Field):
+    v7, v8 = call f12(v4) -> (Field, Field)
+    v10, v11 = call f12(v5) -> (Field, Field)
+    call f13(v7, v8, v10, v11)
+    return
+}
+acir(inline) fn decompose f12 {
+  b0(v4: Field):
+    v6, v7 = call f16(v4) -> (Field, Field)
+    call f15(v6)
+    call f15(v7)
+    v10 = mul Field 340282366920938463463374607431768211456, v7
+    v11 = add v6, v10
+    v12 = eq v4, v11
+    constrain v4 == v11
+    call f13(Field 53438638232309528389504892708671455233, Field 64323764613183177041862057485226039389, v6, v7)
+    return v6, v7
+}
+acir(inline) fn assert_gt_limbs f13 {
+  b0(v4: Field, v5: Field, v6: Field, v7: Field):
+    v9 = call f14(v4, v6) -> u1
+    v10 = sub v4, v6
+    v12 = sub v10, Field 1
+    v13 = cast v9 as Field
+    v14 = mul v13, Field 340282366920938463463374607431768211456
+    v15 = add v12, v14
+    v16 = sub v5, v7
+    v17 = cast v9 as Field
+    v18 = sub v16, v17
+    call f15(v15)
+    call f15(v18)
+    return
+}
+brillig(inline) fn lte_hint f14 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f10(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+acir(inline) fn assert_max_bit_size f15 {
+  b0(v4: Field):
+    range_check v4 to 128 bits
+    return
+}
+brillig(inline) fn decompose_hint f16 {
+  b0(v4: Field):
+    v6, v7 = call f17(v4) -> (Field, Field)
+    return v6, v7
+}
+brillig(inline) fn compute_decomposition f17 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    store v4 at v5
+    v6 = load v5 -> Field
+    v7 = truncate v6 to 64 bits, max_bit_size: 254
+    v8 = cast v7 as u64
+    v9 = cast v7 as Field
+    v10 = load v5 -> Field
+    v11 = sub v10, v9
+    v12 = div v11, Field 18446744073709551616
+    store v12 at v5
+    v13 = load v5 -> Field
+    v14 = truncate v13 to 64 bits, max_bit_size: 254
+    v15 = cast v14 as u64
+    v16 = cast v14 as Field
+    v17 = load v5 -> Field
+    v18 = sub v17, v16
+    v19 = div v18, Field 18446744073709551616
+    v20 = mul v16, Field 18446744073709551616
+    v21 = add v20, v9
+    return v21, v19
+}
+acir(inline) fn to_be_radix f18 {
+  b0(v4: Field, v5: u32):
+    call assert_constant(v5)
+    v8 = call to_be_radix(v4, v5) -> [u8; 32]
+    return v8
+}
+
+After Inlining (1st):
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v12 = allocate -> &mut Field
+    store Field 0 at v12
+    v14 = allocate -> &mut Field
+    store Field 0 at v14
+    v15 = load v12 -> Field
+    v16 = load v12 -> Field
+    v17 = eq v15, v16
+    jmpif v17 then: b1, else: b10
+  b1():
+    v20 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v50 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v51 = allocate -> &mut u1
+    store u1 0 at v51
+    jmp b2(u32 0)
+  b2(v5: u32):
+    v55 = lt v5, u32 32
+    jmpif v55 then: b28, else: b3
+  b3():
+    v56 = load v51 -> u1
+    constrain v56 == u1 1
+    v58 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v59 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v60 = allocate -> &mut u1
+    store u1 0 at v60
+    jmp b4(u32 0)
+  b4(v6: u32):
+    v61 = lt v6, u32 32
+    jmpif v61 then: b23, else: b5
+  b5():
+    v62 = load v60 -> u1
+    constrain v62 == u1 1
+    v63 = allocate -> &mut [u8; 32]
+    store v58 at v63
+    jmp b6(u32 0)
+  b6(v7: u32):
+    v64 = lt v7, u32 32
+    jmpif v64 then: b22, else: b7
+  b7():
+    v65 = load v63 -> [u8; 32]
+    v66 = allocate -> &mut Field
+    store Field 1 at v66
+    v68 = allocate -> &mut Field
+    store Field 0 at v68
+    v69 = allocate -> &mut Field
+    store Field 0 at v69
+    jmp b8(u32 0)
+  b8(v8: u32):
+    v71 = lt v8, u32 16
+    jmpif v71 then: b21, else: b9
+  b9():
+    v72 = load v69 -> Field
+    v73 = load v68 -> Field
+    v74 = load v66 -> Field
+    v75 = mul v73, v74
+    v76 = add v72, v75
+    store v76 at v14
+    jmp b10()
+  b10():
+    v77 = allocate -> &mut Field
+    store Field 0 at v77
+    jmp b11()
+  b11():
+    v78 = eq v4, Field 0
+    jmpif v78 then: b16, else: b12
+  b12():
+    v80 = call f1(v4, Field 0) -> u1
+    jmpif v80 then: b14, else: b13
+  b13():
+    v82, v83 = call f3(v4) -> (Field, Field)
+    range_check v82 to 128 bits
+    range_check v83 to 128 bits
+    v85 = mul Field 340282366920938463463374607431768211456, v83
+    v86 = add v82, v85
+    v87 = eq v4, v86
+    constrain v4 == v86
+    v90 = call f2(Field 53438638232309528389504892708671455233, v82) -> u1
+    v91 = sub Field 53438638232309528389504892708671455233, v82
+    v92 = sub v91, Field 1
+    v93 = cast v90 as Field
+    v94 = mul v93, Field 340282366920938463463374607431768211456
+    v95 = add v92, v94
+    v97 = sub Field 64323764613183177041862057485226039389, v83
+    v98 = cast v90 as Field
+    v99 = sub v97, v98
+    range_check v95 to 128 bits
+    range_check v99 to 128 bits
+    v101, v102 = call f3(Field 0) -> (Field, Field)
+    range_check v101 to 128 bits
+    range_check v102 to 128 bits
+    v103 = mul Field 340282366920938463463374607431768211456, v102
+    v104 = add v101, v103
+    v105 = eq Field 0, v104
+    constrain Field 0 == v104
+    v107 = call f2(Field 53438638232309528389504892708671455233, v101) -> u1
+    v108 = sub Field 53438638232309528389504892708671455233, v101
+    v109 = sub v108, Field 1
+    v110 = cast v107 as Field
+    v111 = mul v110, Field 340282366920938463463374607431768211456
+    v112 = add v109, v111
+    v113 = sub Field 64323764613183177041862057485226039389, v102
+    v114 = cast v107 as Field
+    v115 = sub v113, v114
+    range_check v112 to 128 bits
+    range_check v115 to 128 bits
+    v117 = call f2(v82, v101) -> u1
+    v118 = sub v82, v101
+    v119 = sub v118, Field 1
+    v120 = cast v117 as Field
+    v121 = mul v120, Field 340282366920938463463374607431768211456
+    v122 = add v119, v121
+    v123 = sub v83, v102
+    v124 = cast v117 as Field
+    v125 = sub v123, v124
+    range_check v122 to 128 bits
+    range_check v125 to 128 bits
+    jmp b15(u1 1)
+  b14():
+    v127, v128 = call f3(Field 0) -> (Field, Field)
+    range_check v127 to 128 bits
+    range_check v128 to 128 bits
+    v129 = mul Field 340282366920938463463374607431768211456, v128
+    v130 = add v127, v129
+    v131 = eq Field 0, v130
+    constrain Field 0 == v130
+    v133 = call f2(Field 53438638232309528389504892708671455233, v127) -> u1
+    v134 = sub Field 53438638232309528389504892708671455233, v127
+    v135 = sub v134, Field 1
+    v136 = cast v133 as Field
+    v137 = mul v136, Field 340282366920938463463374607431768211456
+    v138 = add v135, v137
+    v139 = sub Field 64323764613183177041862057485226039389, v128
+    v140 = cast v133 as Field
+    v141 = sub v139, v140
+    range_check v138 to 128 bits
+    range_check v141 to 128 bits
+    v143, v144 = call f3(v4) -> (Field, Field)
+    range_check v143 to 128 bits
+    range_check v144 to 128 bits
+    v145 = mul Field 340282366920938463463374607431768211456, v144
+    v146 = add v143, v145
+    v147 = eq v4, v146
+    constrain v4 == v146
+    v149 = call f2(Field 53438638232309528389504892708671455233, v143) -> u1
+    v150 = sub Field 53438638232309528389504892708671455233, v143
+    v151 = sub v150, Field 1
+    v152 = cast v149 as Field
+    v153 = mul v152, Field 340282366920938463463374607431768211456
+    v154 = add v151, v153
+    v155 = sub Field 64323764613183177041862057485226039389, v144
+    v156 = cast v149 as Field
+    v157 = sub v155, v156
+    range_check v154 to 128 bits
+    range_check v157 to 128 bits
+    v159 = call f2(v127, v143) -> u1
+    v160 = sub v127, v143
+    v161 = sub v160, Field 1
+    v162 = cast v159 as Field
+    v163 = mul v162, Field 340282366920938463463374607431768211456
+    v164 = add v161, v163
+    v165 = sub v128, v144
+    v166 = cast v159 as Field
+    v167 = sub v165, v166
+    range_check v164 to 128 bits
+    range_check v167 to 128 bits
+    jmp b15(u1 0)
+  b15(v9: u1):
+    jmp b17(v9)
+  b16():
+    jmp b17(u1 0)
+  b17(v10: u1):
+    jmp b18(v10)
+  b18(v11: u1):
+    jmpif v11 then: b19, else: b20
+  b19():
+    store Field 1 at v77
+    jmp b20()
+  b20():
+    v168 = load v77 -> Field
+    v169 = load v14 -> Field
+    v170 = sub v168, v169
+    store v170 at v12
+    v171 = load v12 -> Field
+    return v171
+  b21():
+    v172 = load v68 -> Field
+    v174 = sub u32 15, v8
+    v175 = array_get v65, index v174 -> u8
+    v176 = cast v175 as Field
+    v177 = load v66 -> Field
+    v178 = mul v176, v177
+    v179 = add v172, v178
+    store v179 at v68
+    v180 = load v69 -> Field
+    v182 = sub u32 31, v8
+    v183 = array_get v65, index v182 -> u8
+    v184 = cast v183 as Field
+    v185 = load v66 -> Field
+    v186 = mul v184, v185
+    v187 = add v180, v186
+    store v187 at v69
+    v188 = load v66 -> Field
+    v190 = mul v188, Field 256
+    store v190 at v66
+    v192 = unchecked_add v8, u32 1
+    jmp b8(v192)
+  b22():
+    v193 = load v63 -> [u8; 32]
+    v194 = array_get v20, index v7 -> u8
+    v195 = load v63 -> [u8; 32]
+    v196 = array_get v195, index v7 -> u8
+    v197 = xor v194, v196
+    v198 = array_set v193, index v7, value v197
+    v199 = unchecked_add v7, u32 1
+    store v198 at v63
+    v200 = unchecked_add v7, u32 1
+    jmp b6(v200)
+  b23():
+    v201 = load v60 -> u1
+    v202 = not v201
+    jmpif v202 then: b24, else: b27
+  b24():
+    v203 = array_get v58, index v6 -> u8
+    v204 = lt v6, u32 32
+    constrain v204 == u1 1, "Index out of bounds"
+    v205 = array_get v59, index v6 -> u8
+    v206 = eq v203, v205
+    v207 = not v206
+    jmpif v207 then: b25, else: b26
+  b25():
+    v208 = array_get v58, index v6 -> u8
+    v209 = lt v6, u32 32
+    constrain v209 == u1 1, "Index out of bounds"
+    v210 = array_get v59, index v6 -> u8
+    v211 = lt v208, v210
+    constrain v211 == u1 1
+    store u1 1 at v60
+    jmp b26()
+  b26():
+    jmp b27()
+  b27():
+    v212 = unchecked_add v6, u32 1
+    jmp b4(v212)
+  b28():
+    v213 = load v51 -> u1
+    v214 = not v213
+    jmpif v214 then: b29, else: b32
+  b29():
+    v215 = array_get v20, index v5 -> u8
+    v216 = lt v5, u32 32
+    constrain v216 == u1 1, "Index out of bounds"
+    v217 = array_get v50, index v5 -> u8
+    v218 = eq v215, v217
+    v219 = not v218
+    jmpif v219 then: b30, else: b31
+  b30():
+    v220 = array_get v20, index v5 -> u8
+    v221 = lt v5, u32 32
+    constrain v221 == u1 1, "Index out of bounds"
+    v222 = array_get v50, index v5 -> u8
+    v223 = lt v220, v222
+    constrain v223 == u1 1
+    store u1 1 at v51
+    jmp b31()
+  b31():
+    jmp b32()
+  b32():
+    v224 = unchecked_add v5, u32 1
+    jmp b2(v224)
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    store v4 at v5
+    v6 = load v5 -> Field
+    v7 = truncate v6 to 64 bits, max_bit_size: 254
+    v8 = cast v7 as u64
+    v9 = load v5 -> Field
+    v10 = sub v9, v7
+    v11 = div v10, Field 18446744073709551616
+    store v11 at v5
+    v12 = load v5 -> Field
+    v13 = truncate v12 to 64 bits, max_bit_size: 254
+    v14 = cast v13 as u64
+    v15 = load v5 -> Field
+    v16 = sub v15, v13
+    v17 = div v16, Field 18446744073709551616
+    v18 = mul v13, Field 18446744073709551616
+    v19 = add v18, v7
+    return v19, v17
+}
+
+After Mem2Reg (1st):
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v12 = allocate -> &mut Field
+    v13 = allocate -> &mut Field
+    store Field 0 at v13
+    jmpif u1 1 then: b1, else: b10
+  b1():
+    v18 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v48 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v49 = allocate -> &mut u1
+    store u1 0 at v49
+    jmp b2(u32 0)
+  b2(v5: u32):
+    v53 = lt v5, u32 32
+    jmpif v53 then: b28, else: b3
+  b3():
+    v54 = load v49 -> u1
+    constrain v54 == u1 1
+    v55 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v56 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v57 = allocate -> &mut u1
+    store u1 0 at v57
+    jmp b4(u32 0)
+  b4(v6: u32):
+    v58 = lt v6, u32 32
+    jmpif v58 then: b23, else: b5
+  b5():
+    v59 = load v57 -> u1
+    constrain v59 == u1 1
+    v60 = allocate -> &mut [u8; 32]
+    store v55 at v60
+    jmp b6(u32 0)
+  b6(v7: u32):
+    v61 = lt v7, u32 32
+    jmpif v61 then: b22, else: b7
+  b7():
+    v62 = load v60 -> [u8; 32]
+    v63 = allocate -> &mut Field
+    store Field 1 at v63
+    v65 = allocate -> &mut Field
+    store Field 0 at v65
+    v66 = allocate -> &mut Field
+    store Field 0 at v66
+    jmp b8(u32 0)
+  b8(v8: u32):
+    v68 = lt v8, u32 16
+    jmpif v68 then: b21, else: b9
+  b9():
+    v69 = load v66 -> Field
+    v70 = load v65 -> Field
+    v71 = load v63 -> Field
+    v72 = mul v70, v71
+    v73 = add v69, v72
+    store v73 at v13
+    jmp b10()
+  b10():
+    v74 = allocate -> &mut Field
+    store Field 0 at v74
+    jmp b11()
+  b11():
+    v75 = eq v4, Field 0
+    jmpif v75 then: b16, else: b12
+  b12():
+    v77 = call f1(v4, Field 0) -> u1
+    jmpif v77 then: b14, else: b13
+  b13():
+    v79, v80 = call f3(v4) -> (Field, Field)
+    range_check v79 to 128 bits
+    range_check v80 to 128 bits
+    v82 = mul Field 340282366920938463463374607431768211456, v80
+    v83 = add v79, v82
+    v84 = eq v4, v83
+    constrain v4 == v83
+    v87 = call f2(Field 53438638232309528389504892708671455233, v79) -> u1
+    v88 = sub Field 53438638232309528389504892708671455233, v79
+    v89 = sub v88, Field 1
+    v90 = cast v87 as Field
+    v91 = mul v90, Field 340282366920938463463374607431768211456
+    v92 = add v89, v91
+    v94 = sub Field 64323764613183177041862057485226039389, v80
+    v95 = cast v87 as Field
+    v96 = sub v94, v95
+    range_check v92 to 128 bits
+    range_check v96 to 128 bits
+    v98, v99 = call f3(Field 0) -> (Field, Field)
+    range_check v98 to 128 bits
+    range_check v99 to 128 bits
+    v100 = mul Field 340282366920938463463374607431768211456, v99
+    v101 = add v98, v100
+    v102 = eq Field 0, v101
+    constrain Field 0 == v101
+    v104 = call f2(Field 53438638232309528389504892708671455233, v98) -> u1
+    v105 = sub Field 53438638232309528389504892708671455233, v98
+    v106 = sub v105, Field 1
+    v107 = cast v104 as Field
+    v108 = mul v107, Field 340282366920938463463374607431768211456
+    v109 = add v106, v108
+    v110 = sub Field 64323764613183177041862057485226039389, v99
+    v111 = cast v104 as Field
+    v112 = sub v110, v111
+    range_check v109 to 128 bits
+    range_check v112 to 128 bits
+    v114 = call f2(v79, v98) -> u1
+    v115 = sub v79, v98
+    v116 = sub v115, Field 1
+    v117 = cast v114 as Field
+    v118 = mul v117, Field 340282366920938463463374607431768211456
+    v119 = add v116, v118
+    v120 = sub v80, v99
+    v121 = cast v114 as Field
+    v122 = sub v120, v121
+    range_check v119 to 128 bits
+    range_check v122 to 128 bits
+    jmp b15(u1 1)
+  b14():
+    v124, v125 = call f3(Field 0) -> (Field, Field)
+    range_check v124 to 128 bits
+    range_check v125 to 128 bits
+    v126 = mul Field 340282366920938463463374607431768211456, v125
+    v127 = add v124, v126
+    v128 = eq Field 0, v127
+    constrain Field 0 == v127
+    v130 = call f2(Field 53438638232309528389504892708671455233, v124) -> u1
+    v131 = sub Field 53438638232309528389504892708671455233, v124
+    v132 = sub v131, Field 1
+    v133 = cast v130 as Field
+    v134 = mul v133, Field 340282366920938463463374607431768211456
+    v135 = add v132, v134
+    v136 = sub Field 64323764613183177041862057485226039389, v125
+    v137 = cast v130 as Field
+    v138 = sub v136, v137
+    range_check v135 to 128 bits
+    range_check v138 to 128 bits
+    v140, v141 = call f3(v4) -> (Field, Field)
+    range_check v140 to 128 bits
+    range_check v141 to 128 bits
+    v142 = mul Field 340282366920938463463374607431768211456, v141
+    v143 = add v140, v142
+    v144 = eq v4, v143
+    constrain v4 == v143
+    v146 = call f2(Field 53438638232309528389504892708671455233, v140) -> u1
+    v147 = sub Field 53438638232309528389504892708671455233, v140
+    v148 = sub v147, Field 1
+    v149 = cast v146 as Field
+    v150 = mul v149, Field 340282366920938463463374607431768211456
+    v151 = add v148, v150
+    v152 = sub Field 64323764613183177041862057485226039389, v141
+    v153 = cast v146 as Field
+    v154 = sub v152, v153
+    range_check v151 to 128 bits
+    range_check v154 to 128 bits
+    v156 = call f2(v124, v140) -> u1
+    v157 = sub v124, v140
+    v158 = sub v157, Field 1
+    v159 = cast v156 as Field
+    v160 = mul v159, Field 340282366920938463463374607431768211456
+    v161 = add v158, v160
+    v162 = sub v125, v141
+    v163 = cast v156 as Field
+    v164 = sub v162, v163
+    range_check v161 to 128 bits
+    range_check v164 to 128 bits
+    jmp b15(u1 0)
+  b15(v9: u1):
+    jmp b17(v9)
+  b16():
+    jmp b17(u1 0)
+  b17(v10: u1):
+    jmp b18(v10)
+  b18(v11: u1):
+    jmpif v11 then: b19, else: b20
+  b19():
+    store Field 1 at v74
+    jmp b20()
+  b20():
+    v165 = load v74 -> Field
+    v166 = load v13 -> Field
+    v167 = sub v165, v166
+    return v167
+  b21():
+    v168 = load v65 -> Field
+    v170 = sub u32 15, v8
+    v171 = array_get v62, index v170 -> u8
+    v172 = cast v171 as Field
+    v173 = load v63 -> Field
+    v174 = mul v172, v173
+    v175 = add v168, v174
+    store v175 at v65
+    v176 = load v66 -> Field
+    v178 = sub u32 31, v8
+    v179 = array_get v62, index v178 -> u8
+    v180 = cast v179 as Field
+    v181 = mul v180, v173
+    v182 = add v176, v181
+    store v182 at v66
+    v184 = mul v173, Field 256
+    store v184 at v63
+    v186 = unchecked_add v8, u32 1
+    jmp b8(v186)
+  b22():
+    v187 = load v60 -> [u8; 32]
+    v188 = array_get v18, index v7 -> u8
+    v189 = array_get v187, index v7 -> u8
+    v190 = xor v188, v189
+    v191 = array_set v187, index v7, value v190
+    v192 = unchecked_add v7, u32 1
+    store v191 at v60
+    v193 = unchecked_add v7, u32 1
+    jmp b6(v193)
+  b23():
+    v194 = load v57 -> u1
+    v195 = not v194
+    jmpif v195 then: b24, else: b27
+  b24():
+    v196 = array_get v55, index v6 -> u8
+    v197 = lt v6, u32 32
+    constrain v197 == u1 1, "Index out of bounds"
+    v198 = array_get v56, index v6 -> u8
+    v199 = eq v196, v198
+    v200 = not v199
+    jmpif v200 then: b25, else: b26
+  b25():
+    v201 = array_get v55, index v6 -> u8
+    v202 = lt v6, u32 32
+    constrain v202 == u1 1, "Index out of bounds"
+    v203 = array_get v56, index v6 -> u8
+    v204 = lt v201, v203
+    constrain v204 == u1 1
+    store u1 1 at v57
+    jmp b26()
+  b26():
+    jmp b27()
+  b27():
+    v205 = unchecked_add v6, u32 1
+    jmp b4(v205)
+  b28():
+    v206 = load v49 -> u1
+    v207 = not v206
+    jmpif v207 then: b29, else: b32
+  b29():
+    v208 = array_get v18, index v5 -> u8
+    v209 = lt v5, u32 32
+    constrain v209 == u1 1, "Index out of bounds"
+    v210 = array_get v48, index v5 -> u8
+    v211 = eq v208, v210
+    v212 = not v211
+    jmpif v212 then: b30, else: b31
+  b30():
+    v213 = array_get v18, index v5 -> u8
+    v214 = lt v5, u32 32
+    constrain v214 == u1 1, "Index out of bounds"
+    v215 = array_get v48, index v5 -> u8
+    v216 = lt v213, v215
+    constrain v216 == u1 1
+    store u1 1 at v49
+    jmp b31()
+  b31():
+    jmp b32()
+  b32():
+    v217 = unchecked_add v5, u32 1
+    jmp b2(v217)
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Simplifying (1st):
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v11 = allocate -> &mut Field
+    v12 = allocate -> &mut Field
+    store Field 0 at v12
+    v16 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v46 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v47 = allocate -> &mut u1
+    store u1 0 at v47
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v51 = lt v5, u32 32
+    jmpif v51 then: b24, else: b2
+  b2():
+    v52 = load v47 -> u1
+    constrain v52 == u1 1
+    v54 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v55 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v56 = allocate -> &mut u1
+    store u1 0 at v56
+    jmp b3(u32 0)
+  b3(v6: u32):
+    v57 = lt v6, u32 32
+    jmpif v57 then: b19, else: b4
+  b4():
+    v58 = load v56 -> u1
+    constrain v58 == u1 1
+    v59 = allocate -> &mut [u8; 32]
+    store v54 at v59
+    jmp b5(u32 0)
+  b5(v7: u32):
+    v60 = lt v7, u32 32
+    jmpif v60 then: b18, else: b6
+  b6():
+    v61 = load v59 -> [u8; 32]
+    v62 = allocate -> &mut Field
+    store Field 1 at v62
+    v64 = allocate -> &mut Field
+    store Field 0 at v64
+    v65 = allocate -> &mut Field
+    store Field 0 at v65
+    jmp b7(u32 0)
+  b7(v8: u32):
+    v67 = lt v8, u32 16
+    jmpif v67 then: b17, else: b8
+  b8():
+    v68 = load v65 -> Field
+    v69 = load v64 -> Field
+    v70 = load v62 -> Field
+    v71 = mul v69, v70
+    v72 = add v68, v71
+    store v72 at v12
+    v73 = allocate -> &mut Field
+    store Field 0 at v73
+    v74 = eq v4, Field 0
+    jmpif v74 then: b13, else: b9
+  b9():
+    v76 = call f1(v4, Field 0) -> u1
+    jmpif v76 then: b11, else: b10
+  b10():
+    v78, v79 = call f3(v4) -> (Field, Field)
+    range_check v78 to 128 bits
+    range_check v79 to 128 bits
+    v81 = mul Field 340282366920938463463374607431768211456, v79
+    v82 = add v78, v81
+    v83 = eq v4, v82
+    constrain v4 == v82
+    v86 = call f2(Field 53438638232309528389504892708671455233, v78) -> u1
+    v87 = sub Field 53438638232309528389504892708671455233, v78
+    v88 = sub v87, Field 1
+    v89 = cast v86 as Field
+    v90 = mul v89, Field 340282366920938463463374607431768211456
+    v91 = add v88, v90
+    v93 = sub Field 64323764613183177041862057485226039389, v79
+    v94 = cast v86 as Field
+    v95 = sub v93, v94
+    range_check v91 to 128 bits
+    range_check v95 to 128 bits
+    v97, v98 = call f3(Field 0) -> (Field, Field)
+    range_check v97 to 128 bits
+    range_check v98 to 128 bits
+    v99 = mul Field 340282366920938463463374607431768211456, v98
+    v100 = add v97, v99
+    v101 = eq Field 0, v100
+    constrain Field 0 == v100
+    v103 = call f2(Field 53438638232309528389504892708671455233, v97) -> u1
+    v104 = sub Field 53438638232309528389504892708671455233, v97
+    v105 = sub v104, Field 1
+    v106 = cast v103 as Field
+    v107 = mul v106, Field 340282366920938463463374607431768211456
+    v108 = add v105, v107
+    v109 = sub Field 64323764613183177041862057485226039389, v98
+    v110 = cast v103 as Field
+    v111 = sub v109, v110
+    range_check v108 to 128 bits
+    range_check v111 to 128 bits
+    v113 = call f2(v78, v97) -> u1
+    v114 = sub v78, v97
+    v115 = sub v114, Field 1
+    v116 = cast v113 as Field
+    v117 = mul v116, Field 340282366920938463463374607431768211456
+    v118 = add v115, v117
+    v119 = sub v79, v98
+    v120 = cast v113 as Field
+    v121 = sub v119, v120
+    range_check v118 to 128 bits
+    range_check v121 to 128 bits
+    jmp b12(u1 1)
+  b11():
+    v123, v124 = call f3(Field 0) -> (Field, Field)
+    range_check v123 to 128 bits
+    range_check v124 to 128 bits
+    v125 = mul Field 340282366920938463463374607431768211456, v124
+    v126 = add v123, v125
+    v127 = eq Field 0, v126
+    constrain Field 0 == v126
+    v129 = call f2(Field 53438638232309528389504892708671455233, v123) -> u1
+    v130 = sub Field 53438638232309528389504892708671455233, v123
+    v131 = sub v130, Field 1
+    v132 = cast v129 as Field
+    v133 = mul v132, Field 340282366920938463463374607431768211456
+    v134 = add v131, v133
+    v135 = sub Field 64323764613183177041862057485226039389, v124
+    v136 = cast v129 as Field
+    v137 = sub v135, v136
+    range_check v134 to 128 bits
+    range_check v137 to 128 bits
+    v139, v140 = call f3(v4) -> (Field, Field)
+    range_check v139 to 128 bits
+    range_check v140 to 128 bits
+    v141 = mul Field 340282366920938463463374607431768211456, v140
+    v142 = add v139, v141
+    v143 = eq v4, v142
+    constrain v4 == v142
+    v145 = call f2(Field 53438638232309528389504892708671455233, v139) -> u1
+    v146 = sub Field 53438638232309528389504892708671455233, v139
+    v147 = sub v146, Field 1
+    v148 = cast v145 as Field
+    v149 = mul v148, Field 340282366920938463463374607431768211456
+    v150 = add v147, v149
+    v151 = sub Field 64323764613183177041862057485226039389, v140
+    v152 = cast v145 as Field
+    v153 = sub v151, v152
+    range_check v150 to 128 bits
+    range_check v153 to 128 bits
+    v155 = call f2(v123, v139) -> u1
+    v156 = sub v123, v139
+    v157 = sub v156, Field 1
+    v158 = cast v155 as Field
+    v159 = mul v158, Field 340282366920938463463374607431768211456
+    v160 = add v157, v159
+    v161 = sub v124, v140
+    v162 = cast v155 as Field
+    v163 = sub v161, v162
+    range_check v160 to 128 bits
+    range_check v163 to 128 bits
+    jmp b12(u1 0)
+  b12(v9: u1):
+    jmp b14(v9)
+  b13():
+    jmp b14(u1 0)
+  b14(v10: u1):
+    jmpif v10 then: b15, else: b16
+  b15():
+    store Field 1 at v73
+    jmp b16()
+  b16():
+    v164 = load v73 -> Field
+    v165 = load v12 -> Field
+    v166 = sub v164, v165
+    return v166
+  b17():
+    v167 = load v64 -> Field
+    v169 = sub u32 15, v8
+    v170 = array_get v61, index v169 -> u8
+    v171 = cast v170 as Field
+    v172 = load v62 -> Field
+    v173 = mul v171, v172
+    v174 = add v167, v173
+    store v174 at v64
+    v175 = load v65 -> Field
+    v177 = sub u32 31, v8
+    v178 = array_get v61, index v177 -> u8
+    v179 = cast v178 as Field
+    v180 = mul v179, v172
+    v181 = add v175, v180
+    store v181 at v65
+    v183 = mul v172, Field 256
+    store v183 at v62
+    v185 = unchecked_add v8, u32 1
+    jmp b7(v185)
+  b18():
+    v186 = load v59 -> [u8; 32]
+    v187 = array_get v16, index v7 -> u8
+    v188 = array_get v186, index v7 -> u8
+    v189 = xor v187, v188
+    v190 = array_set v186, index v7, value v189
+    v191 = unchecked_add v7, u32 1
+    store v190 at v59
+    v192 = unchecked_add v7, u32 1
+    jmp b5(v192)
+  b19():
+    v193 = load v56 -> u1
+    v194 = not v193
+    jmpif v194 then: b20, else: b23
+  b20():
+    v195 = array_get v54, index v6 -> u8
+    v196 = lt v6, u32 32
+    constrain v196 == u1 1, "Index out of bounds"
+    v197 = array_get v55, index v6 -> u8
+    v198 = eq v195, v197
+    v199 = not v198
+    jmpif v199 then: b21, else: b22
+  b21():
+    v200 = array_get v54, index v6 -> u8
+    v201 = lt v6, u32 32
+    constrain v201 == u1 1, "Index out of bounds"
+    v202 = array_get v55, index v6 -> u8
+    v203 = lt v200, v202
+    constrain v203 == u1 1
+    store u1 1 at v56
+    jmp b22()
+  b22():
+    jmp b23()
+  b23():
+    v204 = unchecked_add v6, u32 1
+    jmp b3(v204)
+  b24():
+    v205 = load v47 -> u1
+    v206 = not v205
+    jmpif v206 then: b25, else: b28
+  b25():
+    v207 = array_get v16, index v5 -> u8
+    v208 = lt v5, u32 32
+    constrain v208 == u1 1, "Index out of bounds"
+    v209 = array_get v46, index v5 -> u8
+    v210 = eq v207, v209
+    v211 = not v210
+    jmpif v211 then: b26, else: b27
+  b26():
+    v212 = array_get v16, index v5 -> u8
+    v213 = lt v5, u32 32
+    constrain v213 == u1 1, "Index out of bounds"
+    v214 = array_get v46, index v5 -> u8
+    v215 = lt v212, v214
+    constrain v215 == u1 1
+    store u1 1 at v47
+    jmp b27()
+  b27():
+    jmp b28()
+  b28():
+    v216 = unchecked_add v5, u32 1
+    jmp b1(v216)
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After `as_slice` optimization:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v11 = allocate -> &mut Field
+    v12 = allocate -> &mut Field
+    store Field 0 at v12
+    v16 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v46 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v47 = allocate -> &mut u1
+    store u1 0 at v47
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v51 = lt v5, u32 32
+    jmpif v51 then: b24, else: b2
+  b2():
+    v52 = load v47 -> u1
+    constrain v52 == u1 1
+    v54 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v55 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v56 = allocate -> &mut u1
+    store u1 0 at v56
+    jmp b3(u32 0)
+  b3(v6: u32):
+    v57 = lt v6, u32 32
+    jmpif v57 then: b19, else: b4
+  b4():
+    v58 = load v56 -> u1
+    constrain v58 == u1 1
+    v59 = allocate -> &mut [u8; 32]
+    store v54 at v59
+    jmp b5(u32 0)
+  b5(v7: u32):
+    v60 = lt v7, u32 32
+    jmpif v60 then: b18, else: b6
+  b6():
+    v61 = load v59 -> [u8; 32]
+    v62 = allocate -> &mut Field
+    store Field 1 at v62
+    v64 = allocate -> &mut Field
+    store Field 0 at v64
+    v65 = allocate -> &mut Field
+    store Field 0 at v65
+    jmp b7(u32 0)
+  b7(v8: u32):
+    v67 = lt v8, u32 16
+    jmpif v67 then: b17, else: b8
+  b8():
+    v68 = load v65 -> Field
+    v69 = load v64 -> Field
+    v70 = load v62 -> Field
+    v71 = mul v69, v70
+    v72 = add v68, v71
+    store v72 at v12
+    v73 = allocate -> &mut Field
+    store Field 0 at v73
+    v74 = eq v4, Field 0
+    jmpif v74 then: b13, else: b9
+  b9():
+    v76 = call f1(v4, Field 0) -> u1
+    jmpif v76 then: b11, else: b10
+  b10():
+    v78, v79 = call f3(v4) -> (Field, Field)
+    range_check v78 to 128 bits
+    range_check v79 to 128 bits
+    v81 = mul Field 340282366920938463463374607431768211456, v79
+    v82 = add v78, v81
+    v83 = eq v4, v82
+    constrain v4 == v82
+    v86 = call f2(Field 53438638232309528389504892708671455233, v78) -> u1
+    v87 = sub Field 53438638232309528389504892708671455233, v78
+    v88 = sub v87, Field 1
+    v89 = cast v86 as Field
+    v90 = mul v89, Field 340282366920938463463374607431768211456
+    v91 = add v88, v90
+    v93 = sub Field 64323764613183177041862057485226039389, v79
+    v94 = cast v86 as Field
+    v95 = sub v93, v94
+    range_check v91 to 128 bits
+    range_check v95 to 128 bits
+    v97, v98 = call f3(Field 0) -> (Field, Field)
+    range_check v97 to 128 bits
+    range_check v98 to 128 bits
+    v99 = mul Field 340282366920938463463374607431768211456, v98
+    v100 = add v97, v99
+    v101 = eq Field 0, v100
+    constrain Field 0 == v100
+    v103 = call f2(Field 53438638232309528389504892708671455233, v97) -> u1
+    v104 = sub Field 53438638232309528389504892708671455233, v97
+    v105 = sub v104, Field 1
+    v106 = cast v103 as Field
+    v107 = mul v106, Field 340282366920938463463374607431768211456
+    v108 = add v105, v107
+    v109 = sub Field 64323764613183177041862057485226039389, v98
+    v110 = cast v103 as Field
+    v111 = sub v109, v110
+    range_check v108 to 128 bits
+    range_check v111 to 128 bits
+    v113 = call f2(v78, v97) -> u1
+    v114 = sub v78, v97
+    v115 = sub v114, Field 1
+    v116 = cast v113 as Field
+    v117 = mul v116, Field 340282366920938463463374607431768211456
+    v118 = add v115, v117
+    v119 = sub v79, v98
+    v120 = cast v113 as Field
+    v121 = sub v119, v120
+    range_check v118 to 128 bits
+    range_check v121 to 128 bits
+    jmp b12(u1 1)
+  b11():
+    v123, v124 = call f3(Field 0) -> (Field, Field)
+    range_check v123 to 128 bits
+    range_check v124 to 128 bits
+    v125 = mul Field 340282366920938463463374607431768211456, v124
+    v126 = add v123, v125
+    v127 = eq Field 0, v126
+    constrain Field 0 == v126
+    v129 = call f2(Field 53438638232309528389504892708671455233, v123) -> u1
+    v130 = sub Field 53438638232309528389504892708671455233, v123
+    v131 = sub v130, Field 1
+    v132 = cast v129 as Field
+    v133 = mul v132, Field 340282366920938463463374607431768211456
+    v134 = add v131, v133
+    v135 = sub Field 64323764613183177041862057485226039389, v124
+    v136 = cast v129 as Field
+    v137 = sub v135, v136
+    range_check v134 to 128 bits
+    range_check v137 to 128 bits
+    v139, v140 = call f3(v4) -> (Field, Field)
+    range_check v139 to 128 bits
+    range_check v140 to 128 bits
+    v141 = mul Field 340282366920938463463374607431768211456, v140
+    v142 = add v139, v141
+    v143 = eq v4, v142
+    constrain v4 == v142
+    v145 = call f2(Field 53438638232309528389504892708671455233, v139) -> u1
+    v146 = sub Field 53438638232309528389504892708671455233, v139
+    v147 = sub v146, Field 1
+    v148 = cast v145 as Field
+    v149 = mul v148, Field 340282366920938463463374607431768211456
+    v150 = add v147, v149
+    v151 = sub Field 64323764613183177041862057485226039389, v140
+    v152 = cast v145 as Field
+    v153 = sub v151, v152
+    range_check v150 to 128 bits
+    range_check v153 to 128 bits
+    v155 = call f2(v123, v139) -> u1
+    v156 = sub v123, v139
+    v157 = sub v156, Field 1
+    v158 = cast v155 as Field
+    v159 = mul v158, Field 340282366920938463463374607431768211456
+    v160 = add v157, v159
+    v161 = sub v124, v140
+    v162 = cast v155 as Field
+    v163 = sub v161, v162
+    range_check v160 to 128 bits
+    range_check v163 to 128 bits
+    jmp b12(u1 0)
+  b12(v9: u1):
+    jmp b14(v9)
+  b13():
+    jmp b14(u1 0)
+  b14(v10: u1):
+    jmpif v10 then: b15, else: b16
+  b15():
+    store Field 1 at v73
+    jmp b16()
+  b16():
+    v164 = load v73 -> Field
+    v165 = load v12 -> Field
+    v166 = sub v164, v165
+    return v166
+  b17():
+    v167 = load v64 -> Field
+    v169 = sub u32 15, v8
+    v170 = array_get v61, index v169 -> u8
+    v171 = cast v170 as Field
+    v172 = load v62 -> Field
+    v173 = mul v171, v172
+    v174 = add v167, v173
+    store v174 at v64
+    v175 = load v65 -> Field
+    v177 = sub u32 31, v8
+    v178 = array_get v61, index v177 -> u8
+    v179 = cast v178 as Field
+    v180 = mul v179, v172
+    v181 = add v175, v180
+    store v181 at v65
+    v183 = mul v172, Field 256
+    store v183 at v62
+    v185 = unchecked_add v8, u32 1
+    jmp b7(v185)
+  b18():
+    v186 = load v59 -> [u8; 32]
+    v187 = array_get v16, index v7 -> u8
+    v188 = array_get v186, index v7 -> u8
+    v189 = xor v187, v188
+    v190 = array_set v186, index v7, value v189
+    v191 = unchecked_add v7, u32 1
+    store v190 at v59
+    v192 = unchecked_add v7, u32 1
+    jmp b5(v192)
+  b19():
+    v193 = load v56 -> u1
+    v194 = not v193
+    jmpif v194 then: b20, else: b23
+  b20():
+    v195 = array_get v54, index v6 -> u8
+    v196 = lt v6, u32 32
+    constrain v196 == u1 1, "Index out of bounds"
+    v197 = array_get v55, index v6 -> u8
+    v198 = eq v195, v197
+    v199 = not v198
+    jmpif v199 then: b21, else: b22
+  b21():
+    v200 = array_get v54, index v6 -> u8
+    v201 = lt v6, u32 32
+    constrain v201 == u1 1, "Index out of bounds"
+    v202 = array_get v55, index v6 -> u8
+    v203 = lt v200, v202
+    constrain v203 == u1 1
+    store u1 1 at v56
+    jmp b22()
+  b22():
+    jmp b23()
+  b23():
+    v204 = unchecked_add v6, u32 1
+    jmp b3(v204)
+  b24():
+    v205 = load v47 -> u1
+    v206 = not v205
+    jmpif v206 then: b25, else: b28
+  b25():
+    v207 = array_get v16, index v5 -> u8
+    v208 = lt v5, u32 32
+    constrain v208 == u1 1, "Index out of bounds"
+    v209 = array_get v46, index v5 -> u8
+    v210 = eq v207, v209
+    v211 = not v210
+    jmpif v211 then: b26, else: b27
+  b26():
+    v212 = array_get v16, index v5 -> u8
+    v213 = lt v5, u32 32
+    constrain v213 == u1 1, "Index out of bounds"
+    v214 = array_get v46, index v5 -> u8
+    v215 = lt v212, v214
+    constrain v215 == u1 1
+    store u1 1 at v47
+    jmp b27()
+  b27():
+    jmp b28()
+  b28():
+    v216 = unchecked_add v5, u32 1
+    jmp b1(v216)
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Removing Unreachable Functions:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v11 = allocate -> &mut Field
+    v12 = allocate -> &mut Field
+    store Field 0 at v12
+    v16 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v46 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v47 = allocate -> &mut u1
+    store u1 0 at v47
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v51 = lt v5, u32 32
+    jmpif v51 then: b24, else: b2
+  b2():
+    v52 = load v47 -> u1
+    constrain v52 == u1 1
+    v54 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v55 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v56 = allocate -> &mut u1
+    store u1 0 at v56
+    jmp b3(u32 0)
+  b3(v6: u32):
+    v57 = lt v6, u32 32
+    jmpif v57 then: b19, else: b4
+  b4():
+    v58 = load v56 -> u1
+    constrain v58 == u1 1
+    v59 = allocate -> &mut [u8; 32]
+    store v54 at v59
+    jmp b5(u32 0)
+  b5(v7: u32):
+    v60 = lt v7, u32 32
+    jmpif v60 then: b18, else: b6
+  b6():
+    v61 = load v59 -> [u8; 32]
+    v62 = allocate -> &mut Field
+    store Field 1 at v62
+    v64 = allocate -> &mut Field
+    store Field 0 at v64
+    v65 = allocate -> &mut Field
+    store Field 0 at v65
+    jmp b7(u32 0)
+  b7(v8: u32):
+    v67 = lt v8, u32 16
+    jmpif v67 then: b17, else: b8
+  b8():
+    v68 = load v65 -> Field
+    v69 = load v64 -> Field
+    v70 = load v62 -> Field
+    v71 = mul v69, v70
+    v72 = add v68, v71
+    store v72 at v12
+    v73 = allocate -> &mut Field
+    store Field 0 at v73
+    v74 = eq v4, Field 0
+    jmpif v74 then: b13, else: b9
+  b9():
+    v76 = call f1(v4, Field 0) -> u1
+    jmpif v76 then: b11, else: b10
+  b10():
+    v78, v79 = call f3(v4) -> (Field, Field)
+    range_check v78 to 128 bits
+    range_check v79 to 128 bits
+    v81 = mul Field 340282366920938463463374607431768211456, v79
+    v82 = add v78, v81
+    v83 = eq v4, v82
+    constrain v4 == v82
+    v86 = call f2(Field 53438638232309528389504892708671455233, v78) -> u1
+    v87 = sub Field 53438638232309528389504892708671455233, v78
+    v88 = sub v87, Field 1
+    v89 = cast v86 as Field
+    v90 = mul v89, Field 340282366920938463463374607431768211456
+    v91 = add v88, v90
+    v93 = sub Field 64323764613183177041862057485226039389, v79
+    v94 = cast v86 as Field
+    v95 = sub v93, v94
+    range_check v91 to 128 bits
+    range_check v95 to 128 bits
+    v97, v98 = call f3(Field 0) -> (Field, Field)
+    range_check v97 to 128 bits
+    range_check v98 to 128 bits
+    v99 = mul Field 340282366920938463463374607431768211456, v98
+    v100 = add v97, v99
+    v101 = eq Field 0, v100
+    constrain Field 0 == v100
+    v103 = call f2(Field 53438638232309528389504892708671455233, v97) -> u1
+    v104 = sub Field 53438638232309528389504892708671455233, v97
+    v105 = sub v104, Field 1
+    v106 = cast v103 as Field
+    v107 = mul v106, Field 340282366920938463463374607431768211456
+    v108 = add v105, v107
+    v109 = sub Field 64323764613183177041862057485226039389, v98
+    v110 = cast v103 as Field
+    v111 = sub v109, v110
+    range_check v108 to 128 bits
+    range_check v111 to 128 bits
+    v113 = call f2(v78, v97) -> u1
+    v114 = sub v78, v97
+    v115 = sub v114, Field 1
+    v116 = cast v113 as Field
+    v117 = mul v116, Field 340282366920938463463374607431768211456
+    v118 = add v115, v117
+    v119 = sub v79, v98
+    v120 = cast v113 as Field
+    v121 = sub v119, v120
+    range_check v118 to 128 bits
+    range_check v121 to 128 bits
+    jmp b12(u1 1)
+  b11():
+    v123, v124 = call f3(Field 0) -> (Field, Field)
+    range_check v123 to 128 bits
+    range_check v124 to 128 bits
+    v125 = mul Field 340282366920938463463374607431768211456, v124
+    v126 = add v123, v125
+    v127 = eq Field 0, v126
+    constrain Field 0 == v126
+    v129 = call f2(Field 53438638232309528389504892708671455233, v123) -> u1
+    v130 = sub Field 53438638232309528389504892708671455233, v123
+    v131 = sub v130, Field 1
+    v132 = cast v129 as Field
+    v133 = mul v132, Field 340282366920938463463374607431768211456
+    v134 = add v131, v133
+    v135 = sub Field 64323764613183177041862057485226039389, v124
+    v136 = cast v129 as Field
+    v137 = sub v135, v136
+    range_check v134 to 128 bits
+    range_check v137 to 128 bits
+    v139, v140 = call f3(v4) -> (Field, Field)
+    range_check v139 to 128 bits
+    range_check v140 to 128 bits
+    v141 = mul Field 340282366920938463463374607431768211456, v140
+    v142 = add v139, v141
+    v143 = eq v4, v142
+    constrain v4 == v142
+    v145 = call f2(Field 53438638232309528389504892708671455233, v139) -> u1
+    v146 = sub Field 53438638232309528389504892708671455233, v139
+    v147 = sub v146, Field 1
+    v148 = cast v145 as Field
+    v149 = mul v148, Field 340282366920938463463374607431768211456
+    v150 = add v147, v149
+    v151 = sub Field 64323764613183177041862057485226039389, v140
+    v152 = cast v145 as Field
+    v153 = sub v151, v152
+    range_check v150 to 128 bits
+    range_check v153 to 128 bits
+    v155 = call f2(v123, v139) -> u1
+    v156 = sub v123, v139
+    v157 = sub v156, Field 1
+    v158 = cast v155 as Field
+    v159 = mul v158, Field 340282366920938463463374607431768211456
+    v160 = add v157, v159
+    v161 = sub v124, v140
+    v162 = cast v155 as Field
+    v163 = sub v161, v162
+    range_check v160 to 128 bits
+    range_check v163 to 128 bits
+    jmp b12(u1 0)
+  b12(v9: u1):
+    jmp b14(v9)
+  b13():
+    jmp b14(u1 0)
+  b14(v10: u1):
+    jmpif v10 then: b15, else: b16
+  b15():
+    store Field 1 at v73
+    jmp b16()
+  b16():
+    v164 = load v73 -> Field
+    v165 = load v12 -> Field
+    v166 = sub v164, v165
+    return v166
+  b17():
+    v167 = load v64 -> Field
+    v169 = sub u32 15, v8
+    v170 = array_get v61, index v169 -> u8
+    v171 = cast v170 as Field
+    v172 = load v62 -> Field
+    v173 = mul v171, v172
+    v174 = add v167, v173
+    store v174 at v64
+    v175 = load v65 -> Field
+    v177 = sub u32 31, v8
+    v178 = array_get v61, index v177 -> u8
+    v179 = cast v178 as Field
+    v180 = mul v179, v172
+    v181 = add v175, v180
+    store v181 at v65
+    v183 = mul v172, Field 256
+    store v183 at v62
+    v185 = unchecked_add v8, u32 1
+    jmp b7(v185)
+  b18():
+    v186 = load v59 -> [u8; 32]
+    v187 = array_get v16, index v7 -> u8
+    v188 = array_get v186, index v7 -> u8
+    v189 = xor v187, v188
+    v190 = array_set v186, index v7, value v189
+    v191 = unchecked_add v7, u32 1
+    store v190 at v59
+    v192 = unchecked_add v7, u32 1
+    jmp b5(v192)
+  b19():
+    v193 = load v56 -> u1
+    v194 = not v193
+    jmpif v194 then: b20, else: b23
+  b20():
+    v195 = array_get v54, index v6 -> u8
+    v196 = lt v6, u32 32
+    constrain v196 == u1 1, "Index out of bounds"
+    v197 = array_get v55, index v6 -> u8
+    v198 = eq v195, v197
+    v199 = not v198
+    jmpif v199 then: b21, else: b22
+  b21():
+    v200 = array_get v54, index v6 -> u8
+    v201 = lt v6, u32 32
+    constrain v201 == u1 1, "Index out of bounds"
+    v202 = array_get v55, index v6 -> u8
+    v203 = lt v200, v202
+    constrain v203 == u1 1
+    store u1 1 at v56
+    jmp b22()
+  b22():
+    jmp b23()
+  b23():
+    v204 = unchecked_add v6, u32 1
+    jmp b3(v204)
+  b24():
+    v205 = load v47 -> u1
+    v206 = not v205
+    jmpif v206 then: b25, else: b28
+  b25():
+    v207 = array_get v16, index v5 -> u8
+    v208 = lt v5, u32 32
+    constrain v208 == u1 1, "Index out of bounds"
+    v209 = array_get v46, index v5 -> u8
+    v210 = eq v207, v209
+    v211 = not v210
+    jmpif v211 then: b26, else: b27
+  b26():
+    v212 = array_get v16, index v5 -> u8
+    v213 = lt v5, u32 32
+    constrain v213 == u1 1, "Index out of bounds"
+    v214 = array_get v46, index v5 -> u8
+    v215 = lt v212, v214
+    constrain v215 == u1 1
+    store u1 1 at v47
+    jmp b27()
+  b27():
+    jmp b28()
+  b28():
+    v216 = unchecked_add v5, u32 1
+    jmp b1(v216)
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After `static_assert` and `assert_constant`:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v11 = allocate -> &mut Field
+    v12 = allocate -> &mut Field
+    store Field 0 at v12
+    v16 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v46 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v47 = allocate -> &mut u1
+    store u1 0 at v47
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v51 = lt v5, u32 32
+    jmpif v51 then: b24, else: b2
+  b2():
+    v52 = load v47 -> u1
+    constrain v52 == u1 1
+    v54 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v55 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v56 = allocate -> &mut u1
+    store u1 0 at v56
+    jmp b3(u32 0)
+  b3(v6: u32):
+    v57 = lt v6, u32 32
+    jmpif v57 then: b19, else: b4
+  b4():
+    v58 = load v56 -> u1
+    constrain v58 == u1 1
+    v59 = allocate -> &mut [u8; 32]
+    store v54 at v59
+    jmp b5(u32 0)
+  b5(v7: u32):
+    v60 = lt v7, u32 32
+    jmpif v60 then: b18, else: b6
+  b6():
+    v61 = load v59 -> [u8; 32]
+    v62 = allocate -> &mut Field
+    store Field 1 at v62
+    v64 = allocate -> &mut Field
+    store Field 0 at v64
+    v65 = allocate -> &mut Field
+    store Field 0 at v65
+    jmp b7(u32 0)
+  b7(v8: u32):
+    v67 = lt v8, u32 16
+    jmpif v67 then: b17, else: b8
+  b8():
+    v68 = load v65 -> Field
+    v69 = load v64 -> Field
+    v70 = load v62 -> Field
+    v71 = mul v69, v70
+    v72 = add v68, v71
+    store v72 at v12
+    v73 = allocate -> &mut Field
+    store Field 0 at v73
+    v74 = eq v4, Field 0
+    jmpif v74 then: b13, else: b9
+  b9():
+    v76 = call f1(v4, Field 0) -> u1
+    jmpif v76 then: b11, else: b10
+  b10():
+    v78, v79 = call f3(v4) -> (Field, Field)
+    range_check v78 to 128 bits
+    range_check v79 to 128 bits
+    v81 = mul Field 340282366920938463463374607431768211456, v79
+    v82 = add v78, v81
+    v83 = eq v4, v82
+    constrain v4 == v82
+    v86 = call f2(Field 53438638232309528389504892708671455233, v78) -> u1
+    v87 = sub Field 53438638232309528389504892708671455233, v78
+    v88 = sub v87, Field 1
+    v89 = cast v86 as Field
+    v90 = mul v89, Field 340282366920938463463374607431768211456
+    v91 = add v88, v90
+    v93 = sub Field 64323764613183177041862057485226039389, v79
+    v94 = cast v86 as Field
+    v95 = sub v93, v94
+    range_check v91 to 128 bits
+    range_check v95 to 128 bits
+    v97, v98 = call f3(Field 0) -> (Field, Field)
+    range_check v97 to 128 bits
+    range_check v98 to 128 bits
+    v99 = mul Field 340282366920938463463374607431768211456, v98
+    v100 = add v97, v99
+    v101 = eq Field 0, v100
+    constrain Field 0 == v100
+    v103 = call f2(Field 53438638232309528389504892708671455233, v97) -> u1
+    v104 = sub Field 53438638232309528389504892708671455233, v97
+    v105 = sub v104, Field 1
+    v106 = cast v103 as Field
+    v107 = mul v106, Field 340282366920938463463374607431768211456
+    v108 = add v105, v107
+    v109 = sub Field 64323764613183177041862057485226039389, v98
+    v110 = cast v103 as Field
+    v111 = sub v109, v110
+    range_check v108 to 128 bits
+    range_check v111 to 128 bits
+    v113 = call f2(v78, v97) -> u1
+    v114 = sub v78, v97
+    v115 = sub v114, Field 1
+    v116 = cast v113 as Field
+    v117 = mul v116, Field 340282366920938463463374607431768211456
+    v118 = add v115, v117
+    v119 = sub v79, v98
+    v120 = cast v113 as Field
+    v121 = sub v119, v120
+    range_check v118 to 128 bits
+    range_check v121 to 128 bits
+    jmp b12(u1 1)
+  b11():
+    v123, v124 = call f3(Field 0) -> (Field, Field)
+    range_check v123 to 128 bits
+    range_check v124 to 128 bits
+    v125 = mul Field 340282366920938463463374607431768211456, v124
+    v126 = add v123, v125
+    v127 = eq Field 0, v126
+    constrain Field 0 == v126
+    v129 = call f2(Field 53438638232309528389504892708671455233, v123) -> u1
+    v130 = sub Field 53438638232309528389504892708671455233, v123
+    v131 = sub v130, Field 1
+    v132 = cast v129 as Field
+    v133 = mul v132, Field 340282366920938463463374607431768211456
+    v134 = add v131, v133
+    v135 = sub Field 64323764613183177041862057485226039389, v124
+    v136 = cast v129 as Field
+    v137 = sub v135, v136
+    range_check v134 to 128 bits
+    range_check v137 to 128 bits
+    v139, v140 = call f3(v4) -> (Field, Field)
+    range_check v139 to 128 bits
+    range_check v140 to 128 bits
+    v141 = mul Field 340282366920938463463374607431768211456, v140
+    v142 = add v139, v141
+    v143 = eq v4, v142
+    constrain v4 == v142
+    v145 = call f2(Field 53438638232309528389504892708671455233, v139) -> u1
+    v146 = sub Field 53438638232309528389504892708671455233, v139
+    v147 = sub v146, Field 1
+    v148 = cast v145 as Field
+    v149 = mul v148, Field 340282366920938463463374607431768211456
+    v150 = add v147, v149
+    v151 = sub Field 64323764613183177041862057485226039389, v140
+    v152 = cast v145 as Field
+    v153 = sub v151, v152
+    range_check v150 to 128 bits
+    range_check v153 to 128 bits
+    v155 = call f2(v123, v139) -> u1
+    v156 = sub v123, v139
+    v157 = sub v156, Field 1
+    v158 = cast v155 as Field
+    v159 = mul v158, Field 340282366920938463463374607431768211456
+    v160 = add v157, v159
+    v161 = sub v124, v140
+    v162 = cast v155 as Field
+    v163 = sub v161, v162
+    range_check v160 to 128 bits
+    range_check v163 to 128 bits
+    jmp b12(u1 0)
+  b12(v9: u1):
+    jmp b14(v9)
+  b13():
+    jmp b14(u1 0)
+  b14(v10: u1):
+    jmpif v10 then: b15, else: b16
+  b15():
+    store Field 1 at v73
+    jmp b16()
+  b16():
+    v164 = load v73 -> Field
+    v165 = load v12 -> Field
+    v166 = sub v164, v165
+    return v166
+  b17():
+    v167 = load v64 -> Field
+    v169 = sub u32 15, v8
+    v170 = array_get v61, index v169 -> u8
+    v171 = cast v170 as Field
+    v172 = load v62 -> Field
+    v173 = mul v171, v172
+    v174 = add v167, v173
+    store v174 at v64
+    v175 = load v65 -> Field
+    v177 = sub u32 31, v8
+    v178 = array_get v61, index v177 -> u8
+    v179 = cast v178 as Field
+    v180 = mul v179, v172
+    v181 = add v175, v180
+    store v181 at v65
+    v183 = mul v172, Field 256
+    store v183 at v62
+    v185 = unchecked_add v8, u32 1
+    jmp b7(v185)
+  b18():
+    v186 = load v59 -> [u8; 32]
+    v187 = array_get v16, index v7 -> u8
+    v188 = array_get v186, index v7 -> u8
+    v189 = xor v187, v188
+    v190 = array_set v186, index v7, value v189
+    v191 = unchecked_add v7, u32 1
+    store v190 at v59
+    v192 = unchecked_add v7, u32 1
+    jmp b5(v192)
+  b19():
+    v193 = load v56 -> u1
+    v194 = not v193
+    jmpif v194 then: b20, else: b23
+  b20():
+    v195 = array_get v54, index v6 -> u8
+    v196 = lt v6, u32 32
+    constrain v196 == u1 1, "Index out of bounds"
+    v197 = array_get v55, index v6 -> u8
+    v198 = eq v195, v197
+    v199 = not v198
+    jmpif v199 then: b21, else: b22
+  b21():
+    v200 = array_get v54, index v6 -> u8
+    v201 = lt v6, u32 32
+    constrain v201 == u1 1, "Index out of bounds"
+    v202 = array_get v55, index v6 -> u8
+    v203 = lt v200, v202
+    constrain v203 == u1 1
+    store u1 1 at v56
+    jmp b22()
+  b22():
+    jmp b23()
+  b23():
+    v204 = unchecked_add v6, u32 1
+    jmp b3(v204)
+  b24():
+    v205 = load v47 -> u1
+    v206 = not v205
+    jmpif v206 then: b25, else: b28
+  b25():
+    v207 = array_get v16, index v5 -> u8
+    v208 = lt v5, u32 32
+    constrain v208 == u1 1, "Index out of bounds"
+    v209 = array_get v46, index v5 -> u8
+    v210 = eq v207, v209
+    v211 = not v210
+    jmpif v211 then: b26, else: b27
+  b26():
+    v212 = array_get v16, index v5 -> u8
+    v213 = lt v5, u32 32
+    constrain v213 == u1 1, "Index out of bounds"
+    v214 = array_get v46, index v5 -> u8
+    v215 = lt v212, v214
+    constrain v215 == u1 1
+    store u1 1 at v47
+    jmp b27()
+  b27():
+    jmp b28()
+  b28():
+    v216 = unchecked_add v5, u32 1
+    jmp b1(v216)
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Loop Invariant Code Motion:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v11 = allocate -> &mut Field
+    v12 = allocate -> &mut Field
+    store Field 0 at v12
+    v16 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v46 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v47 = allocate -> &mut u1
+    store u1 0 at v47
+    jmp b1(u32 0)
+  b1(v5: u32):
+    v51 = lt v5, u32 32
+    jmpif v51 then: b24, else: b2
+  b2():
+    v52 = load v47 -> u1
+    constrain v52 == u1 1
+    v54 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v55 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v56 = allocate -> &mut u1
+    store u1 0 at v56
+    jmp b3(u32 0)
+  b3(v6: u32):
+    v57 = lt v6, u32 32
+    jmpif v57 then: b19, else: b4
+  b4():
+    v58 = load v56 -> u1
+    constrain v58 == u1 1
+    v59 = allocate -> &mut [u8; 32]
+    store v54 at v59
+    jmp b5(u32 0)
+  b5(v7: u32):
+    v60 = lt v7, u32 32
+    jmpif v60 then: b18, else: b6
+  b6():
+    v61 = load v59 -> [u8; 32]
+    v62 = allocate -> &mut Field
+    store Field 1 at v62
+    v64 = allocate -> &mut Field
+    store Field 0 at v64
+    v65 = allocate -> &mut Field
+    store Field 0 at v65
+    jmp b7(u32 0)
+  b7(v8: u32):
+    v67 = lt v8, u32 16
+    jmpif v67 then: b17, else: b8
+  b8():
+    v68 = load v65 -> Field
+    v69 = load v64 -> Field
+    v70 = load v62 -> Field
+    v71 = mul v69, v70
+    v72 = add v68, v71
+    store v72 at v12
+    v73 = allocate -> &mut Field
+    store Field 0 at v73
+    v74 = eq v4, Field 0
+    jmpif v74 then: b13, else: b9
+  b9():
+    v76 = call f1(v4, Field 0) -> u1
+    jmpif v76 then: b11, else: b10
+  b10():
+    v78, v79 = call f3(v4) -> (Field, Field)
+    range_check v78 to 128 bits
+    range_check v79 to 128 bits
+    v81 = mul Field 340282366920938463463374607431768211456, v79
+    v82 = add v78, v81
+    v83 = eq v4, v82
+    constrain v4 == v82
+    v86 = call f2(Field 53438638232309528389504892708671455233, v78) -> u1
+    v87 = sub Field 53438638232309528389504892708671455233, v78
+    v88 = sub v87, Field 1
+    v89 = cast v86 as Field
+    v90 = mul v89, Field 340282366920938463463374607431768211456
+    v91 = add v88, v90
+    v93 = sub Field 64323764613183177041862057485226039389, v79
+    v94 = cast v86 as Field
+    v95 = sub v93, v94
+    range_check v91 to 128 bits
+    range_check v95 to 128 bits
+    v97, v98 = call f3(Field 0) -> (Field, Field)
+    range_check v97 to 128 bits
+    range_check v98 to 128 bits
+    v99 = mul Field 340282366920938463463374607431768211456, v98
+    v100 = add v97, v99
+    v101 = eq Field 0, v100
+    constrain Field 0 == v100
+    v103 = call f2(Field 53438638232309528389504892708671455233, v97) -> u1
+    v104 = sub Field 53438638232309528389504892708671455233, v97
+    v105 = sub v104, Field 1
+    v106 = cast v103 as Field
+    v107 = mul v106, Field 340282366920938463463374607431768211456
+    v108 = add v105, v107
+    v109 = sub Field 64323764613183177041862057485226039389, v98
+    v110 = cast v103 as Field
+    v111 = sub v109, v110
+    range_check v108 to 128 bits
+    range_check v111 to 128 bits
+    v113 = call f2(v78, v97) -> u1
+    v114 = sub v78, v97
+    v115 = sub v114, Field 1
+    v116 = cast v113 as Field
+    v117 = mul v116, Field 340282366920938463463374607431768211456
+    v118 = add v115, v117
+    v119 = sub v79, v98
+    v120 = cast v113 as Field
+    v121 = sub v119, v120
+    range_check v118 to 128 bits
+    range_check v121 to 128 bits
+    jmp b12(u1 1)
+  b11():
+    v123, v124 = call f3(Field 0) -> (Field, Field)
+    range_check v123 to 128 bits
+    range_check v124 to 128 bits
+    v125 = mul Field 340282366920938463463374607431768211456, v124
+    v126 = add v123, v125
+    v127 = eq Field 0, v126
+    constrain Field 0 == v126
+    v129 = call f2(Field 53438638232309528389504892708671455233, v123) -> u1
+    v130 = sub Field 53438638232309528389504892708671455233, v123
+    v131 = sub v130, Field 1
+    v132 = cast v129 as Field
+    v133 = mul v132, Field 340282366920938463463374607431768211456
+    v134 = add v131, v133
+    v135 = sub Field 64323764613183177041862057485226039389, v124
+    v136 = cast v129 as Field
+    v137 = sub v135, v136
+    range_check v134 to 128 bits
+    range_check v137 to 128 bits
+    v139, v140 = call f3(v4) -> (Field, Field)
+    range_check v139 to 128 bits
+    range_check v140 to 128 bits
+    v141 = mul Field 340282366920938463463374607431768211456, v140
+    v142 = add v139, v141
+    v143 = eq v4, v142
+    constrain v4 == v142
+    v145 = call f2(Field 53438638232309528389504892708671455233, v139) -> u1
+    v146 = sub Field 53438638232309528389504892708671455233, v139
+    v147 = sub v146, Field 1
+    v148 = cast v145 as Field
+    v149 = mul v148, Field 340282366920938463463374607431768211456
+    v150 = add v147, v149
+    v151 = sub Field 64323764613183177041862057485226039389, v140
+    v152 = cast v145 as Field
+    v153 = sub v151, v152
+    range_check v150 to 128 bits
+    range_check v153 to 128 bits
+    v155 = call f2(v123, v139) -> u1
+    v156 = sub v123, v139
+    v157 = sub v156, Field 1
+    v158 = cast v155 as Field
+    v159 = mul v158, Field 340282366920938463463374607431768211456
+    v160 = add v157, v159
+    v161 = sub v124, v140
+    v162 = cast v155 as Field
+    v163 = sub v161, v162
+    range_check v160 to 128 bits
+    range_check v163 to 128 bits
+    jmp b12(u1 0)
+  b12(v9: u1):
+    jmp b14(v9)
+  b13():
+    jmp b14(u1 0)
+  b14(v10: u1):
+    jmpif v10 then: b15, else: b16
+  b15():
+    store Field 1 at v73
+    jmp b16()
+  b16():
+    v164 = load v73 -> Field
+    v165 = load v12 -> Field
+    v166 = sub v164, v165
+    return v166
+  b17():
+    v167 = load v64 -> Field
+    v169 = sub u32 15, v8
+    v170 = array_get v61, index v169 -> u8
+    v171 = cast v170 as Field
+    v172 = load v62 -> Field
+    v173 = mul v171, v172
+    v174 = add v167, v173
+    store v174 at v64
+    v175 = load v65 -> Field
+    v177 = sub u32 31, v8
+    v178 = array_get v61, index v177 -> u8
+    v179 = cast v178 as Field
+    v180 = mul v179, v172
+    v181 = add v175, v180
+    store v181 at v65
+    v183 = mul v172, Field 256
+    store v183 at v62
+    v185 = unchecked_add v8, u32 1
+    jmp b7(v185)
+  b18():
+    v186 = load v59 -> [u8; 32]
+    v187 = array_get v16, index v7 -> u8
+    v188 = array_get v186, index v7 -> u8
+    v189 = xor v187, v188
+    v190 = array_set v186, index v7, value v189
+    v191 = unchecked_add v7, u32 1
+    store v190 at v59
+    v192 = unchecked_add v7, u32 1
+    jmp b5(v192)
+  b19():
+    v193 = load v56 -> u1
+    v194 = not v193
+    jmpif v194 then: b20, else: b23
+  b20():
+    v195 = array_get v54, index v6 -> u8
+    v196 = lt v6, u32 32
+    constrain v196 == u1 1, "Index out of bounds"
+    v197 = array_get v55, index v6 -> u8
+    v198 = eq v195, v197
+    v199 = not v198
+    jmpif v199 then: b21, else: b22
+  b21():
+    v200 = array_get v54, index v6 -> u8
+    v201 = lt v6, u32 32
+    constrain v201 == u1 1, "Index out of bounds"
+    v202 = array_get v55, index v6 -> u8
+    v203 = lt v200, v202
+    constrain v203 == u1 1
+    store u1 1 at v56
+    jmp b22()
+  b22():
+    jmp b23()
+  b23():
+    v204 = unchecked_add v6, u32 1
+    jmp b3(v204)
+  b24():
+    v205 = load v47 -> u1
+    v206 = not v205
+    jmpif v206 then: b25, else: b28
+  b25():
+    v207 = array_get v16, index v5 -> u8
+    v208 = lt v5, u32 32
+    constrain v208 == u1 1, "Index out of bounds"
+    v209 = array_get v46, index v5 -> u8
+    v210 = eq v207, v209
+    v211 = not v210
+    jmpif v211 then: b26, else: b27
+  b26():
+    v212 = array_get v16, index v5 -> u8
+    v213 = lt v5, u32 32
+    constrain v213 == u1 1, "Index out of bounds"
+    v214 = array_get v46, index v5 -> u8
+    v215 = lt v212, v214
+    constrain v215 == u1 1
+    store u1 1 at v47
+    jmp b27()
+  b27():
+    jmp b28()
+  b28():
+    v216 = unchecked_add v5, u32 1
+    jmp b1(v216)
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Unrolling:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v7 = allocate -> &mut Field
+    v8 = allocate -> &mut Field
+    store Field 0 at v8
+    v12 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v42 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v43 = allocate -> &mut u1
+    store u1 0 at v43
+    v45 = load v43 -> u1
+    v46 = not v45
+    jmpif v46 then: b1, else: b4
+  b1():
+    v48 = array_get v12, index u32 0 -> u8
+    v49 = eq v48, u8 48
+    v50 = not v49
+    jmpif v50 then: b2, else: b3
+  b2():
+    v51 = array_get v12, index u32 0 -> u8
+    v52 = lt v51, u8 48
+    constrain v52 == u1 1
+    store u1 1 at v43
+    jmp b3()
+  b3():
+    jmp b4()
+  b4():
+    v54 = load v43 -> u1
+    v55 = not v54
+    jmpif v55 then: b5, else: b8
+  b5():
+    v57 = array_get v12, index u32 1 -> u8
+    v58 = eq v57, u8 100
+    v59 = not v58
+    jmpif v59 then: b6, else: b7
+  b6():
+    v60 = array_get v12, index u32 1 -> u8
+    v61 = lt v60, u8 100
+    constrain v61 == u1 1
+    store u1 1 at v43
+    jmp b7()
+  b7():
+    jmp b8()
+  b8():
+    v62 = load v43 -> u1
+    v63 = not v62
+    jmpif v63 then: b9, else: b12
+  b9():
+    v65 = array_get v12, index u32 2 -> u8
+    v66 = eq v65, u8 78
+    v67 = not v66
+    jmpif v67 then: b10, else: b11
+  b10():
+    v68 = array_get v12, index u32 2 -> u8
+    v69 = lt v68, u8 78
+    constrain v69 == u1 1
+    store u1 1 at v43
+    jmp b11()
+  b11():
+    jmp b12()
+  b12():
+    v70 = load v43 -> u1
+    v71 = not v70
+    jmpif v71 then: b13, else: b16
+  b13():
+    v73 = array_get v12, index u32 3 -> u8
+    v74 = eq v73, u8 114
+    v75 = not v74
+    jmpif v75 then: b14, else: b15
+  b14():
+    v76 = array_get v12, index u32 3 -> u8
+    v77 = lt v76, u8 114
+    constrain v77 == u1 1
+    store u1 1 at v43
+    jmp b15()
+  b15():
+    jmp b16()
+  b16():
+    v78 = load v43 -> u1
+    v79 = not v78
+    jmpif v79 then: b17, else: b20
+  b17():
+    v81 = array_get v12, index u32 4 -> u8
+    v82 = eq v81, u8 225
+    v83 = not v82
+    jmpif v83 then: b18, else: b19
+  b18():
+    v84 = array_get v12, index u32 4 -> u8
+    v85 = lt v84, u8 225
+    constrain v85 == u1 1
+    store u1 1 at v43
+    jmp b19()
+  b19():
+    jmp b20()
+  b20():
+    v86 = load v43 -> u1
+    v87 = not v86
+    jmpif v87 then: b21, else: b24
+  b21():
+    v89 = array_get v12, index u32 5 -> u8
+    v90 = eq v89, u8 49
+    v91 = not v90
+    jmpif v91 then: b22, else: b23
+  b22():
+    v92 = array_get v12, index u32 5 -> u8
+    v93 = lt v92, u8 49
+    constrain v93 == u1 1
+    store u1 1 at v43
+    jmp b23()
+  b23():
+    jmp b24()
+  b24():
+    v94 = load v43 -> u1
+    v95 = not v94
+    jmpif v95 then: b25, else: b28
+  b25():
+    v97 = array_get v12, index u32 6 -> u8
+    v98 = eq v97, u8 160
+    v99 = not v98
+    jmpif v99 then: b26, else: b27
+  b26():
+    v100 = array_get v12, index u32 6 -> u8
+    v101 = lt v100, u8 160
+    constrain v101 == u1 1
+    store u1 1 at v43
+    jmp b27()
+  b27():
+    jmp b28()
+  b28():
+    v102 = load v43 -> u1
+    v103 = not v102
+    jmpif v103 then: b29, else: b32
+  b29():
+    v105 = array_get v12, index u32 7 -> u8
+    v106 = eq v105, u8 41
+    v107 = not v106
+    jmpif v107 then: b30, else: b31
+  b30():
+    v108 = array_get v12, index u32 7 -> u8
+    v109 = lt v108, u8 41
+    constrain v109 == u1 1
+    store u1 1 at v43
+    jmp b31()
+  b31():
+    jmp b32()
+  b32():
+    v110 = load v43 -> u1
+    v111 = not v110
+    jmpif v111 then: b33, else: b36
+  b33():
+    v113 = array_get v12, index u32 8 -> u8
+    v114 = eq v113, u8 184
+    v115 = not v114
+    jmpif v115 then: b34, else: b35
+  b34():
+    v116 = array_get v12, index u32 8 -> u8
+    v117 = lt v116, u8 184
+    constrain v117 == u1 1
+    store u1 1 at v43
+    jmp b35()
+  b35():
+    jmp b36()
+  b36():
+    v118 = load v43 -> u1
+    v119 = not v118
+    jmpif v119 then: b37, else: b40
+  b37():
+    v121 = array_get v12, index u32 9 -> u8
+    v122 = eq v121, u8 80
+    v123 = not v122
+    jmpif v123 then: b38, else: b39
+  b38():
+    v124 = array_get v12, index u32 9 -> u8
+    v125 = lt v124, u8 80
+    constrain v125 == u1 1
+    store u1 1 at v43
+    jmp b39()
+  b39():
+    jmp b40()
+  b40():
+    v126 = load v43 -> u1
+    v127 = not v126
+    jmpif v127 then: b41, else: b44
+  b41():
+    v129 = array_get v12, index u32 10 -> u8
+    v130 = eq v129, u8 69
+    v131 = not v130
+    jmpif v131 then: b42, else: b43
+  b42():
+    v132 = array_get v12, index u32 10 -> u8
+    v133 = lt v132, u8 69
+    constrain v133 == u1 1
+    store u1 1 at v43
+    jmp b43()
+  b43():
+    jmp b44()
+  b44():
+    v134 = load v43 -> u1
+    v135 = not v134
+    jmpif v135 then: b45, else: b48
+  b45():
+    v137 = array_get v12, index u32 11 -> u8
+    v138 = eq v137, u8 182
+    v139 = not v138
+    jmpif v139 then: b46, else: b47
+  b46():
+    v140 = array_get v12, index u32 11 -> u8
+    v141 = lt v140, u8 182
+    constrain v141 == u1 1
+    store u1 1 at v43
+    jmp b47()
+  b47():
+    jmp b48()
+  b48():
+    v142 = load v43 -> u1
+    v143 = not v142
+    jmpif v143 then: b49, else: b52
+  b49():
+    v145 = array_get v12, index u32 12 -> u8
+    v146 = eq v145, u8 129
+    v147 = not v146
+    jmpif v147 then: b50, else: b51
+  b50():
+    v148 = array_get v12, index u32 12 -> u8
+    v149 = lt v148, u8 129
+    constrain v149 == u1 1
+    store u1 1 at v43
+    jmp b51()
+  b51():
+    jmp b52()
+  b52():
+    v150 = load v43 -> u1
+    v151 = not v150
+    jmpif v151 then: b53, else: b56
+  b53():
+    v153 = array_get v12, index u32 13 -> u8
+    v154 = eq v153, u8 129
+    v155 = not v154
+    jmpif v155 then: b54, else: b55
+  b54():
+    v156 = array_get v12, index u32 13 -> u8
+    v157 = lt v156, u8 129
+    constrain v157 == u1 1
+    store u1 1 at v43
+    jmp b55()
+  b55():
+    jmp b56()
+  b56():
+    v158 = load v43 -> u1
+    v159 = not v158
+    jmpif v159 then: b57, else: b60
+  b57():
+    v161 = array_get v12, index u32 14 -> u8
+    v162 = eq v161, u8 88
+    v163 = not v162
+    jmpif v163 then: b58, else: b59
+  b58():
+    v164 = array_get v12, index u32 14 -> u8
+    v165 = lt v164, u8 88
+    constrain v165 == u1 1
+    store u1 1 at v43
+    jmp b59()
+  b59():
+    jmp b60()
+  b60():
+    v166 = load v43 -> u1
+    v167 = not v166
+    jmpif v167 then: b61, else: b64
+  b61():
+    v169 = array_get v12, index u32 15 -> u8
+    v170 = eq v169, u8 93
+    v171 = not v170
+    jmpif v171 then: b62, else: b63
+  b62():
+    v172 = array_get v12, index u32 15 -> u8
+    v173 = lt v172, u8 93
+    constrain v173 == u1 1
+    store u1 1 at v43
+    jmp b63()
+  b63():
+    jmp b64()
+  b64():
+    v174 = load v43 -> u1
+    v175 = not v174
+    jmpif v175 then: b65, else: b68
+  b65():
+    v177 = array_get v12, index u32 16 -> u8
+    v178 = eq v177, u8 40
+    v179 = not v178
+    jmpif v179 then: b66, else: b67
+  b66():
+    v180 = array_get v12, index u32 16 -> u8
+    v181 = lt v180, u8 40
+    constrain v181 == u1 1
+    store u1 1 at v43
+    jmp b67()
+  b67():
+    jmp b68()
+  b68():
+    v182 = load v43 -> u1
+    v183 = not v182
+    jmpif v183 then: b69, else: b72
+  b69():
+    v185 = array_get v12, index u32 17 -> u8
+    v186 = eq v185, u8 51
+    v187 = not v186
+    jmpif v187 then: b70, else: b71
+  b70():
+    v188 = array_get v12, index u32 17 -> u8
+    v189 = lt v188, u8 51
+    constrain v189 == u1 1
+    store u1 1 at v43
+    jmp b71()
+  b71():
+    jmp b72()
+  b72():
+    v190 = load v43 -> u1
+    v191 = not v190
+    jmpif v191 then: b73, else: b76
+  b73():
+    v193 = array_get v12, index u32 18 -> u8
+    v194 = eq v193, u8 232
+    v195 = not v194
+    jmpif v195 then: b74, else: b75
+  b74():
+    v196 = array_get v12, index u32 18 -> u8
+    v197 = lt v196, u8 232
+    constrain v197 == u1 1
+    store u1 1 at v43
+    jmp b75()
+  b75():
+    jmp b76()
+  b76():
+    v198 = load v43 -> u1
+    v199 = not v198
+    jmpif v199 then: b77, else: b80
+  b77():
+    v201 = array_get v12, index u32 19 -> u8
+    v202 = eq v201, u8 72
+    v203 = not v202
+    jmpif v203 then: b78, else: b79
+  b78():
+    v204 = array_get v12, index u32 19 -> u8
+    v205 = lt v204, u8 72
+    constrain v205 == u1 1
+    store u1 1 at v43
+    jmp b79()
+  b79():
+    jmp b80()
+  b80():
+    v206 = load v43 -> u1
+    v207 = not v206
+    jmpif v207 then: b81, else: b84
+  b81():
+    v209 = array_get v12, index u32 20 -> u8
+    v210 = eq v209, u8 121
+    v211 = not v210
+    jmpif v211 then: b82, else: b83
+  b82():
+    v212 = array_get v12, index u32 20 -> u8
+    v213 = lt v212, u8 121
+    constrain v213 == u1 1
+    store u1 1 at v43
+    jmp b83()
+  b83():
+    jmp b84()
+  b84():
+    v214 = load v43 -> u1
+    v215 = not v214
+    jmpif v215 then: b85, else: b88
+  b85():
+    v217 = array_get v12, index u32 21 -> u8
+    v218 = eq v217, u8 185
+    v219 = not v218
+    jmpif v219 then: b86, else: b87
+  b86():
+    v220 = array_get v12, index u32 21 -> u8
+    v221 = lt v220, u8 185
+    constrain v221 == u1 1
+    store u1 1 at v43
+    jmp b87()
+  b87():
+    jmp b88()
+  b88():
+    v222 = load v43 -> u1
+    v223 = not v222
+    jmpif v223 then: b89, else: b92
+  b89():
+    v225 = array_get v12, index u32 22 -> u8
+    v226 = eq v225, u8 112
+    v227 = not v226
+    jmpif v227 then: b90, else: b91
+  b90():
+    v228 = array_get v12, index u32 22 -> u8
+    v229 = lt v228, u8 112
+    constrain v229 == u1 1
+    store u1 1 at v43
+    jmp b91()
+  b91():
+    jmp b92()
+  b92():
+    v230 = load v43 -> u1
+    v231 = not v230
+    jmpif v231 then: b93, else: b96
+  b93():
+    v233 = array_get v12, index u32 23 -> u8
+    v234 = eq v233, u8 145
+    v235 = not v234
+    jmpif v235 then: b94, else: b95
+  b94():
+    v236 = array_get v12, index u32 23 -> u8
+    v237 = lt v236, u8 145
+    constrain v237 == u1 1
+    store u1 1 at v43
+    jmp b95()
+  b95():
+    jmp b96()
+  b96():
+    v238 = load v43 -> u1
+    v239 = not v238
+    jmpif v239 then: b97, else: b100
+  b97():
+    v241 = array_get v12, index u32 24 -> u8
+    v242 = eq v241, u8 67
+    v243 = not v242
+    jmpif v243 then: b98, else: b99
+  b98():
+    v244 = array_get v12, index u32 24 -> u8
+    v245 = lt v244, u8 67
+    constrain v245 == u1 1
+    store u1 1 at v43
+    jmp b99()
+  b99():
+    jmp b100()
+  b100():
+    v246 = load v43 -> u1
+    v247 = not v246
+    jmpif v247 then: b101, else: b104
+  b101():
+    v249 = array_get v12, index u32 25 -> u8
+    v250 = eq v249, u8 225
+    v251 = not v250
+    jmpif v251 then: b102, else: b103
+  b102():
+    v252 = array_get v12, index u32 25 -> u8
+    v253 = lt v252, u8 225
+    constrain v253 == u1 1
+    store u1 1 at v43
+    jmp b103()
+  b103():
+    jmp b104()
+  b104():
+    v254 = load v43 -> u1
+    v255 = not v254
+    jmpif v255 then: b105, else: b108
+  b105():
+    v257 = array_get v12, index u32 26 -> u8
+    v258 = eq v257, u8 245
+    v259 = not v258
+    jmpif v259 then: b106, else: b107
+  b106():
+    v260 = array_get v12, index u32 26 -> u8
+    v261 = lt v260, u8 245
+    constrain v261 == u1 1
+    store u1 1 at v43
+    jmp b107()
+  b107():
+    jmp b108()
+  b108():
+    v262 = load v43 -> u1
+    v263 = not v262
+    jmpif v263 then: b109, else: b112
+  b109():
+    v265 = array_get v12, index u32 27 -> u8
+    v266 = eq v265, u8 147
+    v267 = not v266
+    jmpif v267 then: b110, else: b111
+  b110():
+    v268 = array_get v12, index u32 27 -> u8
+    v269 = lt v268, u8 147
+    constrain v269 == u1 1
+    store u1 1 at v43
+    jmp b111()
+  b111():
+    jmp b112()
+  b112():
+    v270 = load v43 -> u1
+    v271 = not v270
+    jmpif v271 then: b113, else: b116
+  b113():
+    v273 = array_get v12, index u32 28 -> u8
+    v274 = eq v273, u8 240
+    v275 = not v274
+    jmpif v275 then: b114, else: b115
+  b114():
+    v276 = array_get v12, index u32 28 -> u8
+    v277 = lt v276, u8 240
+    constrain v277 == u1 1
+    store u1 1 at v43
+    jmp b115()
+  b115():
+    jmp b116()
+  b116():
+    v278 = load v43 -> u1
+    v279 = not v278
+    jmpif v279 then: b117, else: b120
+  b117():
+    v281 = array_get v12, index u32 29 -> u8
+    v282 = eq v281, u8 0
+    v283 = not v282
+    jmpif v283 then: b118, else: b119
+  b118():
+    v284 = array_get v12, index u32 29 -> u8
+    constrain u1 0 == u1 1
+    store u1 1 at v43
+    jmp b119()
+  b119():
+    jmp b120()
+  b120():
+    v285 = load v43 -> u1
+    v286 = not v285
+    jmpif v286 then: b121, else: b124
+  b121():
+    v288 = array_get v12, index u32 30 -> u8
+    v289 = eq v288, u8 0
+    v290 = not v289
+    jmpif v290 then: b122, else: b123
+  b122():
+    v291 = array_get v12, index u32 30 -> u8
+    constrain u1 0 == u1 1
+    store u1 1 at v43
+    jmp b123()
+  b123():
+    jmp b124()
+  b124():
+    v292 = load v43 -> u1
+    v293 = not v292
+    jmpif v293 then: b125, else: b128
+  b125():
+    v295 = array_get v12, index u32 31 -> u8
+    v296 = eq v295, u8 1
+    v297 = not v296
+    jmpif v297 then: b126, else: b127
+  b126():
+    v298 = array_get v12, index u32 31 -> u8
+    v299 = eq v298, u8 0
+    constrain v298 == u8 0
+    store u1 1 at v43
+    jmp b127()
+  b127():
+    jmp b128()
+  b128():
+    jmp b129()
+  b129():
+    v300 = load v43 -> u1
+    constrain v300 == u1 1
+    v301 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v302 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v303 = allocate -> &mut u1
+    store u1 0 at v303
+    v304 = load v303 -> u1
+    v305 = not v304
+    jmpif v305 then: b130, else: b133
+  b130():
+    jmp b131()
+  b131():
+    store u1 1 at v303
+    jmp b132()
+  b132():
+    jmp b133()
+  b133():
+    v306 = load v303 -> u1
+    v307 = not v306
+    jmpif v307 then: b134, else: b137
+  b134():
+    jmp b135()
+  b135():
+    store u1 1 at v303
+    jmp b136()
+  b136():
+    jmp b137()
+  b137():
+    v308 = load v303 -> u1
+    v309 = not v308
+    jmpif v309 then: b138, else: b141
+  b138():
+    jmp b139()
+  b139():
+    store u1 1 at v303
+    jmp b140()
+  b140():
+    jmp b141()
+  b141():
+    v310 = load v303 -> u1
+    v311 = not v310
+    jmpif v311 then: b142, else: b145
+  b142():
+    jmp b143()
+  b143():
+    store u1 1 at v303
+    jmp b144()
+  b144():
+    jmp b145()
+  b145():
+    v312 = load v303 -> u1
+    v313 = not v312
+    jmpif v313 then: b146, else: b149
+  b146():
+    jmp b147()
+  b147():
+    store u1 1 at v303
+    jmp b148()
+  b148():
+    jmp b149()
+  b149():
+    v314 = load v303 -> u1
+    v315 = not v314
+    jmpif v315 then: b150, else: b153
+  b150():
+    jmp b151()
+  b151():
+    store u1 1 at v303
+    jmp b152()
+  b152():
+    jmp b153()
+  b153():
+    v316 = load v303 -> u1
+    v317 = not v316
+    jmpif v317 then: b154, else: b157
+  b154():
+    jmp b155()
+  b155():
+    store u1 1 at v303
+    jmp b156()
+  b156():
+    jmp b157()
+  b157():
+    v318 = load v303 -> u1
+    v319 = not v318
+    jmpif v319 then: b158, else: b161
+  b158():
+    jmp b159()
+  b159():
+    store u1 1 at v303
+    jmp b160()
+  b160():
+    jmp b161()
+  b161():
+    v320 = load v303 -> u1
+    v321 = not v320
+    jmpif v321 then: b162, else: b165
+  b162():
+    jmp b163()
+  b163():
+    store u1 1 at v303
+    jmp b164()
+  b164():
+    jmp b165()
+  b165():
+    v322 = load v303 -> u1
+    v323 = not v322
+    jmpif v323 then: b166, else: b169
+  b166():
+    jmp b167()
+  b167():
+    store u1 1 at v303
+    jmp b168()
+  b168():
+    jmp b169()
+  b169():
+    v324 = load v303 -> u1
+    v325 = not v324
+    jmpif v325 then: b170, else: b173
+  b170():
+    jmp b171()
+  b171():
+    store u1 1 at v303
+    jmp b172()
+  b172():
+    jmp b173()
+  b173():
+    v326 = load v303 -> u1
+    v327 = not v326
+    jmpif v327 then: b174, else: b177
+  b174():
+    jmp b175()
+  b175():
+    store u1 1 at v303
+    jmp b176()
+  b176():
+    jmp b177()
+  b177():
+    v328 = load v303 -> u1
+    v329 = not v328
+    jmpif v329 then: b178, else: b181
+  b178():
+    jmp b179()
+  b179():
+    store u1 1 at v303
+    jmp b180()
+  b180():
+    jmp b181()
+  b181():
+    v330 = load v303 -> u1
+    v331 = not v330
+    jmpif v331 then: b182, else: b185
+  b182():
+    jmp b183()
+  b183():
+    store u1 1 at v303
+    jmp b184()
+  b184():
+    jmp b185()
+  b185():
+    v332 = load v303 -> u1
+    v333 = not v332
+    jmpif v333 then: b186, else: b189
+  b186():
+    jmp b187()
+  b187():
+    store u1 1 at v303
+    jmp b188()
+  b188():
+    jmp b189()
+  b189():
+    v334 = load v303 -> u1
+    v335 = not v334
+    jmpif v335 then: b190, else: b193
+  b190():
+    jmp b191()
+  b191():
+    store u1 1 at v303
+    jmp b192()
+  b192():
+    jmp b193()
+  b193():
+    v336 = load v303 -> u1
+    v337 = not v336
+    jmpif v337 then: b194, else: b197
+  b194():
+    jmp b195()
+  b195():
+    store u1 1 at v303
+    jmp b196()
+  b196():
+    jmp b197()
+  b197():
+    v338 = load v303 -> u1
+    v339 = not v338
+    jmpif v339 then: b198, else: b201
+  b198():
+    jmp b199()
+  b199():
+    store u1 1 at v303
+    jmp b200()
+  b200():
+    jmp b201()
+  b201():
+    v340 = load v303 -> u1
+    v341 = not v340
+    jmpif v341 then: b202, else: b205
+  b202():
+    jmp b203()
+  b203():
+    store u1 1 at v303
+    jmp b204()
+  b204():
+    jmp b205()
+  b205():
+    v342 = load v303 -> u1
+    v343 = not v342
+    jmpif v343 then: b206, else: b209
+  b206():
+    jmp b207()
+  b207():
+    store u1 1 at v303
+    jmp b208()
+  b208():
+    jmp b209()
+  b209():
+    v344 = load v303 -> u1
+    v345 = not v344
+    jmpif v345 then: b210, else: b213
+  b210():
+    jmp b211()
+  b211():
+    store u1 1 at v303
+    jmp b212()
+  b212():
+    jmp b213()
+  b213():
+    v346 = load v303 -> u1
+    v347 = not v346
+    jmpif v347 then: b214, else: b217
+  b214():
+    jmp b215()
+  b215():
+    store u1 1 at v303
+    jmp b216()
+  b216():
+    jmp b217()
+  b217():
+    v348 = load v303 -> u1
+    v349 = not v348
+    jmpif v349 then: b218, else: b221
+  b218():
+    jmp b219()
+  b219():
+    store u1 1 at v303
+    jmp b220()
+  b220():
+    jmp b221()
+  b221():
+    v350 = load v303 -> u1
+    v351 = not v350
+    jmpif v351 then: b222, else: b225
+  b222():
+    jmp b223()
+  b223():
+    store u1 1 at v303
+    jmp b224()
+  b224():
+    jmp b225()
+  b225():
+    v352 = load v303 -> u1
+    v353 = not v352
+    jmpif v353 then: b226, else: b229
+  b226():
+    jmp b227()
+  b227():
+    store u1 1 at v303
+    jmp b228()
+  b228():
+    jmp b229()
+  b229():
+    v354 = load v303 -> u1
+    v355 = not v354
+    jmpif v355 then: b230, else: b233
+  b230():
+    jmp b231()
+  b231():
+    store u1 1 at v303
+    jmp b232()
+  b232():
+    jmp b233()
+  b233():
+    v356 = load v303 -> u1
+    v357 = not v356
+    jmpif v357 then: b234, else: b237
+  b234():
+    jmp b235()
+  b235():
+    store u1 1 at v303
+    jmp b236()
+  b236():
+    jmp b237()
+  b237():
+    v358 = load v303 -> u1
+    v359 = not v358
+    jmpif v359 then: b238, else: b241
+  b238():
+    jmp b239()
+  b239():
+    store u1 1 at v303
+    jmp b240()
+  b240():
+    jmp b241()
+  b241():
+    v360 = load v303 -> u1
+    v361 = not v360
+    jmpif v361 then: b242, else: b245
+  b242():
+    jmp b243()
+  b243():
+    store u1 1 at v303
+    jmp b244()
+  b244():
+    jmp b245()
+  b245():
+    v362 = load v303 -> u1
+    v363 = not v362
+    jmpif v363 then: b246, else: b248
+  b246():
+    jmp b247()
+  b247():
+    jmp b248()
+  b248():
+    v364 = load v303 -> u1
+    v365 = not v364
+    jmpif v365 then: b249, else: b251
+  b249():
+    jmp b250()
+  b250():
+    jmp b251()
+  b251():
+    v366 = load v303 -> u1
+    v367 = not v366
+    jmpif v367 then: b252, else: b255
+  b252():
+    jmp b253()
+  b253():
+    store u1 1 at v303
+    jmp b254()
+  b254():
+    jmp b255()
+  b255():
+    jmp b256()
+  b256():
+    v368 = load v303 -> u1
+    constrain v368 == u1 1
+    v369 = allocate -> &mut [u8; 32]
+    store v301 at v369
+    v370 = load v369 -> [u8; 32]
+    v371 = array_get v12, index u32 0 -> u8
+    v372 = array_get v370, index u32 0 -> u8
+    v373 = xor v371, v372
+    v374 = array_set v370, index u32 0, value v373
+    store v374 at v369
+    v375 = load v369 -> [u8; 32]
+    v376 = array_get v12, index u32 1 -> u8
+    v377 = array_get v375, index u32 1 -> u8
+    v378 = xor v376, v377
+    v379 = array_set v375, index u32 1, value v378
+    store v379 at v369
+    v380 = load v369 -> [u8; 32]
+    v381 = array_get v12, index u32 2 -> u8
+    v382 = array_get v380, index u32 2 -> u8
+    v383 = xor v381, v382
+    v384 = array_set v380, index u32 2, value v383
+    store v384 at v369
+    v385 = load v369 -> [u8; 32]
+    v386 = array_get v12, index u32 3 -> u8
+    v387 = array_get v385, index u32 3 -> u8
+    v388 = xor v386, v387
+    v389 = array_set v385, index u32 3, value v388
+    store v389 at v369
+    v390 = load v369 -> [u8; 32]
+    v391 = array_get v12, index u32 4 -> u8
+    v392 = array_get v390, index u32 4 -> u8
+    v393 = xor v391, v392
+    v394 = array_set v390, index u32 4, value v393
+    store v394 at v369
+    v395 = load v369 -> [u8; 32]
+    v396 = array_get v12, index u32 5 -> u8
+    v397 = array_get v395, index u32 5 -> u8
+    v398 = xor v396, v397
+    v399 = array_set v395, index u32 5, value v398
+    store v399 at v369
+    v400 = load v369 -> [u8; 32]
+    v401 = array_get v12, index u32 6 -> u8
+    v402 = array_get v400, index u32 6 -> u8
+    v403 = xor v401, v402
+    v404 = array_set v400, index u32 6, value v403
+    store v404 at v369
+    v405 = load v369 -> [u8; 32]
+    v406 = array_get v12, index u32 7 -> u8
+    v407 = array_get v405, index u32 7 -> u8
+    v408 = xor v406, v407
+    v409 = array_set v405, index u32 7, value v408
+    store v409 at v369
+    v410 = load v369 -> [u8; 32]
+    v411 = array_get v12, index u32 8 -> u8
+    v412 = array_get v410, index u32 8 -> u8
+    v413 = xor v411, v412
+    v414 = array_set v410, index u32 8, value v413
+    store v414 at v369
+    v415 = load v369 -> [u8; 32]
+    v416 = array_get v12, index u32 9 -> u8
+    v417 = array_get v415, index u32 9 -> u8
+    v418 = xor v416, v417
+    v419 = array_set v415, index u32 9, value v418
+    store v419 at v369
+    v420 = load v369 -> [u8; 32]
+    v421 = array_get v12, index u32 10 -> u8
+    v422 = array_get v420, index u32 10 -> u8
+    v423 = xor v421, v422
+    v424 = array_set v420, index u32 10, value v423
+    store v424 at v369
+    v425 = load v369 -> [u8; 32]
+    v426 = array_get v12, index u32 11 -> u8
+    v427 = array_get v425, index u32 11 -> u8
+    v428 = xor v426, v427
+    v429 = array_set v425, index u32 11, value v428
+    store v429 at v369
+    v430 = load v369 -> [u8; 32]
+    v431 = array_get v12, index u32 12 -> u8
+    v432 = array_get v430, index u32 12 -> u8
+    v433 = xor v431, v432
+    v434 = array_set v430, index u32 12, value v433
+    store v434 at v369
+    v435 = load v369 -> [u8; 32]
+    v436 = array_get v12, index u32 13 -> u8
+    v437 = array_get v435, index u32 13 -> u8
+    v438 = xor v436, v437
+    v439 = array_set v435, index u32 13, value v438
+    store v439 at v369
+    v440 = load v369 -> [u8; 32]
+    v441 = array_get v12, index u32 14 -> u8
+    v442 = array_get v440, index u32 14 -> u8
+    v443 = xor v441, v442
+    v444 = array_set v440, index u32 14, value v443
+    store v444 at v369
+    v445 = load v369 -> [u8; 32]
+    v446 = array_get v12, index u32 15 -> u8
+    v447 = array_get v445, index u32 15 -> u8
+    v448 = xor v446, v447
+    v449 = array_set v445, index u32 15, value v448
+    store v449 at v369
+    v450 = load v369 -> [u8; 32]
+    v451 = array_get v12, index u32 16 -> u8
+    v452 = array_get v450, index u32 16 -> u8
+    v453 = xor v451, v452
+    v454 = array_set v450, index u32 16, value v453
+    store v454 at v369
+    v455 = load v369 -> [u8; 32]
+    v456 = array_get v12, index u32 17 -> u8
+    v457 = array_get v455, index u32 17 -> u8
+    v458 = xor v456, v457
+    v459 = array_set v455, index u32 17, value v458
+    store v459 at v369
+    v460 = load v369 -> [u8; 32]
+    v461 = array_get v12, index u32 18 -> u8
+    v462 = array_get v460, index u32 18 -> u8
+    v463 = xor v461, v462
+    v464 = array_set v460, index u32 18, value v463
+    store v464 at v369
+    v465 = load v369 -> [u8; 32]
+    v466 = array_get v12, index u32 19 -> u8
+    v467 = array_get v465, index u32 19 -> u8
+    v468 = xor v466, v467
+    v469 = array_set v465, index u32 19, value v468
+    store v469 at v369
+    v470 = load v369 -> [u8; 32]
+    v471 = array_get v12, index u32 20 -> u8
+    v472 = array_get v470, index u32 20 -> u8
+    v473 = xor v471, v472
+    v474 = array_set v470, index u32 20, value v473
+    store v474 at v369
+    v475 = load v369 -> [u8; 32]
+    v476 = array_get v12, index u32 21 -> u8
+    v477 = array_get v475, index u32 21 -> u8
+    v478 = xor v476, v477
+    v479 = array_set v475, index u32 21, value v478
+    store v479 at v369
+    v480 = load v369 -> [u8; 32]
+    v481 = array_get v12, index u32 22 -> u8
+    v482 = array_get v480, index u32 22 -> u8
+    v483 = xor v481, v482
+    v484 = array_set v480, index u32 22, value v483
+    store v484 at v369
+    v485 = load v369 -> [u8; 32]
+    v486 = array_get v12, index u32 23 -> u8
+    v487 = array_get v485, index u32 23 -> u8
+    v488 = xor v486, v487
+    v489 = array_set v485, index u32 23, value v488
+    store v489 at v369
+    v490 = load v369 -> [u8; 32]
+    v491 = array_get v12, index u32 24 -> u8
+    v492 = array_get v490, index u32 24 -> u8
+    v493 = xor v491, v492
+    v494 = array_set v490, index u32 24, value v493
+    store v494 at v369
+    v495 = load v369 -> [u8; 32]
+    v496 = array_get v12, index u32 25 -> u8
+    v497 = array_get v495, index u32 25 -> u8
+    v498 = xor v496, v497
+    v499 = array_set v495, index u32 25, value v498
+    store v499 at v369
+    v500 = load v369 -> [u8; 32]
+    v501 = array_get v12, index u32 26 -> u8
+    v502 = array_get v500, index u32 26 -> u8
+    v503 = xor v501, v502
+    v504 = array_set v500, index u32 26, value v503
+    store v504 at v369
+    v505 = load v369 -> [u8; 32]
+    v506 = array_get v12, index u32 27 -> u8
+    v507 = array_get v505, index u32 27 -> u8
+    v508 = xor v506, v507
+    v509 = array_set v505, index u32 27, value v508
+    store v509 at v369
+    v510 = load v369 -> [u8; 32]
+    v511 = array_get v12, index u32 28 -> u8
+    v512 = array_get v510, index u32 28 -> u8
+    v513 = xor v511, v512
+    v514 = array_set v510, index u32 28, value v513
+    store v514 at v369
+    v515 = load v369 -> [u8; 32]
+    v516 = array_get v12, index u32 29 -> u8
+    v517 = array_get v515, index u32 29 -> u8
+    v518 = xor v516, v517
+    v519 = array_set v515, index u32 29, value v518
+    store v519 at v369
+    v520 = load v369 -> [u8; 32]
+    v521 = array_get v12, index u32 30 -> u8
+    v522 = array_get v520, index u32 30 -> u8
+    v523 = xor v521, v522
+    v524 = array_set v520, index u32 30, value v523
+    store v524 at v369
+    v525 = load v369 -> [u8; 32]
+    v526 = array_get v12, index u32 31 -> u8
+    v527 = array_get v525, index u32 31 -> u8
+    v528 = xor v526, v527
+    v529 = array_set v525, index u32 31, value v528
+    store v529 at v369
+    jmp b257()
+  b257():
+    v530 = load v369 -> [u8; 32]
+    v531 = allocate -> &mut Field
+    store Field 1 at v531
+    v533 = allocate -> &mut Field
+    store Field 0 at v533
+    v534 = allocate -> &mut Field
+    store Field 0 at v534
+    v535 = load v533 -> Field
+    v536 = array_get v530, index u32 15 -> u8
+    v537 = cast v536 as Field
+    v538 = load v531 -> Field
+    v539 = mul v537, v538
+    v540 = add v535, v539
+    store v540 at v533
+    v541 = load v534 -> Field
+    v542 = array_get v530, index u32 31 -> u8
+    v543 = cast v542 as Field
+    v544 = mul v543, v538
+    v545 = add v541, v544
+    store v545 at v534
+    v547 = mul v538, Field 256
+    store v547 at v531
+    v548 = load v533 -> Field
+    v549 = array_get v530, index u32 14 -> u8
+    v550 = cast v549 as Field
+    v551 = load v531 -> Field
+    v552 = mul v550, v551
+    v553 = add v548, v552
+    store v553 at v533
+    v554 = load v534 -> Field
+    v555 = array_get v530, index u32 30 -> u8
+    v556 = cast v555 as Field
+    v557 = mul v556, v551
+    v558 = add v554, v557
+    store v558 at v534
+    v559 = mul v551, Field 256
+    store v559 at v531
+    v560 = load v533 -> Field
+    v561 = array_get v530, index u32 13 -> u8
+    v562 = cast v561 as Field
+    v563 = load v531 -> Field
+    v564 = mul v562, v563
+    v565 = add v560, v564
+    store v565 at v533
+    v566 = load v534 -> Field
+    v567 = array_get v530, index u32 29 -> u8
+    v568 = cast v567 as Field
+    v569 = mul v568, v563
+    v570 = add v566, v569
+    store v570 at v534
+    v571 = mul v563, Field 256
+    store v571 at v531
+    v572 = load v533 -> Field
+    v573 = array_get v530, index u32 12 -> u8
+    v574 = cast v573 as Field
+    v575 = load v531 -> Field
+    v576 = mul v574, v575
+    v577 = add v572, v576
+    store v577 at v533
+    v578 = load v534 -> Field
+    v579 = array_get v530, index u32 28 -> u8
+    v580 = cast v579 as Field
+    v581 = mul v580, v575
+    v582 = add v578, v581
+    store v582 at v534
+    v583 = mul v575, Field 256
+    store v583 at v531
+    v584 = load v533 -> Field
+    v585 = array_get v530, index u32 11 -> u8
+    v586 = cast v585 as Field
+    v587 = load v531 -> Field
+    v588 = mul v586, v587
+    v589 = add v584, v588
+    store v589 at v533
+    v590 = load v534 -> Field
+    v591 = array_get v530, index u32 27 -> u8
+    v592 = cast v591 as Field
+    v593 = mul v592, v587
+    v594 = add v590, v593
+    store v594 at v534
+    v595 = mul v587, Field 256
+    store v595 at v531
+    v596 = load v533 -> Field
+    v597 = array_get v530, index u32 10 -> u8
+    v598 = cast v597 as Field
+    v599 = load v531 -> Field
+    v600 = mul v598, v599
+    v601 = add v596, v600
+    store v601 at v533
+    v602 = load v534 -> Field
+    v603 = array_get v530, index u32 26 -> u8
+    v604 = cast v603 as Field
+    v605 = mul v604, v599
+    v606 = add v602, v605
+    store v606 at v534
+    v607 = mul v599, Field 256
+    store v607 at v531
+    v608 = load v533 -> Field
+    v609 = array_get v530, index u32 9 -> u8
+    v610 = cast v609 as Field
+    v611 = load v531 -> Field
+    v612 = mul v610, v611
+    v613 = add v608, v612
+    store v613 at v533
+    v614 = load v534 -> Field
+    v615 = array_get v530, index u32 25 -> u8
+    v616 = cast v615 as Field
+    v617 = mul v616, v611
+    v618 = add v614, v617
+    store v618 at v534
+    v619 = mul v611, Field 256
+    store v619 at v531
+    v620 = load v533 -> Field
+    v621 = array_get v530, index u32 8 -> u8
+    v622 = cast v621 as Field
+    v623 = load v531 -> Field
+    v624 = mul v622, v623
+    v625 = add v620, v624
+    store v625 at v533
+    v626 = load v534 -> Field
+    v627 = array_get v530, index u32 24 -> u8
+    v628 = cast v627 as Field
+    v629 = mul v628, v623
+    v630 = add v626, v629
+    store v630 at v534
+    v631 = mul v623, Field 256
+    store v631 at v531
+    v632 = load v533 -> Field
+    v633 = array_get v530, index u32 7 -> u8
+    v634 = cast v633 as Field
+    v635 = load v531 -> Field
+    v636 = mul v634, v635
+    v637 = add v632, v636
+    store v637 at v533
+    v638 = load v534 -> Field
+    v639 = array_get v530, index u32 23 -> u8
+    v640 = cast v639 as Field
+    v641 = mul v640, v635
+    v642 = add v638, v641
+    store v642 at v534
+    v643 = mul v635, Field 256
+    store v643 at v531
+    v644 = load v533 -> Field
+    v645 = array_get v530, index u32 6 -> u8
+    v646 = cast v645 as Field
+    v647 = load v531 -> Field
+    v648 = mul v646, v647
+    v649 = add v644, v648
+    store v649 at v533
+    v650 = load v534 -> Field
+    v651 = array_get v530, index u32 22 -> u8
+    v652 = cast v651 as Field
+    v653 = mul v652, v647
+    v654 = add v650, v653
+    store v654 at v534
+    v655 = mul v647, Field 256
+    store v655 at v531
+    v656 = load v533 -> Field
+    v657 = array_get v530, index u32 5 -> u8
+    v658 = cast v657 as Field
+    v659 = load v531 -> Field
+    v660 = mul v658, v659
+    v661 = add v656, v660
+    store v661 at v533
+    v662 = load v534 -> Field
+    v663 = array_get v530, index u32 21 -> u8
+    v664 = cast v663 as Field
+    v665 = mul v664, v659
+    v666 = add v662, v665
+    store v666 at v534
+    v667 = mul v659, Field 256
+    store v667 at v531
+    v668 = load v533 -> Field
+    v669 = array_get v530, index u32 4 -> u8
+    v670 = cast v669 as Field
+    v671 = load v531 -> Field
+    v672 = mul v670, v671
+    v673 = add v668, v672
+    store v673 at v533
+    v674 = load v534 -> Field
+    v675 = array_get v530, index u32 20 -> u8
+    v676 = cast v675 as Field
+    v677 = mul v676, v671
+    v678 = add v674, v677
+    store v678 at v534
+    v679 = mul v671, Field 256
+    store v679 at v531
+    v680 = load v533 -> Field
+    v681 = array_get v530, index u32 3 -> u8
+    v682 = cast v681 as Field
+    v683 = load v531 -> Field
+    v684 = mul v682, v683
+    v685 = add v680, v684
+    store v685 at v533
+    v686 = load v534 -> Field
+    v687 = array_get v530, index u32 19 -> u8
+    v688 = cast v687 as Field
+    v689 = mul v688, v683
+    v690 = add v686, v689
+    store v690 at v534
+    v691 = mul v683, Field 256
+    store v691 at v531
+    v692 = load v533 -> Field
+    v693 = array_get v530, index u32 2 -> u8
+    v694 = cast v693 as Field
+    v695 = load v531 -> Field
+    v696 = mul v694, v695
+    v697 = add v692, v696
+    store v697 at v533
+    v698 = load v534 -> Field
+    v699 = array_get v530, index u32 18 -> u8
+    v700 = cast v699 as Field
+    v701 = mul v700, v695
+    v702 = add v698, v701
+    store v702 at v534
+    v703 = mul v695, Field 256
+    store v703 at v531
+    v704 = load v533 -> Field
+    v705 = array_get v530, index u32 1 -> u8
+    v706 = cast v705 as Field
+    v707 = load v531 -> Field
+    v708 = mul v706, v707
+    v709 = add v704, v708
+    store v709 at v533
+    v710 = load v534 -> Field
+    v711 = array_get v530, index u32 17 -> u8
+    v712 = cast v711 as Field
+    v713 = mul v712, v707
+    v714 = add v710, v713
+    store v714 at v534
+    v715 = mul v707, Field 256
+    store v715 at v531
+    v716 = load v533 -> Field
+    v717 = array_get v530, index u32 0 -> u8
+    v718 = cast v717 as Field
+    v719 = load v531 -> Field
+    v720 = mul v718, v719
+    v721 = add v716, v720
+    store v721 at v533
+    v722 = load v534 -> Field
+    v723 = array_get v530, index u32 16 -> u8
+    v724 = cast v723 as Field
+    v725 = mul v724, v719
+    v726 = add v722, v725
+    store v726 at v534
+    v727 = mul v719, Field 256
+    store v727 at v531
+    jmp b258()
+  b258():
+    v728 = load v534 -> Field
+    v729 = load v533 -> Field
+    v730 = load v531 -> Field
+    v731 = mul v729, v730
+    v732 = add v728, v731
+    store v732 at v8
+    v733 = allocate -> &mut Field
+    store Field 0 at v733
+    v734 = eq v4, Field 0
+    jmpif v734 then: b263, else: b259
+  b259():
+    v736 = call f1(v4, Field 0) -> u1
+    jmpif v736 then: b261, else: b260
+  b260():
+    v738, v739 = call f3(v4) -> (Field, Field)
+    range_check v738 to 128 bits
+    range_check v739 to 128 bits
+    v741 = mul Field 340282366920938463463374607431768211456, v739
+    v742 = add v738, v741
+    v743 = eq v4, v742
+    constrain v4 == v742
+    v746 = call f2(Field 53438638232309528389504892708671455233, v738) -> u1
+    v747 = sub Field 53438638232309528389504892708671455233, v738
+    v748 = sub v747, Field 1
+    v749 = cast v746 as Field
+    v750 = mul v749, Field 340282366920938463463374607431768211456
+    v751 = add v748, v750
+    v753 = sub Field 64323764613183177041862057485226039389, v739
+    v754 = cast v746 as Field
+    v755 = sub v753, v754
+    range_check v751 to 128 bits
+    range_check v755 to 128 bits
+    v757, v758 = call f3(Field 0) -> (Field, Field)
+    range_check v757 to 128 bits
+    range_check v758 to 128 bits
+    v759 = mul Field 340282366920938463463374607431768211456, v758
+    v760 = add v757, v759
+    v761 = eq Field 0, v760
+    constrain Field 0 == v760
+    v763 = call f2(Field 53438638232309528389504892708671455233, v757) -> u1
+    v764 = sub Field 53438638232309528389504892708671455233, v757
+    v765 = sub v764, Field 1
+    v766 = cast v763 as Field
+    v767 = mul v766, Field 340282366920938463463374607431768211456
+    v768 = add v765, v767
+    v769 = sub Field 64323764613183177041862057485226039389, v758
+    v770 = cast v763 as Field
+    v771 = sub v769, v770
+    range_check v768 to 128 bits
+    range_check v771 to 128 bits
+    v773 = call f2(v738, v757) -> u1
+    v774 = sub v738, v757
+    v775 = sub v774, Field 1
+    v776 = cast v773 as Field
+    v777 = mul v776, Field 340282366920938463463374607431768211456
+    v778 = add v775, v777
+    v779 = sub v739, v758
+    v780 = cast v773 as Field
+    v781 = sub v779, v780
+    range_check v778 to 128 bits
+    range_check v781 to 128 bits
+    jmp b262(u1 1)
+  b261():
+    v783, v784 = call f3(Field 0) -> (Field, Field)
+    range_check v783 to 128 bits
+    range_check v784 to 128 bits
+    v785 = mul Field 340282366920938463463374607431768211456, v784
+    v786 = add v783, v785
+    v787 = eq Field 0, v786
+    constrain Field 0 == v786
+    v789 = call f2(Field 53438638232309528389504892708671455233, v783) -> u1
+    v790 = sub Field 53438638232309528389504892708671455233, v783
+    v791 = sub v790, Field 1
+    v792 = cast v789 as Field
+    v793 = mul v792, Field 340282366920938463463374607431768211456
+    v794 = add v791, v793
+    v795 = sub Field 64323764613183177041862057485226039389, v784
+    v796 = cast v789 as Field
+    v797 = sub v795, v796
+    range_check v794 to 128 bits
+    range_check v797 to 128 bits
+    v799, v800 = call f3(v4) -> (Field, Field)
+    range_check v799 to 128 bits
+    range_check v800 to 128 bits
+    v801 = mul Field 340282366920938463463374607431768211456, v800
+    v802 = add v799, v801
+    v803 = eq v4, v802
+    constrain v4 == v802
+    v805 = call f2(Field 53438638232309528389504892708671455233, v799) -> u1
+    v806 = sub Field 53438638232309528389504892708671455233, v799
+    v807 = sub v806, Field 1
+    v808 = cast v805 as Field
+    v809 = mul v808, Field 340282366920938463463374607431768211456
+    v810 = add v807, v809
+    v811 = sub Field 64323764613183177041862057485226039389, v800
+    v812 = cast v805 as Field
+    v813 = sub v811, v812
+    range_check v810 to 128 bits
+    range_check v813 to 128 bits
+    v815 = call f2(v783, v799) -> u1
+    v816 = sub v783, v799
+    v817 = sub v816, Field 1
+    v818 = cast v815 as Field
+    v819 = mul v818, Field 340282366920938463463374607431768211456
+    v820 = add v817, v819
+    v821 = sub v784, v800
+    v822 = cast v815 as Field
+    v823 = sub v821, v822
+    range_check v820 to 128 bits
+    range_check v823 to 128 bits
+    jmp b262(u1 0)
+  b262(v5: u1):
+    jmp b264(v5)
+  b263():
+    jmp b264(u1 0)
+  b264(v6: u1):
+    jmpif v6 then: b265, else: b266
+  b265():
+    store Field 1 at v733
+    jmp b266()
+  b266():
+    v824 = load v733 -> Field
+    v825 = load v8 -> Field
+    v826 = sub v824, v825
+    return v826
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Simplifying (2nd):
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v7 = allocate -> &mut Field
+    v8 = allocate -> &mut Field
+    store Field 0 at v8
+    v12 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v42 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v43 = allocate -> &mut u1
+    store u1 0 at v43
+    v45 = load v43 -> u1
+    v46 = not v45
+    jmpif v46 then: b1, else: b4
+  b1():
+    v48 = array_get v12, index u32 0 -> u8
+    v49 = eq v48, u8 48
+    v50 = not v49
+    jmpif v50 then: b2, else: b3
+  b2():
+    v51 = array_get v12, index u32 0 -> u8
+    v52 = lt v51, u8 48
+    constrain v52 == u1 1
+    store u1 1 at v43
+    jmp b3()
+  b3():
+    jmp b4()
+  b4():
+    v54 = load v43 -> u1
+    v55 = not v54
+    jmpif v55 then: b5, else: b8
+  b5():
+    v57 = array_get v12, index u32 1 -> u8
+    v58 = eq v57, u8 100
+    v59 = not v58
+    jmpif v59 then: b6, else: b7
+  b6():
+    v60 = array_get v12, index u32 1 -> u8
+    v61 = lt v60, u8 100
+    constrain v61 == u1 1
+    store u1 1 at v43
+    jmp b7()
+  b7():
+    jmp b8()
+  b8():
+    v62 = load v43 -> u1
+    v63 = not v62
+    jmpif v63 then: b9, else: b12
+  b9():
+    v65 = array_get v12, index u32 2 -> u8
+    v66 = eq v65, u8 78
+    v67 = not v66
+    jmpif v67 then: b10, else: b11
+  b10():
+    v68 = array_get v12, index u32 2 -> u8
+    v69 = lt v68, u8 78
+    constrain v69 == u1 1
+    store u1 1 at v43
+    jmp b11()
+  b11():
+    jmp b12()
+  b12():
+    v70 = load v43 -> u1
+    v71 = not v70
+    jmpif v71 then: b13, else: b16
+  b13():
+    v73 = array_get v12, index u32 3 -> u8
+    v74 = eq v73, u8 114
+    v75 = not v74
+    jmpif v75 then: b14, else: b15
+  b14():
+    v76 = array_get v12, index u32 3 -> u8
+    v77 = lt v76, u8 114
+    constrain v77 == u1 1
+    store u1 1 at v43
+    jmp b15()
+  b15():
+    jmp b16()
+  b16():
+    v78 = load v43 -> u1
+    v79 = not v78
+    jmpif v79 then: b17, else: b20
+  b17():
+    v81 = array_get v12, index u32 4 -> u8
+    v82 = eq v81, u8 225
+    v83 = not v82
+    jmpif v83 then: b18, else: b19
+  b18():
+    v84 = array_get v12, index u32 4 -> u8
+    v85 = lt v84, u8 225
+    constrain v85 == u1 1
+    store u1 1 at v43
+    jmp b19()
+  b19():
+    jmp b20()
+  b20():
+    v86 = load v43 -> u1
+    v87 = not v86
+    jmpif v87 then: b21, else: b24
+  b21():
+    v89 = array_get v12, index u32 5 -> u8
+    v90 = eq v89, u8 49
+    v91 = not v90
+    jmpif v91 then: b22, else: b23
+  b22():
+    v92 = array_get v12, index u32 5 -> u8
+    v93 = lt v92, u8 49
+    constrain v93 == u1 1
+    store u1 1 at v43
+    jmp b23()
+  b23():
+    jmp b24()
+  b24():
+    v94 = load v43 -> u1
+    v95 = not v94
+    jmpif v95 then: b25, else: b28
+  b25():
+    v97 = array_get v12, index u32 6 -> u8
+    v98 = eq v97, u8 160
+    v99 = not v98
+    jmpif v99 then: b26, else: b27
+  b26():
+    v100 = array_get v12, index u32 6 -> u8
+    v101 = lt v100, u8 160
+    constrain v101 == u1 1
+    store u1 1 at v43
+    jmp b27()
+  b27():
+    jmp b28()
+  b28():
+    v102 = load v43 -> u1
+    v103 = not v102
+    jmpif v103 then: b29, else: b32
+  b29():
+    v105 = array_get v12, index u32 7 -> u8
+    v106 = eq v105, u8 41
+    v107 = not v106
+    jmpif v107 then: b30, else: b31
+  b30():
+    v108 = array_get v12, index u32 7 -> u8
+    v109 = lt v108, u8 41
+    constrain v109 == u1 1
+    store u1 1 at v43
+    jmp b31()
+  b31():
+    jmp b32()
+  b32():
+    v110 = load v43 -> u1
+    v111 = not v110
+    jmpif v111 then: b33, else: b36
+  b33():
+    v113 = array_get v12, index u32 8 -> u8
+    v114 = eq v113, u8 184
+    v115 = not v114
+    jmpif v115 then: b34, else: b35
+  b34():
+    v116 = array_get v12, index u32 8 -> u8
+    v117 = lt v116, u8 184
+    constrain v117 == u1 1
+    store u1 1 at v43
+    jmp b35()
+  b35():
+    jmp b36()
+  b36():
+    v118 = load v43 -> u1
+    v119 = not v118
+    jmpif v119 then: b37, else: b40
+  b37():
+    v121 = array_get v12, index u32 9 -> u8
+    v122 = eq v121, u8 80
+    v123 = not v122
+    jmpif v123 then: b38, else: b39
+  b38():
+    v124 = array_get v12, index u32 9 -> u8
+    v125 = lt v124, u8 80
+    constrain v125 == u1 1
+    store u1 1 at v43
+    jmp b39()
+  b39():
+    jmp b40()
+  b40():
+    v126 = load v43 -> u1
+    v127 = not v126
+    jmpif v127 then: b41, else: b44
+  b41():
+    v129 = array_get v12, index u32 10 -> u8
+    v130 = eq v129, u8 69
+    v131 = not v130
+    jmpif v131 then: b42, else: b43
+  b42():
+    v132 = array_get v12, index u32 10 -> u8
+    v133 = lt v132, u8 69
+    constrain v133 == u1 1
+    store u1 1 at v43
+    jmp b43()
+  b43():
+    jmp b44()
+  b44():
+    v134 = load v43 -> u1
+    v135 = not v134
+    jmpif v135 then: b45, else: b48
+  b45():
+    v137 = array_get v12, index u32 11 -> u8
+    v138 = eq v137, u8 182
+    v139 = not v138
+    jmpif v139 then: b46, else: b47
+  b46():
+    v140 = array_get v12, index u32 11 -> u8
+    v141 = lt v140, u8 182
+    constrain v141 == u1 1
+    store u1 1 at v43
+    jmp b47()
+  b47():
+    jmp b48()
+  b48():
+    v142 = load v43 -> u1
+    v143 = not v142
+    jmpif v143 then: b49, else: b52
+  b49():
+    v145 = array_get v12, index u32 12 -> u8
+    v146 = eq v145, u8 129
+    v147 = not v146
+    jmpif v147 then: b50, else: b51
+  b50():
+    v148 = array_get v12, index u32 12 -> u8
+    v149 = lt v148, u8 129
+    constrain v149 == u1 1
+    store u1 1 at v43
+    jmp b51()
+  b51():
+    jmp b52()
+  b52():
+    v150 = load v43 -> u1
+    v151 = not v150
+    jmpif v151 then: b53, else: b56
+  b53():
+    v153 = array_get v12, index u32 13 -> u8
+    v154 = eq v153, u8 129
+    v155 = not v154
+    jmpif v155 then: b54, else: b55
+  b54():
+    v156 = array_get v12, index u32 13 -> u8
+    v157 = lt v156, u8 129
+    constrain v157 == u1 1
+    store u1 1 at v43
+    jmp b55()
+  b55():
+    jmp b56()
+  b56():
+    v158 = load v43 -> u1
+    v159 = not v158
+    jmpif v159 then: b57, else: b60
+  b57():
+    v161 = array_get v12, index u32 14 -> u8
+    v162 = eq v161, u8 88
+    v163 = not v162
+    jmpif v163 then: b58, else: b59
+  b58():
+    v164 = array_get v12, index u32 14 -> u8
+    v165 = lt v164, u8 88
+    constrain v165 == u1 1
+    store u1 1 at v43
+    jmp b59()
+  b59():
+    jmp b60()
+  b60():
+    v166 = load v43 -> u1
+    v167 = not v166
+    jmpif v167 then: b61, else: b64
+  b61():
+    v169 = array_get v12, index u32 15 -> u8
+    v170 = eq v169, u8 93
+    v171 = not v170
+    jmpif v171 then: b62, else: b63
+  b62():
+    v172 = array_get v12, index u32 15 -> u8
+    v173 = lt v172, u8 93
+    constrain v173 == u1 1
+    store u1 1 at v43
+    jmp b63()
+  b63():
+    jmp b64()
+  b64():
+    v174 = load v43 -> u1
+    v175 = not v174
+    jmpif v175 then: b65, else: b68
+  b65():
+    v177 = array_get v12, index u32 16 -> u8
+    v178 = eq v177, u8 40
+    v179 = not v178
+    jmpif v179 then: b66, else: b67
+  b66():
+    v180 = array_get v12, index u32 16 -> u8
+    v181 = lt v180, u8 40
+    constrain v181 == u1 1
+    store u1 1 at v43
+    jmp b67()
+  b67():
+    jmp b68()
+  b68():
+    v182 = load v43 -> u1
+    v183 = not v182
+    jmpif v183 then: b69, else: b72
+  b69():
+    v185 = array_get v12, index u32 17 -> u8
+    v186 = eq v185, u8 51
+    v187 = not v186
+    jmpif v187 then: b70, else: b71
+  b70():
+    v188 = array_get v12, index u32 17 -> u8
+    v189 = lt v188, u8 51
+    constrain v189 == u1 1
+    store u1 1 at v43
+    jmp b71()
+  b71():
+    jmp b72()
+  b72():
+    v190 = load v43 -> u1
+    v191 = not v190
+    jmpif v191 then: b73, else: b76
+  b73():
+    v193 = array_get v12, index u32 18 -> u8
+    v194 = eq v193, u8 232
+    v195 = not v194
+    jmpif v195 then: b74, else: b75
+  b74():
+    v196 = array_get v12, index u32 18 -> u8
+    v197 = lt v196, u8 232
+    constrain v197 == u1 1
+    store u1 1 at v43
+    jmp b75()
+  b75():
+    jmp b76()
+  b76():
+    v198 = load v43 -> u1
+    v199 = not v198
+    jmpif v199 then: b77, else: b80
+  b77():
+    v201 = array_get v12, index u32 19 -> u8
+    v202 = eq v201, u8 72
+    v203 = not v202
+    jmpif v203 then: b78, else: b79
+  b78():
+    v204 = array_get v12, index u32 19 -> u8
+    v205 = lt v204, u8 72
+    constrain v205 == u1 1
+    store u1 1 at v43
+    jmp b79()
+  b79():
+    jmp b80()
+  b80():
+    v206 = load v43 -> u1
+    v207 = not v206
+    jmpif v207 then: b81, else: b84
+  b81():
+    v209 = array_get v12, index u32 20 -> u8
+    v210 = eq v209, u8 121
+    v211 = not v210
+    jmpif v211 then: b82, else: b83
+  b82():
+    v212 = array_get v12, index u32 20 -> u8
+    v213 = lt v212, u8 121
+    constrain v213 == u1 1
+    store u1 1 at v43
+    jmp b83()
+  b83():
+    jmp b84()
+  b84():
+    v214 = load v43 -> u1
+    v215 = not v214
+    jmpif v215 then: b85, else: b88
+  b85():
+    v217 = array_get v12, index u32 21 -> u8
+    v218 = eq v217, u8 185
+    v219 = not v218
+    jmpif v219 then: b86, else: b87
+  b86():
+    v220 = array_get v12, index u32 21 -> u8
+    v221 = lt v220, u8 185
+    constrain v221 == u1 1
+    store u1 1 at v43
+    jmp b87()
+  b87():
+    jmp b88()
+  b88():
+    v222 = load v43 -> u1
+    v223 = not v222
+    jmpif v223 then: b89, else: b92
+  b89():
+    v225 = array_get v12, index u32 22 -> u8
+    v226 = eq v225, u8 112
+    v227 = not v226
+    jmpif v227 then: b90, else: b91
+  b90():
+    v228 = array_get v12, index u32 22 -> u8
+    v229 = lt v228, u8 112
+    constrain v229 == u1 1
+    store u1 1 at v43
+    jmp b91()
+  b91():
+    jmp b92()
+  b92():
+    v230 = load v43 -> u1
+    v231 = not v230
+    jmpif v231 then: b93, else: b96
+  b93():
+    v233 = array_get v12, index u32 23 -> u8
+    v234 = eq v233, u8 145
+    v235 = not v234
+    jmpif v235 then: b94, else: b95
+  b94():
+    v236 = array_get v12, index u32 23 -> u8
+    v237 = lt v236, u8 145
+    constrain v237 == u1 1
+    store u1 1 at v43
+    jmp b95()
+  b95():
+    jmp b96()
+  b96():
+    v238 = load v43 -> u1
+    v239 = not v238
+    jmpif v239 then: b97, else: b100
+  b97():
+    v241 = array_get v12, index u32 24 -> u8
+    v242 = eq v241, u8 67
+    v243 = not v242
+    jmpif v243 then: b98, else: b99
+  b98():
+    v244 = array_get v12, index u32 24 -> u8
+    v245 = lt v244, u8 67
+    constrain v245 == u1 1
+    store u1 1 at v43
+    jmp b99()
+  b99():
+    jmp b100()
+  b100():
+    v246 = load v43 -> u1
+    v247 = not v246
+    jmpif v247 then: b101, else: b104
+  b101():
+    v249 = array_get v12, index u32 25 -> u8
+    v250 = eq v249, u8 225
+    v251 = not v250
+    jmpif v251 then: b102, else: b103
+  b102():
+    v252 = array_get v12, index u32 25 -> u8
+    v253 = lt v252, u8 225
+    constrain v253 == u1 1
+    store u1 1 at v43
+    jmp b103()
+  b103():
+    jmp b104()
+  b104():
+    v254 = load v43 -> u1
+    v255 = not v254
+    jmpif v255 then: b105, else: b108
+  b105():
+    v257 = array_get v12, index u32 26 -> u8
+    v258 = eq v257, u8 245
+    v259 = not v258
+    jmpif v259 then: b106, else: b107
+  b106():
+    v260 = array_get v12, index u32 26 -> u8
+    v261 = lt v260, u8 245
+    constrain v261 == u1 1
+    store u1 1 at v43
+    jmp b107()
+  b107():
+    jmp b108()
+  b108():
+    v262 = load v43 -> u1
+    v263 = not v262
+    jmpif v263 then: b109, else: b112
+  b109():
+    v265 = array_get v12, index u32 27 -> u8
+    v266 = eq v265, u8 147
+    v267 = not v266
+    jmpif v267 then: b110, else: b111
+  b110():
+    v268 = array_get v12, index u32 27 -> u8
+    v269 = lt v268, u8 147
+    constrain v269 == u1 1
+    store u1 1 at v43
+    jmp b111()
+  b111():
+    jmp b112()
+  b112():
+    v270 = load v43 -> u1
+    v271 = not v270
+    jmpif v271 then: b113, else: b116
+  b113():
+    v273 = array_get v12, index u32 28 -> u8
+    v274 = eq v273, u8 240
+    v275 = not v274
+    jmpif v275 then: b114, else: b115
+  b114():
+    v276 = array_get v12, index u32 28 -> u8
+    v277 = lt v276, u8 240
+    constrain v277 == u1 1
+    store u1 1 at v43
+    jmp b115()
+  b115():
+    jmp b116()
+  b116():
+    v278 = load v43 -> u1
+    v279 = not v278
+    jmpif v279 then: b117, else: b120
+  b117():
+    v281 = array_get v12, index u32 29 -> u8
+    v282 = eq v281, u8 0
+    v283 = not v282
+    jmpif v283 then: b118, else: b119
+  b118():
+    v284 = array_get v12, index u32 29 -> u8
+    constrain u1 0 == u1 1
+    store u1 1 at v43
+    jmp b119()
+  b119():
+    jmp b120()
+  b120():
+    v285 = load v43 -> u1
+    v286 = not v285
+    jmpif v286 then: b121, else: b124
+  b121():
+    v288 = array_get v12, index u32 30 -> u8
+    v289 = eq v288, u8 0
+    v290 = not v289
+    jmpif v290 then: b122, else: b123
+  b122():
+    v291 = array_get v12, index u32 30 -> u8
+    constrain u1 0 == u1 1
+    store u1 1 at v43
+    jmp b123()
+  b123():
+    jmp b124()
+  b124():
+    v292 = load v43 -> u1
+    v293 = not v292
+    jmpif v293 then: b125, else: b128
+  b125():
+    v295 = array_get v12, index u32 31 -> u8
+    v296 = eq v295, u8 1
+    v297 = not v296
+    jmpif v297 then: b126, else: b127
+  b126():
+    v298 = array_get v12, index u32 31 -> u8
+    v299 = eq v298, u8 0
+    constrain v298 == u8 0
+    store u1 1 at v43
+    jmp b127()
+  b127():
+    jmp b128()
+  b128():
+    v300 = load v43 -> u1
+    constrain v300 == u1 1
+    v301 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v302 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v303 = allocate -> &mut u1
+    store u1 0 at v303
+    v304 = load v303 -> u1
+    v305 = not v304
+    jmpif v305 then: b129, else: b130
+  b129():
+    store u1 1 at v303
+    jmp b130()
+  b130():
+    v306 = load v303 -> u1
+    v307 = not v306
+    jmpif v307 then: b131, else: b132
+  b131():
+    store u1 1 at v303
+    jmp b132()
+  b132():
+    v308 = load v303 -> u1
+    v309 = not v308
+    jmpif v309 then: b133, else: b134
+  b133():
+    store u1 1 at v303
+    jmp b134()
+  b134():
+    v310 = load v303 -> u1
+    v311 = not v310
+    jmpif v311 then: b135, else: b136
+  b135():
+    store u1 1 at v303
+    jmp b136()
+  b136():
+    v312 = load v303 -> u1
+    v313 = not v312
+    jmpif v313 then: b137, else: b138
+  b137():
+    store u1 1 at v303
+    jmp b138()
+  b138():
+    v314 = load v303 -> u1
+    v315 = not v314
+    jmpif v315 then: b139, else: b140
+  b139():
+    store u1 1 at v303
+    jmp b140()
+  b140():
+    v316 = load v303 -> u1
+    v317 = not v316
+    jmpif v317 then: b141, else: b142
+  b141():
+    store u1 1 at v303
+    jmp b142()
+  b142():
+    v318 = load v303 -> u1
+    v319 = not v318
+    jmpif v319 then: b143, else: b144
+  b143():
+    store u1 1 at v303
+    jmp b144()
+  b144():
+    v320 = load v303 -> u1
+    v321 = not v320
+    jmpif v321 then: b145, else: b146
+  b145():
+    store u1 1 at v303
+    jmp b146()
+  b146():
+    v322 = load v303 -> u1
+    v323 = not v322
+    jmpif v323 then: b147, else: b148
+  b147():
+    store u1 1 at v303
+    jmp b148()
+  b148():
+    v324 = load v303 -> u1
+    v325 = not v324
+    jmpif v325 then: b149, else: b150
+  b149():
+    store u1 1 at v303
+    jmp b150()
+  b150():
+    v326 = load v303 -> u1
+    v327 = not v326
+    jmpif v327 then: b151, else: b152
+  b151():
+    store u1 1 at v303
+    jmp b152()
+  b152():
+    v328 = load v303 -> u1
+    v329 = not v328
+    jmpif v329 then: b153, else: b154
+  b153():
+    store u1 1 at v303
+    jmp b154()
+  b154():
+    v330 = load v303 -> u1
+    v331 = not v330
+    jmpif v331 then: b155, else: b156
+  b155():
+    store u1 1 at v303
+    jmp b156()
+  b156():
+    v332 = load v303 -> u1
+    v333 = not v332
+    jmpif v333 then: b157, else: b158
+  b157():
+    store u1 1 at v303
+    jmp b158()
+  b158():
+    v334 = load v303 -> u1
+    v335 = not v334
+    jmpif v335 then: b159, else: b160
+  b159():
+    store u1 1 at v303
+    jmp b160()
+  b160():
+    v336 = load v303 -> u1
+    v337 = not v336
+    jmpif v337 then: b161, else: b162
+  b161():
+    store u1 1 at v303
+    jmp b162()
+  b162():
+    v338 = load v303 -> u1
+    v339 = not v338
+    jmpif v339 then: b163, else: b164
+  b163():
+    store u1 1 at v303
+    jmp b164()
+  b164():
+    v340 = load v303 -> u1
+    v341 = not v340
+    jmpif v341 then: b165, else: b166
+  b165():
+    store u1 1 at v303
+    jmp b166()
+  b166():
+    v342 = load v303 -> u1
+    v343 = not v342
+    jmpif v343 then: b167, else: b168
+  b167():
+    store u1 1 at v303
+    jmp b168()
+  b168():
+    v344 = load v303 -> u1
+    v345 = not v344
+    jmpif v345 then: b169, else: b170
+  b169():
+    store u1 1 at v303
+    jmp b170()
+  b170():
+    v346 = load v303 -> u1
+    v347 = not v346
+    jmpif v347 then: b171, else: b172
+  b171():
+    store u1 1 at v303
+    jmp b172()
+  b172():
+    v348 = load v303 -> u1
+    v349 = not v348
+    jmpif v349 then: b173, else: b174
+  b173():
+    store u1 1 at v303
+    jmp b174()
+  b174():
+    v350 = load v303 -> u1
+    v351 = not v350
+    jmpif v351 then: b175, else: b176
+  b175():
+    store u1 1 at v303
+    jmp b176()
+  b176():
+    v352 = load v303 -> u1
+    v353 = not v352
+    jmpif v353 then: b177, else: b178
+  b177():
+    store u1 1 at v303
+    jmp b178()
+  b178():
+    v354 = load v303 -> u1
+    v355 = not v354
+    jmpif v355 then: b179, else: b180
+  b179():
+    store u1 1 at v303
+    jmp b180()
+  b180():
+    v356 = load v303 -> u1
+    v357 = not v356
+    jmpif v357 then: b181, else: b182
+  b181():
+    store u1 1 at v303
+    jmp b182()
+  b182():
+    v358 = load v303 -> u1
+    v359 = not v358
+    jmpif v359 then: b183, else: b184
+  b183():
+    store u1 1 at v303
+    jmp b184()
+  b184():
+    v360 = load v303 -> u1
+    v361 = not v360
+    jmpif v361 then: b185, else: b186
+  b185():
+    store u1 1 at v303
+    jmp b186()
+  b186():
+    v362 = load v303 -> u1
+    v363 = not v362
+    jmpif v363 then: b187, else: b188
+  b187():
+    jmp b188()
+  b188():
+    v364 = load v303 -> u1
+    v365 = not v364
+    jmpif v365 then: b189, else: b190
+  b189():
+    jmp b190()
+  b190():
+    v366 = load v303 -> u1
+    v367 = not v366
+    jmpif v367 then: b191, else: b192
+  b191():
+    store u1 1 at v303
+    jmp b192()
+  b192():
+    v368 = load v303 -> u1
+    constrain v368 == u1 1
+    v369 = allocate -> &mut [u8; 32]
+    store v301 at v369
+    v370 = load v369 -> [u8; 32]
+    v371 = array_get v12, index u32 0 -> u8
+    v372 = array_get v370, index u32 0 -> u8
+    v373 = xor v371, v372
+    v374 = array_set v370, index u32 0, value v373
+    store v374 at v369
+    v375 = load v369 -> [u8; 32]
+    v376 = array_get v12, index u32 1 -> u8
+    v377 = array_get v375, index u32 1 -> u8
+    v378 = xor v376, v377
+    v379 = array_set v375, index u32 1, value v378
+    store v379 at v369
+    v380 = load v369 -> [u8; 32]
+    v381 = array_get v12, index u32 2 -> u8
+    v382 = array_get v380, index u32 2 -> u8
+    v383 = xor v381, v382
+    v384 = array_set v380, index u32 2, value v383
+    store v384 at v369
+    v385 = load v369 -> [u8; 32]
+    v386 = array_get v12, index u32 3 -> u8
+    v387 = array_get v385, index u32 3 -> u8
+    v388 = xor v386, v387
+    v389 = array_set v385, index u32 3, value v388
+    store v389 at v369
+    v390 = load v369 -> [u8; 32]
+    v391 = array_get v12, index u32 4 -> u8
+    v392 = array_get v390, index u32 4 -> u8
+    v393 = xor v391, v392
+    v394 = array_set v390, index u32 4, value v393
+    store v394 at v369
+    v395 = load v369 -> [u8; 32]
+    v396 = array_get v12, index u32 5 -> u8
+    v397 = array_get v395, index u32 5 -> u8
+    v398 = xor v396, v397
+    v399 = array_set v395, index u32 5, value v398
+    store v399 at v369
+    v400 = load v369 -> [u8; 32]
+    v401 = array_get v12, index u32 6 -> u8
+    v402 = array_get v400, index u32 6 -> u8
+    v403 = xor v401, v402
+    v404 = array_set v400, index u32 6, value v403
+    store v404 at v369
+    v405 = load v369 -> [u8; 32]
+    v406 = array_get v12, index u32 7 -> u8
+    v407 = array_get v405, index u32 7 -> u8
+    v408 = xor v406, v407
+    v409 = array_set v405, index u32 7, value v408
+    store v409 at v369
+    v410 = load v369 -> [u8; 32]
+    v411 = array_get v12, index u32 8 -> u8
+    v412 = array_get v410, index u32 8 -> u8
+    v413 = xor v411, v412
+    v414 = array_set v410, index u32 8, value v413
+    store v414 at v369
+    v415 = load v369 -> [u8; 32]
+    v416 = array_get v12, index u32 9 -> u8
+    v417 = array_get v415, index u32 9 -> u8
+    v418 = xor v416, v417
+    v419 = array_set v415, index u32 9, value v418
+    store v419 at v369
+    v420 = load v369 -> [u8; 32]
+    v421 = array_get v12, index u32 10 -> u8
+    v422 = array_get v420, index u32 10 -> u8
+    v423 = xor v421, v422
+    v424 = array_set v420, index u32 10, value v423
+    store v424 at v369
+    v425 = load v369 -> [u8; 32]
+    v426 = array_get v12, index u32 11 -> u8
+    v427 = array_get v425, index u32 11 -> u8
+    v428 = xor v426, v427
+    v429 = array_set v425, index u32 11, value v428
+    store v429 at v369
+    v430 = load v369 -> [u8; 32]
+    v431 = array_get v12, index u32 12 -> u8
+    v432 = array_get v430, index u32 12 -> u8
+    v433 = xor v431, v432
+    v434 = array_set v430, index u32 12, value v433
+    store v434 at v369
+    v435 = load v369 -> [u8; 32]
+    v436 = array_get v12, index u32 13 -> u8
+    v437 = array_get v435, index u32 13 -> u8
+    v438 = xor v436, v437
+    v439 = array_set v435, index u32 13, value v438
+    store v439 at v369
+    v440 = load v369 -> [u8; 32]
+    v441 = array_get v12, index u32 14 -> u8
+    v442 = array_get v440, index u32 14 -> u8
+    v443 = xor v441, v442
+    v444 = array_set v440, index u32 14, value v443
+    store v444 at v369
+    v445 = load v369 -> [u8; 32]
+    v446 = array_get v12, index u32 15 -> u8
+    v447 = array_get v445, index u32 15 -> u8
+    v448 = xor v446, v447
+    v449 = array_set v445, index u32 15, value v448
+    store v449 at v369
+    v450 = load v369 -> [u8; 32]
+    v451 = array_get v12, index u32 16 -> u8
+    v452 = array_get v450, index u32 16 -> u8
+    v453 = xor v451, v452
+    v454 = array_set v450, index u32 16, value v453
+    store v454 at v369
+    v455 = load v369 -> [u8; 32]
+    v456 = array_get v12, index u32 17 -> u8
+    v457 = array_get v455, index u32 17 -> u8
+    v458 = xor v456, v457
+    v459 = array_set v455, index u32 17, value v458
+    store v459 at v369
+    v460 = load v369 -> [u8; 32]
+    v461 = array_get v12, index u32 18 -> u8
+    v462 = array_get v460, index u32 18 -> u8
+    v463 = xor v461, v462
+    v464 = array_set v460, index u32 18, value v463
+    store v464 at v369
+    v465 = load v369 -> [u8; 32]
+    v466 = array_get v12, index u32 19 -> u8
+    v467 = array_get v465, index u32 19 -> u8
+    v468 = xor v466, v467
+    v469 = array_set v465, index u32 19, value v468
+    store v469 at v369
+    v470 = load v369 -> [u8; 32]
+    v471 = array_get v12, index u32 20 -> u8
+    v472 = array_get v470, index u32 20 -> u8
+    v473 = xor v471, v472
+    v474 = array_set v470, index u32 20, value v473
+    store v474 at v369
+    v475 = load v369 -> [u8; 32]
+    v476 = array_get v12, index u32 21 -> u8
+    v477 = array_get v475, index u32 21 -> u8
+    v478 = xor v476, v477
+    v479 = array_set v475, index u32 21, value v478
+    store v479 at v369
+    v480 = load v369 -> [u8; 32]
+    v481 = array_get v12, index u32 22 -> u8
+    v482 = array_get v480, index u32 22 -> u8
+    v483 = xor v481, v482
+    v484 = array_set v480, index u32 22, value v483
+    store v484 at v369
+    v485 = load v369 -> [u8; 32]
+    v486 = array_get v12, index u32 23 -> u8
+    v487 = array_get v485, index u32 23 -> u8
+    v488 = xor v486, v487
+    v489 = array_set v485, index u32 23, value v488
+    store v489 at v369
+    v490 = load v369 -> [u8; 32]
+    v491 = array_get v12, index u32 24 -> u8
+    v492 = array_get v490, index u32 24 -> u8
+    v493 = xor v491, v492
+    v494 = array_set v490, index u32 24, value v493
+    store v494 at v369
+    v495 = load v369 -> [u8; 32]
+    v496 = array_get v12, index u32 25 -> u8
+    v497 = array_get v495, index u32 25 -> u8
+    v498 = xor v496, v497
+    v499 = array_set v495, index u32 25, value v498
+    store v499 at v369
+    v500 = load v369 -> [u8; 32]
+    v501 = array_get v12, index u32 26 -> u8
+    v502 = array_get v500, index u32 26 -> u8
+    v503 = xor v501, v502
+    v504 = array_set v500, index u32 26, value v503
+    store v504 at v369
+    v505 = load v369 -> [u8; 32]
+    v506 = array_get v12, index u32 27 -> u8
+    v507 = array_get v505, index u32 27 -> u8
+    v508 = xor v506, v507
+    v509 = array_set v505, index u32 27, value v508
+    store v509 at v369
+    v510 = load v369 -> [u8; 32]
+    v511 = array_get v12, index u32 28 -> u8
+    v512 = array_get v510, index u32 28 -> u8
+    v513 = xor v511, v512
+    v514 = array_set v510, index u32 28, value v513
+    store v514 at v369
+    v515 = load v369 -> [u8; 32]
+    v516 = array_get v12, index u32 29 -> u8
+    v517 = array_get v515, index u32 29 -> u8
+    v518 = xor v516, v517
+    v519 = array_set v515, index u32 29, value v518
+    store v519 at v369
+    v520 = load v369 -> [u8; 32]
+    v521 = array_get v12, index u32 30 -> u8
+    v522 = array_get v520, index u32 30 -> u8
+    v523 = xor v521, v522
+    v524 = array_set v520, index u32 30, value v523
+    store v524 at v369
+    v525 = load v369 -> [u8; 32]
+    v526 = array_get v12, index u32 31 -> u8
+    v527 = array_get v525, index u32 31 -> u8
+    v528 = xor v526, v527
+    v529 = array_set v525, index u32 31, value v528
+    store v529 at v369
+    v530 = load v369 -> [u8; 32]
+    v531 = allocate -> &mut Field
+    store Field 1 at v531
+    v533 = allocate -> &mut Field
+    store Field 0 at v533
+    v534 = allocate -> &mut Field
+    store Field 0 at v534
+    v535 = load v533 -> Field
+    v536 = array_get v530, index u32 15 -> u8
+    v537 = cast v536 as Field
+    v538 = load v531 -> Field
+    v539 = mul v537, v538
+    v540 = add v535, v539
+    store v540 at v533
+    v541 = load v534 -> Field
+    v542 = array_get v530, index u32 31 -> u8
+    v543 = cast v542 as Field
+    v544 = mul v543, v538
+    v545 = add v541, v544
+    store v545 at v534
+    v547 = mul v538, Field 256
+    store v547 at v531
+    v548 = load v533 -> Field
+    v549 = array_get v530, index u32 14 -> u8
+    v550 = cast v549 as Field
+    v551 = load v531 -> Field
+    v552 = mul v550, v551
+    v553 = add v548, v552
+    store v553 at v533
+    v554 = load v534 -> Field
+    v555 = array_get v530, index u32 30 -> u8
+    v556 = cast v555 as Field
+    v557 = mul v556, v551
+    v558 = add v554, v557
+    store v558 at v534
+    v559 = mul v551, Field 256
+    store v559 at v531
+    v560 = load v533 -> Field
+    v561 = array_get v530, index u32 13 -> u8
+    v562 = cast v561 as Field
+    v563 = load v531 -> Field
+    v564 = mul v562, v563
+    v565 = add v560, v564
+    store v565 at v533
+    v566 = load v534 -> Field
+    v567 = array_get v530, index u32 29 -> u8
+    v568 = cast v567 as Field
+    v569 = mul v568, v563
+    v570 = add v566, v569
+    store v570 at v534
+    v571 = mul v563, Field 256
+    store v571 at v531
+    v572 = load v533 -> Field
+    v573 = array_get v530, index u32 12 -> u8
+    v574 = cast v573 as Field
+    v575 = load v531 -> Field
+    v576 = mul v574, v575
+    v577 = add v572, v576
+    store v577 at v533
+    v578 = load v534 -> Field
+    v579 = array_get v530, index u32 28 -> u8
+    v580 = cast v579 as Field
+    v581 = mul v580, v575
+    v582 = add v578, v581
+    store v582 at v534
+    v583 = mul v575, Field 256
+    store v583 at v531
+    v584 = load v533 -> Field
+    v585 = array_get v530, index u32 11 -> u8
+    v586 = cast v585 as Field
+    v587 = load v531 -> Field
+    v588 = mul v586, v587
+    v589 = add v584, v588
+    store v589 at v533
+    v590 = load v534 -> Field
+    v591 = array_get v530, index u32 27 -> u8
+    v592 = cast v591 as Field
+    v593 = mul v592, v587
+    v594 = add v590, v593
+    store v594 at v534
+    v595 = mul v587, Field 256
+    store v595 at v531
+    v596 = load v533 -> Field
+    v597 = array_get v530, index u32 10 -> u8
+    v598 = cast v597 as Field
+    v599 = load v531 -> Field
+    v600 = mul v598, v599
+    v601 = add v596, v600
+    store v601 at v533
+    v602 = load v534 -> Field
+    v603 = array_get v530, index u32 26 -> u8
+    v604 = cast v603 as Field
+    v605 = mul v604, v599
+    v606 = add v602, v605
+    store v606 at v534
+    v607 = mul v599, Field 256
+    store v607 at v531
+    v608 = load v533 -> Field
+    v609 = array_get v530, index u32 9 -> u8
+    v610 = cast v609 as Field
+    v611 = load v531 -> Field
+    v612 = mul v610, v611
+    v613 = add v608, v612
+    store v613 at v533
+    v614 = load v534 -> Field
+    v615 = array_get v530, index u32 25 -> u8
+    v616 = cast v615 as Field
+    v617 = mul v616, v611
+    v618 = add v614, v617
+    store v618 at v534
+    v619 = mul v611, Field 256
+    store v619 at v531
+    v620 = load v533 -> Field
+    v621 = array_get v530, index u32 8 -> u8
+    v622 = cast v621 as Field
+    v623 = load v531 -> Field
+    v624 = mul v622, v623
+    v625 = add v620, v624
+    store v625 at v533
+    v626 = load v534 -> Field
+    v627 = array_get v530, index u32 24 -> u8
+    v628 = cast v627 as Field
+    v629 = mul v628, v623
+    v630 = add v626, v629
+    store v630 at v534
+    v631 = mul v623, Field 256
+    store v631 at v531
+    v632 = load v533 -> Field
+    v633 = array_get v530, index u32 7 -> u8
+    v634 = cast v633 as Field
+    v635 = load v531 -> Field
+    v636 = mul v634, v635
+    v637 = add v632, v636
+    store v637 at v533
+    v638 = load v534 -> Field
+    v639 = array_get v530, index u32 23 -> u8
+    v640 = cast v639 as Field
+    v641 = mul v640, v635
+    v642 = add v638, v641
+    store v642 at v534
+    v643 = mul v635, Field 256
+    store v643 at v531
+    v644 = load v533 -> Field
+    v645 = array_get v530, index u32 6 -> u8
+    v646 = cast v645 as Field
+    v647 = load v531 -> Field
+    v648 = mul v646, v647
+    v649 = add v644, v648
+    store v649 at v533
+    v650 = load v534 -> Field
+    v651 = array_get v530, index u32 22 -> u8
+    v652 = cast v651 as Field
+    v653 = mul v652, v647
+    v654 = add v650, v653
+    store v654 at v534
+    v655 = mul v647, Field 256
+    store v655 at v531
+    v656 = load v533 -> Field
+    v657 = array_get v530, index u32 5 -> u8
+    v658 = cast v657 as Field
+    v659 = load v531 -> Field
+    v660 = mul v658, v659
+    v661 = add v656, v660
+    store v661 at v533
+    v662 = load v534 -> Field
+    v663 = array_get v530, index u32 21 -> u8
+    v664 = cast v663 as Field
+    v665 = mul v664, v659
+    v666 = add v662, v665
+    store v666 at v534
+    v667 = mul v659, Field 256
+    store v667 at v531
+    v668 = load v533 -> Field
+    v669 = array_get v530, index u32 4 -> u8
+    v670 = cast v669 as Field
+    v671 = load v531 -> Field
+    v672 = mul v670, v671
+    v673 = add v668, v672
+    store v673 at v533
+    v674 = load v534 -> Field
+    v675 = array_get v530, index u32 20 -> u8
+    v676 = cast v675 as Field
+    v677 = mul v676, v671
+    v678 = add v674, v677
+    store v678 at v534
+    v679 = mul v671, Field 256
+    store v679 at v531
+    v680 = load v533 -> Field
+    v681 = array_get v530, index u32 3 -> u8
+    v682 = cast v681 as Field
+    v683 = load v531 -> Field
+    v684 = mul v682, v683
+    v685 = add v680, v684
+    store v685 at v533
+    v686 = load v534 -> Field
+    v687 = array_get v530, index u32 19 -> u8
+    v688 = cast v687 as Field
+    v689 = mul v688, v683
+    v690 = add v686, v689
+    store v690 at v534
+    v691 = mul v683, Field 256
+    store v691 at v531
+    v692 = load v533 -> Field
+    v693 = array_get v530, index u32 2 -> u8
+    v694 = cast v693 as Field
+    v695 = load v531 -> Field
+    v696 = mul v694, v695
+    v697 = add v692, v696
+    store v697 at v533
+    v698 = load v534 -> Field
+    v699 = array_get v530, index u32 18 -> u8
+    v700 = cast v699 as Field
+    v701 = mul v700, v695
+    v702 = add v698, v701
+    store v702 at v534
+    v703 = mul v695, Field 256
+    store v703 at v531
+    v704 = load v533 -> Field
+    v705 = array_get v530, index u32 1 -> u8
+    v706 = cast v705 as Field
+    v707 = load v531 -> Field
+    v708 = mul v706, v707
+    v709 = add v704, v708
+    store v709 at v533
+    v710 = load v534 -> Field
+    v711 = array_get v530, index u32 17 -> u8
+    v712 = cast v711 as Field
+    v713 = mul v712, v707
+    v714 = add v710, v713
+    store v714 at v534
+    v715 = mul v707, Field 256
+    store v715 at v531
+    v716 = load v533 -> Field
+    v717 = array_get v530, index u32 0 -> u8
+    v718 = cast v717 as Field
+    v719 = load v531 -> Field
+    v720 = mul v718, v719
+    v721 = add v716, v720
+    store v721 at v533
+    v722 = load v534 -> Field
+    v723 = array_get v530, index u32 16 -> u8
+    v724 = cast v723 as Field
+    v725 = mul v724, v719
+    v726 = add v722, v725
+    store v726 at v534
+    v727 = mul v719, Field 256
+    store v727 at v531
+    v728 = load v534 -> Field
+    v729 = load v533 -> Field
+    v730 = load v531 -> Field
+    v731 = mul v729, v730
+    v732 = add v728, v731
+    store v732 at v8
+    v733 = allocate -> &mut Field
+    store Field 0 at v733
+    v734 = eq v4, Field 0
+    jmpif v734 then: b197, else: b193
+  b193():
+    v736 = call f1(v4, Field 0) -> u1
+    jmpif v736 then: b195, else: b194
+  b194():
+    v738, v739 = call f3(v4) -> (Field, Field)
+    range_check v738 to 128 bits
+    range_check v739 to 128 bits
+    v741 = mul Field 340282366920938463463374607431768211456, v739
+    v742 = add v738, v741
+    v743 = eq v4, v742
+    constrain v4 == v742
+    v746 = call f2(Field 53438638232309528389504892708671455233, v738) -> u1
+    v747 = sub Field 53438638232309528389504892708671455233, v738
+    v748 = sub v747, Field 1
+    v749 = cast v746 as Field
+    v750 = mul v749, Field 340282366920938463463374607431768211456
+    v751 = add v748, v750
+    v753 = sub Field 64323764613183177041862057485226039389, v739
+    v754 = cast v746 as Field
+    v755 = sub v753, v754
+    range_check v751 to 128 bits
+    range_check v755 to 128 bits
+    v757, v758 = call f3(Field 0) -> (Field, Field)
+    range_check v757 to 128 bits
+    range_check v758 to 128 bits
+    v759 = mul Field 340282366920938463463374607431768211456, v758
+    v760 = add v757, v759
+    v761 = eq Field 0, v760
+    constrain Field 0 == v760
+    v763 = call f2(Field 53438638232309528389504892708671455233, v757) -> u1
+    v764 = sub Field 53438638232309528389504892708671455233, v757
+    v765 = sub v764, Field 1
+    v766 = cast v763 as Field
+    v767 = mul v766, Field 340282366920938463463374607431768211456
+    v768 = add v765, v767
+    v769 = sub Field 64323764613183177041862057485226039389, v758
+    v770 = cast v763 as Field
+    v771 = sub v769, v770
+    range_check v768 to 128 bits
+    range_check v771 to 128 bits
+    v773 = call f2(v738, v757) -> u1
+    v774 = sub v738, v757
+    v775 = sub v774, Field 1
+    v776 = cast v773 as Field
+    v777 = mul v776, Field 340282366920938463463374607431768211456
+    v778 = add v775, v777
+    v779 = sub v739, v758
+    v780 = cast v773 as Field
+    v781 = sub v779, v780
+    range_check v778 to 128 bits
+    range_check v781 to 128 bits
+    jmp b196(u1 1)
+  b195():
+    v783, v784 = call f3(Field 0) -> (Field, Field)
+    range_check v783 to 128 bits
+    range_check v784 to 128 bits
+    v785 = mul Field 340282366920938463463374607431768211456, v784
+    v786 = add v783, v785
+    v787 = eq Field 0, v786
+    constrain Field 0 == v786
+    v789 = call f2(Field 53438638232309528389504892708671455233, v783) -> u1
+    v790 = sub Field 53438638232309528389504892708671455233, v783
+    v791 = sub v790, Field 1
+    v792 = cast v789 as Field
+    v793 = mul v792, Field 340282366920938463463374607431768211456
+    v794 = add v791, v793
+    v795 = sub Field 64323764613183177041862057485226039389, v784
+    v796 = cast v789 as Field
+    v797 = sub v795, v796
+    range_check v794 to 128 bits
+    range_check v797 to 128 bits
+    v799, v800 = call f3(v4) -> (Field, Field)
+    range_check v799 to 128 bits
+    range_check v800 to 128 bits
+    v801 = mul Field 340282366920938463463374607431768211456, v800
+    v802 = add v799, v801
+    v803 = eq v4, v802
+    constrain v4 == v802
+    v805 = call f2(Field 53438638232309528389504892708671455233, v799) -> u1
+    v806 = sub Field 53438638232309528389504892708671455233, v799
+    v807 = sub v806, Field 1
+    v808 = cast v805 as Field
+    v809 = mul v808, Field 340282366920938463463374607431768211456
+    v810 = add v807, v809
+    v811 = sub Field 64323764613183177041862057485226039389, v800
+    v812 = cast v805 as Field
+    v813 = sub v811, v812
+    range_check v810 to 128 bits
+    range_check v813 to 128 bits
+    v815 = call f2(v783, v799) -> u1
+    v816 = sub v783, v799
+    v817 = sub v816, Field 1
+    v818 = cast v815 as Field
+    v819 = mul v818, Field 340282366920938463463374607431768211456
+    v820 = add v817, v819
+    v821 = sub v784, v800
+    v822 = cast v815 as Field
+    v823 = sub v821, v822
+    range_check v820 to 128 bits
+    range_check v823 to 128 bits
+    jmp b196(u1 0)
+  b196(v5: u1):
+    jmp b198(v5)
+  b197():
+    jmp b198(u1 0)
+  b198(v6: u1):
+    jmpif v6 then: b199, else: b200
+  b199():
+    store Field 1 at v733
+    jmp b200()
+  b200():
+    v824 = load v733 -> Field
+    v825 = load v8 -> Field
+    v826 = sub v824, v825
+    return v826
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Mem2Reg (2nd):
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v7 = allocate -> &mut Field
+    v8 = allocate -> &mut Field
+    v11 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v41 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v42 = allocate -> &mut u1
+    store u1 0 at v42
+    jmpif u1 1 then: b1, else: b4
+  b1():
+    v46 = array_get v11, index u32 0 -> u8
+    v47 = eq v46, u8 48
+    v48 = not v47
+    jmpif v48 then: b2, else: b3
+  b2():
+    v49 = array_get v11, index u32 0 -> u8
+    v50 = lt v49, u8 48
+    constrain v50 == u1 1
+    store u1 1 at v42
+    jmp b3()
+  b3():
+    jmp b4()
+  b4():
+    v51 = load v42 -> u1
+    v52 = not v51
+    jmpif v52 then: b5, else: b8
+  b5():
+    v54 = array_get v11, index u32 1 -> u8
+    v55 = eq v54, u8 100
+    v56 = not v55
+    jmpif v56 then: b6, else: b7
+  b6():
+    v57 = array_get v11, index u32 1 -> u8
+    v58 = lt v57, u8 100
+    constrain v58 == u1 1
+    store u1 1 at v42
+    jmp b7()
+  b7():
+    jmp b8()
+  b8():
+    v59 = load v42 -> u1
+    v60 = not v59
+    jmpif v60 then: b9, else: b12
+  b9():
+    v62 = array_get v11, index u32 2 -> u8
+    v63 = eq v62, u8 78
+    v64 = not v63
+    jmpif v64 then: b10, else: b11
+  b10():
+    v65 = array_get v11, index u32 2 -> u8
+    v66 = lt v65, u8 78
+    constrain v66 == u1 1
+    store u1 1 at v42
+    jmp b11()
+  b11():
+    jmp b12()
+  b12():
+    v67 = load v42 -> u1
+    v68 = not v67
+    jmpif v68 then: b13, else: b16
+  b13():
+    v70 = array_get v11, index u32 3 -> u8
+    v71 = eq v70, u8 114
+    v72 = not v71
+    jmpif v72 then: b14, else: b15
+  b14():
+    v73 = array_get v11, index u32 3 -> u8
+    v74 = lt v73, u8 114
+    constrain v74 == u1 1
+    store u1 1 at v42
+    jmp b15()
+  b15():
+    jmp b16()
+  b16():
+    v75 = load v42 -> u1
+    v76 = not v75
+    jmpif v76 then: b17, else: b20
+  b17():
+    v78 = array_get v11, index u32 4 -> u8
+    v79 = eq v78, u8 225
+    v80 = not v79
+    jmpif v80 then: b18, else: b19
+  b18():
+    v81 = array_get v11, index u32 4 -> u8
+    v82 = lt v81, u8 225
+    constrain v82 == u1 1
+    store u1 1 at v42
+    jmp b19()
+  b19():
+    jmp b20()
+  b20():
+    v83 = load v42 -> u1
+    v84 = not v83
+    jmpif v84 then: b21, else: b24
+  b21():
+    v86 = array_get v11, index u32 5 -> u8
+    v87 = eq v86, u8 49
+    v88 = not v87
+    jmpif v88 then: b22, else: b23
+  b22():
+    v89 = array_get v11, index u32 5 -> u8
+    v90 = lt v89, u8 49
+    constrain v90 == u1 1
+    store u1 1 at v42
+    jmp b23()
+  b23():
+    jmp b24()
+  b24():
+    v91 = load v42 -> u1
+    v92 = not v91
+    jmpif v92 then: b25, else: b28
+  b25():
+    v94 = array_get v11, index u32 6 -> u8
+    v95 = eq v94, u8 160
+    v96 = not v95
+    jmpif v96 then: b26, else: b27
+  b26():
+    v97 = array_get v11, index u32 6 -> u8
+    v98 = lt v97, u8 160
+    constrain v98 == u1 1
+    store u1 1 at v42
+    jmp b27()
+  b27():
+    jmp b28()
+  b28():
+    v99 = load v42 -> u1
+    v100 = not v99
+    jmpif v100 then: b29, else: b32
+  b29():
+    v102 = array_get v11, index u32 7 -> u8
+    v103 = eq v102, u8 41
+    v104 = not v103
+    jmpif v104 then: b30, else: b31
+  b30():
+    v105 = array_get v11, index u32 7 -> u8
+    v106 = lt v105, u8 41
+    constrain v106 == u1 1
+    store u1 1 at v42
+    jmp b31()
+  b31():
+    jmp b32()
+  b32():
+    v107 = load v42 -> u1
+    v108 = not v107
+    jmpif v108 then: b33, else: b36
+  b33():
+    v110 = array_get v11, index u32 8 -> u8
+    v111 = eq v110, u8 184
+    v112 = not v111
+    jmpif v112 then: b34, else: b35
+  b34():
+    v113 = array_get v11, index u32 8 -> u8
+    v114 = lt v113, u8 184
+    constrain v114 == u1 1
+    store u1 1 at v42
+    jmp b35()
+  b35():
+    jmp b36()
+  b36():
+    v115 = load v42 -> u1
+    v116 = not v115
+    jmpif v116 then: b37, else: b40
+  b37():
+    v118 = array_get v11, index u32 9 -> u8
+    v119 = eq v118, u8 80
+    v120 = not v119
+    jmpif v120 then: b38, else: b39
+  b38():
+    v121 = array_get v11, index u32 9 -> u8
+    v122 = lt v121, u8 80
+    constrain v122 == u1 1
+    store u1 1 at v42
+    jmp b39()
+  b39():
+    jmp b40()
+  b40():
+    v123 = load v42 -> u1
+    v124 = not v123
+    jmpif v124 then: b41, else: b44
+  b41():
+    v126 = array_get v11, index u32 10 -> u8
+    v127 = eq v126, u8 69
+    v128 = not v127
+    jmpif v128 then: b42, else: b43
+  b42():
+    v129 = array_get v11, index u32 10 -> u8
+    v130 = lt v129, u8 69
+    constrain v130 == u1 1
+    store u1 1 at v42
+    jmp b43()
+  b43():
+    jmp b44()
+  b44():
+    v131 = load v42 -> u1
+    v132 = not v131
+    jmpif v132 then: b45, else: b48
+  b45():
+    v134 = array_get v11, index u32 11 -> u8
+    v135 = eq v134, u8 182
+    v136 = not v135
+    jmpif v136 then: b46, else: b47
+  b46():
+    v137 = array_get v11, index u32 11 -> u8
+    v138 = lt v137, u8 182
+    constrain v138 == u1 1
+    store u1 1 at v42
+    jmp b47()
+  b47():
+    jmp b48()
+  b48():
+    v139 = load v42 -> u1
+    v140 = not v139
+    jmpif v140 then: b49, else: b52
+  b49():
+    v142 = array_get v11, index u32 12 -> u8
+    v143 = eq v142, u8 129
+    v144 = not v143
+    jmpif v144 then: b50, else: b51
+  b50():
+    v145 = array_get v11, index u32 12 -> u8
+    v146 = lt v145, u8 129
+    constrain v146 == u1 1
+    store u1 1 at v42
+    jmp b51()
+  b51():
+    jmp b52()
+  b52():
+    v147 = load v42 -> u1
+    v148 = not v147
+    jmpif v148 then: b53, else: b56
+  b53():
+    v150 = array_get v11, index u32 13 -> u8
+    v151 = eq v150, u8 129
+    v152 = not v151
+    jmpif v152 then: b54, else: b55
+  b54():
+    v153 = array_get v11, index u32 13 -> u8
+    v154 = lt v153, u8 129
+    constrain v154 == u1 1
+    store u1 1 at v42
+    jmp b55()
+  b55():
+    jmp b56()
+  b56():
+    v155 = load v42 -> u1
+    v156 = not v155
+    jmpif v156 then: b57, else: b60
+  b57():
+    v158 = array_get v11, index u32 14 -> u8
+    v159 = eq v158, u8 88
+    v160 = not v159
+    jmpif v160 then: b58, else: b59
+  b58():
+    v161 = array_get v11, index u32 14 -> u8
+    v162 = lt v161, u8 88
+    constrain v162 == u1 1
+    store u1 1 at v42
+    jmp b59()
+  b59():
+    jmp b60()
+  b60():
+    v163 = load v42 -> u1
+    v164 = not v163
+    jmpif v164 then: b61, else: b64
+  b61():
+    v166 = array_get v11, index u32 15 -> u8
+    v167 = eq v166, u8 93
+    v168 = not v167
+    jmpif v168 then: b62, else: b63
+  b62():
+    v169 = array_get v11, index u32 15 -> u8
+    v170 = lt v169, u8 93
+    constrain v170 == u1 1
+    store u1 1 at v42
+    jmp b63()
+  b63():
+    jmp b64()
+  b64():
+    v171 = load v42 -> u1
+    v172 = not v171
+    jmpif v172 then: b65, else: b68
+  b65():
+    v174 = array_get v11, index u32 16 -> u8
+    v175 = eq v174, u8 40
+    v176 = not v175
+    jmpif v176 then: b66, else: b67
+  b66():
+    v177 = array_get v11, index u32 16 -> u8
+    v178 = lt v177, u8 40
+    constrain v178 == u1 1
+    store u1 1 at v42
+    jmp b67()
+  b67():
+    jmp b68()
+  b68():
+    v179 = load v42 -> u1
+    v180 = not v179
+    jmpif v180 then: b69, else: b72
+  b69():
+    v182 = array_get v11, index u32 17 -> u8
+    v183 = eq v182, u8 51
+    v184 = not v183
+    jmpif v184 then: b70, else: b71
+  b70():
+    v185 = array_get v11, index u32 17 -> u8
+    v186 = lt v185, u8 51
+    constrain v186 == u1 1
+    store u1 1 at v42
+    jmp b71()
+  b71():
+    jmp b72()
+  b72():
+    v187 = load v42 -> u1
+    v188 = not v187
+    jmpif v188 then: b73, else: b76
+  b73():
+    v190 = array_get v11, index u32 18 -> u8
+    v191 = eq v190, u8 232
+    v192 = not v191
+    jmpif v192 then: b74, else: b75
+  b74():
+    v193 = array_get v11, index u32 18 -> u8
+    v194 = lt v193, u8 232
+    constrain v194 == u1 1
+    store u1 1 at v42
+    jmp b75()
+  b75():
+    jmp b76()
+  b76():
+    v195 = load v42 -> u1
+    v196 = not v195
+    jmpif v196 then: b77, else: b80
+  b77():
+    v198 = array_get v11, index u32 19 -> u8
+    v199 = eq v198, u8 72
+    v200 = not v199
+    jmpif v200 then: b78, else: b79
+  b78():
+    v201 = array_get v11, index u32 19 -> u8
+    v202 = lt v201, u8 72
+    constrain v202 == u1 1
+    store u1 1 at v42
+    jmp b79()
+  b79():
+    jmp b80()
+  b80():
+    v203 = load v42 -> u1
+    v204 = not v203
+    jmpif v204 then: b81, else: b84
+  b81():
+    v206 = array_get v11, index u32 20 -> u8
+    v207 = eq v206, u8 121
+    v208 = not v207
+    jmpif v208 then: b82, else: b83
+  b82():
+    v209 = array_get v11, index u32 20 -> u8
+    v210 = lt v209, u8 121
+    constrain v210 == u1 1
+    store u1 1 at v42
+    jmp b83()
+  b83():
+    jmp b84()
+  b84():
+    v211 = load v42 -> u1
+    v212 = not v211
+    jmpif v212 then: b85, else: b88
+  b85():
+    v214 = array_get v11, index u32 21 -> u8
+    v215 = eq v214, u8 185
+    v216 = not v215
+    jmpif v216 then: b86, else: b87
+  b86():
+    v217 = array_get v11, index u32 21 -> u8
+    v218 = lt v217, u8 185
+    constrain v218 == u1 1
+    store u1 1 at v42
+    jmp b87()
+  b87():
+    jmp b88()
+  b88():
+    v219 = load v42 -> u1
+    v220 = not v219
+    jmpif v220 then: b89, else: b92
+  b89():
+    v222 = array_get v11, index u32 22 -> u8
+    v223 = eq v222, u8 112
+    v224 = not v223
+    jmpif v224 then: b90, else: b91
+  b90():
+    v225 = array_get v11, index u32 22 -> u8
+    v226 = lt v225, u8 112
+    constrain v226 == u1 1
+    store u1 1 at v42
+    jmp b91()
+  b91():
+    jmp b92()
+  b92():
+    v227 = load v42 -> u1
+    v228 = not v227
+    jmpif v228 then: b93, else: b96
+  b93():
+    v230 = array_get v11, index u32 23 -> u8
+    v231 = eq v230, u8 145
+    v232 = not v231
+    jmpif v232 then: b94, else: b95
+  b94():
+    v233 = array_get v11, index u32 23 -> u8
+    v234 = lt v233, u8 145
+    constrain v234 == u1 1
+    store u1 1 at v42
+    jmp b95()
+  b95():
+    jmp b96()
+  b96():
+    v235 = load v42 -> u1
+    v236 = not v235
+    jmpif v236 then: b97, else: b100
+  b97():
+    v238 = array_get v11, index u32 24 -> u8
+    v239 = eq v238, u8 67
+    v240 = not v239
+    jmpif v240 then: b98, else: b99
+  b98():
+    v241 = array_get v11, index u32 24 -> u8
+    v242 = lt v241, u8 67
+    constrain v242 == u1 1
+    store u1 1 at v42
+    jmp b99()
+  b99():
+    jmp b100()
+  b100():
+    v243 = load v42 -> u1
+    v244 = not v243
+    jmpif v244 then: b101, else: b104
+  b101():
+    v246 = array_get v11, index u32 25 -> u8
+    v247 = eq v246, u8 225
+    v248 = not v247
+    jmpif v248 then: b102, else: b103
+  b102():
+    v249 = array_get v11, index u32 25 -> u8
+    v250 = lt v249, u8 225
+    constrain v250 == u1 1
+    store u1 1 at v42
+    jmp b103()
+  b103():
+    jmp b104()
+  b104():
+    v251 = load v42 -> u1
+    v252 = not v251
+    jmpif v252 then: b105, else: b108
+  b105():
+    v254 = array_get v11, index u32 26 -> u8
+    v255 = eq v254, u8 245
+    v256 = not v255
+    jmpif v256 then: b106, else: b107
+  b106():
+    v257 = array_get v11, index u32 26 -> u8
+    v258 = lt v257, u8 245
+    constrain v258 == u1 1
+    store u1 1 at v42
+    jmp b107()
+  b107():
+    jmp b108()
+  b108():
+    v259 = load v42 -> u1
+    v260 = not v259
+    jmpif v260 then: b109, else: b112
+  b109():
+    v262 = array_get v11, index u32 27 -> u8
+    v263 = eq v262, u8 147
+    v264 = not v263
+    jmpif v264 then: b110, else: b111
+  b110():
+    v265 = array_get v11, index u32 27 -> u8
+    v266 = lt v265, u8 147
+    constrain v266 == u1 1
+    store u1 1 at v42
+    jmp b111()
+  b111():
+    jmp b112()
+  b112():
+    v267 = load v42 -> u1
+    v268 = not v267
+    jmpif v268 then: b113, else: b116
+  b113():
+    v270 = array_get v11, index u32 28 -> u8
+    v271 = eq v270, u8 240
+    v272 = not v271
+    jmpif v272 then: b114, else: b115
+  b114():
+    v273 = array_get v11, index u32 28 -> u8
+    v274 = lt v273, u8 240
+    constrain v274 == u1 1
+    store u1 1 at v42
+    jmp b115()
+  b115():
+    jmp b116()
+  b116():
+    v275 = load v42 -> u1
+    v276 = not v275
+    jmpif v276 then: b117, else: b120
+  b117():
+    v278 = array_get v11, index u32 29 -> u8
+    v279 = eq v278, u8 0
+    v280 = not v279
+    jmpif v280 then: b118, else: b119
+  b118():
+    v281 = array_get v11, index u32 29 -> u8
+    constrain u1 0 == u1 1
+    store u1 1 at v42
+    jmp b119()
+  b119():
+    jmp b120()
+  b120():
+    v282 = load v42 -> u1
+    v283 = not v282
+    jmpif v283 then: b121, else: b124
+  b121():
+    v285 = array_get v11, index u32 30 -> u8
+    v286 = eq v285, u8 0
+    v287 = not v286
+    jmpif v287 then: b122, else: b123
+  b122():
+    v288 = array_get v11, index u32 30 -> u8
+    constrain u1 0 == u1 1
+    store u1 1 at v42
+    jmp b123()
+  b123():
+    jmp b124()
+  b124():
+    v289 = load v42 -> u1
+    v290 = not v289
+    jmpif v290 then: b125, else: b128
+  b125():
+    v292 = array_get v11, index u32 31 -> u8
+    v293 = eq v292, u8 1
+    v294 = not v293
+    jmpif v294 then: b126, else: b127
+  b126():
+    v295 = array_get v11, index u32 31 -> u8
+    v296 = eq v295, u8 0
+    constrain v295 == u8 0
+    store u1 1 at v42
+    jmp b127()
+  b127():
+    jmp b128()
+  b128():
+    v297 = load v42 -> u1
+    constrain v297 == u1 1
+    v298 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v299 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v300 = allocate -> &mut u1
+    store u1 0 at v300
+    jmpif u1 1 then: b129, else: b130
+  b129():
+    store u1 1 at v300
+    jmp b130()
+  b130():
+    v301 = load v300 -> u1
+    v302 = not v301
+    jmpif v302 then: b131, else: b132
+  b131():
+    store u1 1 at v300
+    jmp b132()
+  b132():
+    v303 = load v300 -> u1
+    v304 = not v303
+    jmpif v304 then: b133, else: b134
+  b133():
+    store u1 1 at v300
+    jmp b134()
+  b134():
+    v305 = load v300 -> u1
+    v306 = not v305
+    jmpif v306 then: b135, else: b136
+  b135():
+    store u1 1 at v300
+    jmp b136()
+  b136():
+    v307 = load v300 -> u1
+    v308 = not v307
+    jmpif v308 then: b137, else: b138
+  b137():
+    store u1 1 at v300
+    jmp b138()
+  b138():
+    v309 = load v300 -> u1
+    v310 = not v309
+    jmpif v310 then: b139, else: b140
+  b139():
+    store u1 1 at v300
+    jmp b140()
+  b140():
+    v311 = load v300 -> u1
+    v312 = not v311
+    jmpif v312 then: b141, else: b142
+  b141():
+    store u1 1 at v300
+    jmp b142()
+  b142():
+    v313 = load v300 -> u1
+    v314 = not v313
+    jmpif v314 then: b143, else: b144
+  b143():
+    store u1 1 at v300
+    jmp b144()
+  b144():
+    v315 = load v300 -> u1
+    v316 = not v315
+    jmpif v316 then: b145, else: b146
+  b145():
+    store u1 1 at v300
+    jmp b146()
+  b146():
+    v317 = load v300 -> u1
+    v318 = not v317
+    jmpif v318 then: b147, else: b148
+  b147():
+    store u1 1 at v300
+    jmp b148()
+  b148():
+    v319 = load v300 -> u1
+    v320 = not v319
+    jmpif v320 then: b149, else: b150
+  b149():
+    store u1 1 at v300
+    jmp b150()
+  b150():
+    v321 = load v300 -> u1
+    v322 = not v321
+    jmpif v322 then: b151, else: b152
+  b151():
+    store u1 1 at v300
+    jmp b152()
+  b152():
+    v323 = load v300 -> u1
+    v324 = not v323
+    jmpif v324 then: b153, else: b154
+  b153():
+    store u1 1 at v300
+    jmp b154()
+  b154():
+    v325 = load v300 -> u1
+    v326 = not v325
+    jmpif v326 then: b155, else: b156
+  b155():
+    store u1 1 at v300
+    jmp b156()
+  b156():
+    v327 = load v300 -> u1
+    v328 = not v327
+    jmpif v328 then: b157, else: b158
+  b157():
+    store u1 1 at v300
+    jmp b158()
+  b158():
+    v329 = load v300 -> u1
+    v330 = not v329
+    jmpif v330 then: b159, else: b160
+  b159():
+    store u1 1 at v300
+    jmp b160()
+  b160():
+    v331 = load v300 -> u1
+    v332 = not v331
+    jmpif v332 then: b161, else: b162
+  b161():
+    store u1 1 at v300
+    jmp b162()
+  b162():
+    v333 = load v300 -> u1
+    v334 = not v333
+    jmpif v334 then: b163, else: b164
+  b163():
+    store u1 1 at v300
+    jmp b164()
+  b164():
+    v335 = load v300 -> u1
+    v336 = not v335
+    jmpif v336 then: b165, else: b166
+  b165():
+    store u1 1 at v300
+    jmp b166()
+  b166():
+    v337 = load v300 -> u1
+    v338 = not v337
+    jmpif v338 then: b167, else: b168
+  b167():
+    store u1 1 at v300
+    jmp b168()
+  b168():
+    v339 = load v300 -> u1
+    v340 = not v339
+    jmpif v340 then: b169, else: b170
+  b169():
+    store u1 1 at v300
+    jmp b170()
+  b170():
+    v341 = load v300 -> u1
+    v342 = not v341
+    jmpif v342 then: b171, else: b172
+  b171():
+    store u1 1 at v300
+    jmp b172()
+  b172():
+    v343 = load v300 -> u1
+    v344 = not v343
+    jmpif v344 then: b173, else: b174
+  b173():
+    store u1 1 at v300
+    jmp b174()
+  b174():
+    v345 = load v300 -> u1
+    v346 = not v345
+    jmpif v346 then: b175, else: b176
+  b175():
+    store u1 1 at v300
+    jmp b176()
+  b176():
+    v347 = load v300 -> u1
+    v348 = not v347
+    jmpif v348 then: b177, else: b178
+  b177():
+    store u1 1 at v300
+    jmp b178()
+  b178():
+    v349 = load v300 -> u1
+    v350 = not v349
+    jmpif v350 then: b179, else: b180
+  b179():
+    store u1 1 at v300
+    jmp b180()
+  b180():
+    v351 = load v300 -> u1
+    v352 = not v351
+    jmpif v352 then: b181, else: b182
+  b181():
+    store u1 1 at v300
+    jmp b182()
+  b182():
+    v353 = load v300 -> u1
+    v354 = not v353
+    jmpif v354 then: b183, else: b184
+  b183():
+    store u1 1 at v300
+    jmp b184()
+  b184():
+    v355 = load v300 -> u1
+    v356 = not v355
+    jmpif v356 then: b185, else: b186
+  b185():
+    store u1 1 at v300
+    jmp b186()
+  b186():
+    v357 = load v300 -> u1
+    v358 = not v357
+    jmpif v358 then: b187, else: b188
+  b187():
+    jmp b188()
+  b188():
+    v359 = load v300 -> u1
+    v360 = not v359
+    jmpif v360 then: b189, else: b190
+  b189():
+    jmp b190()
+  b190():
+    v361 = load v300 -> u1
+    v362 = not v361
+    jmpif v362 then: b191, else: b192
+  b191():
+    store u1 1 at v300
+    jmp b192()
+  b192():
+    v363 = load v300 -> u1
+    constrain v363 == u1 1
+    v364 = allocate -> &mut [u8; 32]
+    v365 = array_get v11, index u32 0 -> u8
+    v366 = make_array [v365, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v367 = array_get v11, index u32 1 -> u8
+    v368 = make_array [v365, v367, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v369 = array_get v11, index u32 2 -> u8
+    v370 = make_array [v365, v367, v369, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v371 = array_get v11, index u32 3 -> u8
+    v372 = make_array [v365, v367, v369, v371, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v373 = array_get v11, index u32 4 -> u8
+    v374 = make_array [v365, v367, v369, v371, v373, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v375 = array_get v11, index u32 5 -> u8
+    v376 = make_array [v365, v367, v369, v371, v373, v375, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v377 = array_get v11, index u32 6 -> u8
+    v378 = make_array [v365, v367, v369, v371, v373, v375, v377, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v379 = array_get v11, index u32 7 -> u8
+    v380 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v381 = array_get v11, index u32 8 -> u8
+    v382 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v383 = array_get v11, index u32 9 -> u8
+    v384 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v385 = array_get v11, index u32 10 -> u8
+    v386 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v387 = array_get v11, index u32 11 -> u8
+    v388 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v389 = array_get v11, index u32 12 -> u8
+    v390 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v391 = array_get v11, index u32 13 -> u8
+    v392 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v393 = array_get v11, index u32 14 -> u8
+    v394 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v395 = array_get v11, index u32 15 -> u8
+    v396 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v397 = array_get v11, index u32 16 -> u8
+    v398 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v399 = array_get v11, index u32 17 -> u8
+    v400 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v401 = array_get v11, index u32 18 -> u8
+    v402 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v403 = array_get v11, index u32 19 -> u8
+    v404 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v405 = array_get v11, index u32 20 -> u8
+    v406 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v407 = array_get v11, index u32 21 -> u8
+    v408 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v409 = array_get v11, index u32 22 -> u8
+    v410 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v411 = array_get v11, index u32 23 -> u8
+    v412 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v413 = array_get v11, index u32 24 -> u8
+    v414 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v415 = array_get v11, index u32 25 -> u8
+    v416 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v417 = array_get v11, index u32 26 -> u8
+    v418 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, v417, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v419 = array_get v11, index u32 27 -> u8
+    v420 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, v417, v419, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v421 = array_get v11, index u32 28 -> u8
+    v422 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, v417, v419, v421, u8 0, u8 0, u8 0] : [u8; 32]
+    v423 = array_get v11, index u32 29 -> u8
+    v424 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, v417, v419, v421, v423, u8 0, u8 0] : [u8; 32]
+    v425 = array_get v11, index u32 30 -> u8
+    v426 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, v417, v419, v421, v423, v425, u8 0] : [u8; 32]
+    v427 = array_get v11, index u32 31 -> u8
+    v428 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, v417, v419, v421, v423, v425, v427] : [u8; 32]
+    v429 = allocate -> &mut Field
+    v430 = allocate -> &mut Field
+    v431 = allocate -> &mut Field
+    v432 = cast v395 as Field
+    v433 = cast v427 as Field
+    v434 = cast v393 as Field
+    v436 = mul v434, Field 256
+    v437 = add v432, v436
+    v438 = cast v425 as Field
+    v439 = mul v438, Field 256
+    v440 = add v433, v439
+    v441 = cast v391 as Field
+    v443 = mul v441, Field 65536
+    v444 = add v437, v443
+    v445 = cast v423 as Field
+    v446 = mul v445, Field 65536
+    v447 = add v440, v446
+    v448 = cast v389 as Field
+    v450 = mul v448, Field 16777216
+    v451 = add v444, v450
+    v452 = cast v421 as Field
+    v453 = mul v452, Field 16777216
+    v454 = add v447, v453
+    v455 = cast v387 as Field
+    v457 = mul v455, Field 4294967296
+    v458 = add v451, v457
+    v459 = cast v419 as Field
+    v460 = mul v459, Field 4294967296
+    v461 = add v454, v460
+    v462 = cast v385 as Field
+    v464 = mul v462, Field 1099511627776
+    v465 = add v458, v464
+    v466 = cast v417 as Field
+    v467 = mul v466, Field 1099511627776
+    v468 = add v461, v467
+    v469 = cast v383 as Field
+    v471 = mul v469, Field 281474976710656
+    v472 = add v465, v471
+    v473 = cast v415 as Field
+    v474 = mul v473, Field 281474976710656
+    v475 = add v468, v474
+    v476 = cast v381 as Field
+    v478 = mul v476, Field 72057594037927936
+    v479 = add v472, v478
+    v480 = cast v413 as Field
+    v481 = mul v480, Field 72057594037927936
+    v482 = add v475, v481
+    v483 = cast v379 as Field
+    v485 = mul v483, Field 18446744073709551616
+    v486 = add v479, v485
+    v487 = cast v411 as Field
+    v488 = mul v487, Field 18446744073709551616
+    v489 = add v482, v488
+    v490 = cast v377 as Field
+    v492 = mul v490, Field 4722366482869645213696
+    v493 = add v486, v492
+    v494 = cast v409 as Field
+    v495 = mul v494, Field 4722366482869645213696
+    v496 = add v489, v495
+    v497 = cast v375 as Field
+    v499 = mul v497, Field 1208925819614629174706176
+    v500 = add v493, v499
+    v501 = cast v407 as Field
+    v502 = mul v501, Field 1208925819614629174706176
+    v503 = add v496, v502
+    v504 = cast v373 as Field
+    v506 = mul v504, Field 309485009821345068724781056
+    v507 = add v500, v506
+    v508 = cast v405 as Field
+    v509 = mul v508, Field 309485009821345068724781056
+    v510 = add v503, v509
+    v511 = cast v371 as Field
+    v513 = mul v511, Field 79228162514264337593543950336
+    v514 = add v507, v513
+    v515 = cast v403 as Field
+    v516 = mul v515, Field 79228162514264337593543950336
+    v517 = add v510, v516
+    v518 = cast v369 as Field
+    v520 = mul v518, Field 20282409603651670423947251286016
+    v521 = add v514, v520
+    v522 = cast v401 as Field
+    v523 = mul v522, Field 20282409603651670423947251286016
+    v524 = add v517, v523
+    v525 = cast v367 as Field
+    v527 = mul v525, Field 5192296858534827628530496329220096
+    v528 = add v521, v527
+    v529 = cast v399 as Field
+    v530 = mul v529, Field 5192296858534827628530496329220096
+    v531 = add v524, v530
+    v532 = cast v365 as Field
+    v534 = mul v532, Field 1329227995784915872903807060280344576
+    v535 = add v528, v534
+    v536 = cast v397 as Field
+    v537 = mul v536, Field 1329227995784915872903807060280344576
+    v538 = add v531, v537
+    v540 = mul v535, Field 340282366920938463463374607431768211456
+    v541 = add v538, v540
+    v542 = allocate -> &mut Field
+    store Field 0 at v542
+    v544 = eq v4, Field 0
+    jmpif v544 then: b197, else: b193
+  b193():
+    v546 = call f1(v4, Field 0) -> u1
+    jmpif v546 then: b195, else: b194
+  b194():
+    v548, v549 = call f3(v4) -> (Field, Field)
+    range_check v548 to 128 bits
+    range_check v549 to 128 bits
+    v550 = mul Field 340282366920938463463374607431768211456, v549
+    v551 = add v548, v550
+    v552 = eq v4, v551
+    constrain v4 == v551
+    v555 = call f2(Field 53438638232309528389504892708671455233, v548) -> u1
+    v556 = sub Field 53438638232309528389504892708671455233, v548
+    v558 = sub v556, Field 1
+    v559 = cast v555 as Field
+    v560 = mul v559, Field 340282366920938463463374607431768211456
+    v561 = add v558, v560
+    v563 = sub Field 64323764613183177041862057485226039389, v549
+    v564 = cast v555 as Field
+    v565 = sub v563, v564
+    range_check v561 to 128 bits
+    range_check v565 to 128 bits
+    v567, v568 = call f3(Field 0) -> (Field, Field)
+    range_check v567 to 128 bits
+    range_check v568 to 128 bits
+    v569 = mul Field 340282366920938463463374607431768211456, v568
+    v570 = add v567, v569
+    v571 = eq Field 0, v570
+    constrain Field 0 == v570
+    v573 = call f2(Field 53438638232309528389504892708671455233, v567) -> u1
+    v574 = sub Field 53438638232309528389504892708671455233, v567
+    v575 = sub v574, Field 1
+    v576 = cast v573 as Field
+    v577 = mul v576, Field 340282366920938463463374607431768211456
+    v578 = add v575, v577
+    v579 = sub Field 64323764613183177041862057485226039389, v568
+    v580 = cast v573 as Field
+    v581 = sub v579, v580
+    range_check v578 to 128 bits
+    range_check v581 to 128 bits
+    v583 = call f2(v548, v567) -> u1
+    v584 = sub v548, v567
+    v585 = sub v584, Field 1
+    v586 = cast v583 as Field
+    v587 = mul v586, Field 340282366920938463463374607431768211456
+    v588 = add v585, v587
+    v589 = sub v549, v568
+    v590 = cast v583 as Field
+    v591 = sub v589, v590
+    range_check v588 to 128 bits
+    range_check v591 to 128 bits
+    jmp b196(u1 1)
+  b195():
+    v593, v594 = call f3(Field 0) -> (Field, Field)
+    range_check v593 to 128 bits
+    range_check v594 to 128 bits
+    v595 = mul Field 340282366920938463463374607431768211456, v594
+    v596 = add v593, v595
+    v597 = eq Field 0, v596
+    constrain Field 0 == v596
+    v599 = call f2(Field 53438638232309528389504892708671455233, v593) -> u1
+    v600 = sub Field 53438638232309528389504892708671455233, v593
+    v601 = sub v600, Field 1
+    v602 = cast v599 as Field
+    v603 = mul v602, Field 340282366920938463463374607431768211456
+    v604 = add v601, v603
+    v605 = sub Field 64323764613183177041862057485226039389, v594
+    v606 = cast v599 as Field
+    v607 = sub v605, v606
+    range_check v604 to 128 bits
+    range_check v607 to 128 bits
+    v609, v610 = call f3(v4) -> (Field, Field)
+    range_check v609 to 128 bits
+    range_check v610 to 128 bits
+    v611 = mul Field 340282366920938463463374607431768211456, v610
+    v612 = add v609, v611
+    v613 = eq v4, v612
+    constrain v4 == v612
+    v615 = call f2(Field 53438638232309528389504892708671455233, v609) -> u1
+    v616 = sub Field 53438638232309528389504892708671455233, v609
+    v617 = sub v616, Field 1
+    v618 = cast v615 as Field
+    v619 = mul v618, Field 340282366920938463463374607431768211456
+    v620 = add v617, v619
+    v621 = sub Field 64323764613183177041862057485226039389, v610
+    v622 = cast v615 as Field
+    v623 = sub v621, v622
+    range_check v620 to 128 bits
+    range_check v623 to 128 bits
+    v625 = call f2(v593, v609) -> u1
+    v626 = sub v593, v609
+    v627 = sub v626, Field 1
+    v628 = cast v625 as Field
+    v629 = mul v628, Field 340282366920938463463374607431768211456
+    v630 = add v627, v629
+    v631 = sub v594, v610
+    v632 = cast v625 as Field
+    v633 = sub v631, v632
+    range_check v630 to 128 bits
+    range_check v633 to 128 bits
+    jmp b196(u1 0)
+  b196(v5: u1):
+    jmp b198(v5)
+  b197():
+    jmp b198(u1 0)
+  b198(v6: u1):
+    jmpif v6 then: b199, else: b200
+  b199():
+    store Field 1 at v542
+    jmp b200()
+  b200():
+    v634 = load v542 -> Field
+    v635 = sub v634, v541
+    return v635
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Flattening:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = allocate -> &mut Field
+    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v40 = allocate -> &mut u1
+    store u1 0 at v40
+    enable_side_effects u1 1
+    v44 = array_get v9, index u32 0 -> u8
+    v45 = eq v44, u8 48
+    v46 = not v45
+    v47 = unchecked_mul u1 1, v46
+    enable_side_effects v47
+    v48 = array_get v9, index u32 0 -> u8
+    v49 = lt v48, u8 48
+    v50 = mul v49, v47
+    constrain v50 == v47
+    v51 = load v40 -> u1
+    v52 = not v47
+    v53 = mul v52, v51
+    v54 = unchecked_add v47, v53
+    store v54 at v40
+    v55 = unchecked_mul u1 1, v45
+    enable_side_effects u1 1
+    v56 = load v40 -> u1
+    v57 = not v56
+    enable_side_effects v57
+    v59 = array_get v9, index u32 1 -> u8
+    v60 = eq v59, u8 100
+    v61 = not v60
+    v62 = unchecked_mul v57, v61
+    enable_side_effects v62
+    v63 = array_get v9, index u32 1 -> u8
+    v64 = lt v63, u8 100
+    v65 = mul v64, v62
+    constrain v65 == v62
+    v66 = load v40 -> u1
+    v67 = not v62
+    v68 = mul v67, v66
+    v69 = unchecked_add v62, v68
+    store v69 at v40
+    v70 = unchecked_mul v57, v60
+    enable_side_effects u1 1
+    v71 = load v40 -> u1
+    v72 = not v71
+    enable_side_effects v72
+    v74 = array_get v9, index u32 2 -> u8
+    v75 = eq v74, u8 78
+    v76 = not v75
+    v77 = unchecked_mul v72, v76
+    enable_side_effects v77
+    v78 = array_get v9, index u32 2 -> u8
+    v79 = lt v78, u8 78
+    v80 = mul v79, v77
+    constrain v80 == v77
+    v81 = load v40 -> u1
+    v82 = not v77
+    v83 = mul v82, v81
+    v84 = unchecked_add v77, v83
+    store v84 at v40
+    v85 = unchecked_mul v72, v75
+    enable_side_effects u1 1
+    v86 = load v40 -> u1
+    v87 = not v86
+    enable_side_effects v87
+    v89 = array_get v9, index u32 3 -> u8
+    v90 = eq v89, u8 114
+    v91 = not v90
+    v92 = unchecked_mul v87, v91
+    enable_side_effects v92
+    v93 = array_get v9, index u32 3 -> u8
+    v94 = lt v93, u8 114
+    v95 = mul v94, v92
+    constrain v95 == v92
+    v96 = load v40 -> u1
+    v97 = not v92
+    v98 = mul v97, v96
+    v99 = unchecked_add v92, v98
+    store v99 at v40
+    v100 = unchecked_mul v87, v90
+    enable_side_effects u1 1
+    v101 = load v40 -> u1
+    v102 = not v101
+    enable_side_effects v102
+    v104 = array_get v9, index u32 4 -> u8
+    v105 = eq v104, u8 225
+    v106 = not v105
+    v107 = unchecked_mul v102, v106
+    enable_side_effects v107
+    v108 = array_get v9, index u32 4 -> u8
+    v109 = lt v108, u8 225
+    v110 = mul v109, v107
+    constrain v110 == v107
+    v111 = load v40 -> u1
+    v112 = not v107
+    v113 = mul v112, v111
+    v114 = unchecked_add v107, v113
+    store v114 at v40
+    v115 = unchecked_mul v102, v105
+    enable_side_effects u1 1
+    v116 = load v40 -> u1
+    v117 = not v116
+    enable_side_effects v117
+    v119 = array_get v9, index u32 5 -> u8
+    v120 = eq v119, u8 49
+    v121 = not v120
+    v122 = unchecked_mul v117, v121
+    enable_side_effects v122
+    v123 = array_get v9, index u32 5 -> u8
+    v124 = lt v123, u8 49
+    v125 = mul v124, v122
+    constrain v125 == v122
+    v126 = load v40 -> u1
+    v127 = not v122
+    v128 = mul v127, v126
+    v129 = unchecked_add v122, v128
+    store v129 at v40
+    v130 = unchecked_mul v117, v120
+    enable_side_effects u1 1
+    v131 = load v40 -> u1
+    v132 = not v131
+    enable_side_effects v132
+    v134 = array_get v9, index u32 6 -> u8
+    v135 = eq v134, u8 160
+    v136 = not v135
+    v137 = unchecked_mul v132, v136
+    enable_side_effects v137
+    v138 = array_get v9, index u32 6 -> u8
+    v139 = lt v138, u8 160
+    v140 = mul v139, v137
+    constrain v140 == v137
+    v141 = load v40 -> u1
+    v142 = not v137
+    v143 = mul v142, v141
+    v144 = unchecked_add v137, v143
+    store v144 at v40
+    v145 = unchecked_mul v132, v135
+    enable_side_effects u1 1
+    v146 = load v40 -> u1
+    v147 = not v146
+    enable_side_effects v147
+    v149 = array_get v9, index u32 7 -> u8
+    v150 = eq v149, u8 41
+    v151 = not v150
+    v152 = unchecked_mul v147, v151
+    enable_side_effects v152
+    v153 = array_get v9, index u32 7 -> u8
+    v154 = lt v153, u8 41
+    v155 = mul v154, v152
+    constrain v155 == v152
+    v156 = load v40 -> u1
+    v157 = not v152
+    v158 = mul v157, v156
+    v159 = unchecked_add v152, v158
+    store v159 at v40
+    v160 = unchecked_mul v147, v150
+    enable_side_effects u1 1
+    v161 = load v40 -> u1
+    v162 = not v161
+    enable_side_effects v162
+    v164 = array_get v9, index u32 8 -> u8
+    v165 = eq v164, u8 184
+    v166 = not v165
+    v167 = unchecked_mul v162, v166
+    enable_side_effects v167
+    v168 = array_get v9, index u32 8 -> u8
+    v169 = lt v168, u8 184
+    v170 = mul v169, v167
+    constrain v170 == v167
+    v171 = load v40 -> u1
+    v172 = not v167
+    v173 = mul v172, v171
+    v174 = unchecked_add v167, v173
+    store v174 at v40
+    v175 = unchecked_mul v162, v165
+    enable_side_effects u1 1
+    v176 = load v40 -> u1
+    v177 = not v176
+    enable_side_effects v177
+    v179 = array_get v9, index u32 9 -> u8
+    v180 = eq v179, u8 80
+    v181 = not v180
+    v182 = unchecked_mul v177, v181
+    enable_side_effects v182
+    v183 = array_get v9, index u32 9 -> u8
+    v184 = lt v183, u8 80
+    v185 = mul v184, v182
+    constrain v185 == v182
+    v186 = load v40 -> u1
+    v187 = not v182
+    v188 = mul v187, v186
+    v189 = unchecked_add v182, v188
+    store v189 at v40
+    v190 = unchecked_mul v177, v180
+    enable_side_effects u1 1
+    v191 = load v40 -> u1
+    v192 = not v191
+    enable_side_effects v192
+    v194 = array_get v9, index u32 10 -> u8
+    v195 = eq v194, u8 69
+    v196 = not v195
+    v197 = unchecked_mul v192, v196
+    enable_side_effects v197
+    v198 = array_get v9, index u32 10 -> u8
+    v199 = lt v198, u8 69
+    v200 = mul v199, v197
+    constrain v200 == v197
+    v201 = load v40 -> u1
+    v202 = not v197
+    v203 = mul v202, v201
+    v204 = unchecked_add v197, v203
+    store v204 at v40
+    v205 = unchecked_mul v192, v195
+    enable_side_effects u1 1
+    v206 = load v40 -> u1
+    v207 = not v206
+    enable_side_effects v207
+    v209 = array_get v9, index u32 11 -> u8
+    v210 = eq v209, u8 182
+    v211 = not v210
+    v212 = unchecked_mul v207, v211
+    enable_side_effects v212
+    v213 = array_get v9, index u32 11 -> u8
+    v214 = lt v213, u8 182
+    v215 = mul v214, v212
+    constrain v215 == v212
+    v216 = load v40 -> u1
+    v217 = not v212
+    v218 = mul v217, v216
+    v219 = unchecked_add v212, v218
+    store v219 at v40
+    v220 = unchecked_mul v207, v210
+    enable_side_effects u1 1
+    v221 = load v40 -> u1
+    v222 = not v221
+    enable_side_effects v222
+    v224 = array_get v9, index u32 12 -> u8
+    v225 = eq v224, u8 129
+    v226 = not v225
+    v227 = unchecked_mul v222, v226
+    enable_side_effects v227
+    v228 = array_get v9, index u32 12 -> u8
+    v229 = lt v228, u8 129
+    v230 = mul v229, v227
+    constrain v230 == v227
+    v231 = load v40 -> u1
+    v232 = not v227
+    v233 = mul v232, v231
+    v234 = unchecked_add v227, v233
+    store v234 at v40
+    v235 = unchecked_mul v222, v225
+    enable_side_effects u1 1
+    v236 = load v40 -> u1
+    v237 = not v236
+    enable_side_effects v237
+    v239 = array_get v9, index u32 13 -> u8
+    v240 = eq v239, u8 129
+    v241 = not v240
+    v242 = unchecked_mul v237, v241
+    enable_side_effects v242
+    v243 = array_get v9, index u32 13 -> u8
+    v244 = lt v243, u8 129
+    v245 = mul v244, v242
+    constrain v245 == v242
+    v246 = load v40 -> u1
+    v247 = not v242
+    v248 = mul v247, v246
+    v249 = unchecked_add v242, v248
+    store v249 at v40
+    v250 = unchecked_mul v237, v240
+    enable_side_effects u1 1
+    v251 = load v40 -> u1
+    v252 = not v251
+    enable_side_effects v252
+    v254 = array_get v9, index u32 14 -> u8
+    v255 = eq v254, u8 88
+    v256 = not v255
+    v257 = unchecked_mul v252, v256
+    enable_side_effects v257
+    v258 = array_get v9, index u32 14 -> u8
+    v259 = lt v258, u8 88
+    v260 = mul v259, v257
+    constrain v260 == v257
+    v261 = load v40 -> u1
+    v262 = not v257
+    v263 = mul v262, v261
+    v264 = unchecked_add v257, v263
+    store v264 at v40
+    v265 = unchecked_mul v252, v255
+    enable_side_effects u1 1
+    v266 = load v40 -> u1
+    v267 = not v266
+    enable_side_effects v267
+    v269 = array_get v9, index u32 15 -> u8
+    v270 = eq v269, u8 93
+    v271 = not v270
+    v272 = unchecked_mul v267, v271
+    enable_side_effects v272
+    v273 = array_get v9, index u32 15 -> u8
+    v274 = lt v273, u8 93
+    v275 = mul v274, v272
+    constrain v275 == v272
+    v276 = load v40 -> u1
+    v277 = not v272
+    v278 = mul v277, v276
+    v279 = unchecked_add v272, v278
+    store v279 at v40
+    v280 = unchecked_mul v267, v270
+    enable_side_effects u1 1
+    v281 = load v40 -> u1
+    v282 = not v281
+    enable_side_effects v282
+    v284 = array_get v9, index u32 16 -> u8
+    v285 = eq v284, u8 40
+    v286 = not v285
+    v287 = unchecked_mul v282, v286
+    enable_side_effects v287
+    v288 = array_get v9, index u32 16 -> u8
+    v289 = lt v288, u8 40
+    v290 = mul v289, v287
+    constrain v290 == v287
+    v291 = load v40 -> u1
+    v292 = not v287
+    v293 = mul v292, v291
+    v294 = unchecked_add v287, v293
+    store v294 at v40
+    v295 = unchecked_mul v282, v285
+    enable_side_effects u1 1
+    v296 = load v40 -> u1
+    v297 = not v296
+    enable_side_effects v297
+    v299 = array_get v9, index u32 17 -> u8
+    v300 = eq v299, u8 51
+    v301 = not v300
+    v302 = unchecked_mul v297, v301
+    enable_side_effects v302
+    v303 = array_get v9, index u32 17 -> u8
+    v304 = lt v303, u8 51
+    v305 = mul v304, v302
+    constrain v305 == v302
+    v306 = load v40 -> u1
+    v307 = not v302
+    v308 = mul v307, v306
+    v309 = unchecked_add v302, v308
+    store v309 at v40
+    v310 = unchecked_mul v297, v300
+    enable_side_effects u1 1
+    v311 = load v40 -> u1
+    v312 = not v311
+    enable_side_effects v312
+    v314 = array_get v9, index u32 18 -> u8
+    v315 = eq v314, u8 232
+    v316 = not v315
+    v317 = unchecked_mul v312, v316
+    enable_side_effects v317
+    v318 = array_get v9, index u32 18 -> u8
+    v319 = lt v318, u8 232
+    v320 = mul v319, v317
+    constrain v320 == v317
+    v321 = load v40 -> u1
+    v322 = not v317
+    v323 = mul v322, v321
+    v324 = unchecked_add v317, v323
+    store v324 at v40
+    v325 = unchecked_mul v312, v315
+    enable_side_effects u1 1
+    v326 = load v40 -> u1
+    v327 = not v326
+    enable_side_effects v327
+    v329 = array_get v9, index u32 19 -> u8
+    v330 = eq v329, u8 72
+    v331 = not v330
+    v332 = unchecked_mul v327, v331
+    enable_side_effects v332
+    v333 = array_get v9, index u32 19 -> u8
+    v334 = lt v333, u8 72
+    v335 = mul v334, v332
+    constrain v335 == v332
+    v336 = load v40 -> u1
+    v337 = not v332
+    v338 = mul v337, v336
+    v339 = unchecked_add v332, v338
+    store v339 at v40
+    v340 = unchecked_mul v327, v330
+    enable_side_effects u1 1
+    v341 = load v40 -> u1
+    v342 = not v341
+    enable_side_effects v342
+    v344 = array_get v9, index u32 20 -> u8
+    v345 = eq v344, u8 121
+    v346 = not v345
+    v347 = unchecked_mul v342, v346
+    enable_side_effects v347
+    v348 = array_get v9, index u32 20 -> u8
+    v349 = lt v348, u8 121
+    v350 = mul v349, v347
+    constrain v350 == v347
+    v351 = load v40 -> u1
+    v352 = not v347
+    v353 = mul v352, v351
+    v354 = unchecked_add v347, v353
+    store v354 at v40
+    v355 = unchecked_mul v342, v345
+    enable_side_effects u1 1
+    v356 = load v40 -> u1
+    v357 = not v356
+    enable_side_effects v357
+    v359 = array_get v9, index u32 21 -> u8
+    v360 = eq v359, u8 185
+    v361 = not v360
+    v362 = unchecked_mul v357, v361
+    enable_side_effects v362
+    v363 = array_get v9, index u32 21 -> u8
+    v364 = lt v363, u8 185
+    v365 = mul v364, v362
+    constrain v365 == v362
+    v366 = load v40 -> u1
+    v367 = not v362
+    v368 = mul v367, v366
+    v369 = unchecked_add v362, v368
+    store v369 at v40
+    v370 = unchecked_mul v357, v360
+    enable_side_effects u1 1
+    v371 = load v40 -> u1
+    v372 = not v371
+    enable_side_effects v372
+    v374 = array_get v9, index u32 22 -> u8
+    v375 = eq v374, u8 112
+    v376 = not v375
+    v377 = unchecked_mul v372, v376
+    enable_side_effects v377
+    v378 = array_get v9, index u32 22 -> u8
+    v379 = lt v378, u8 112
+    v380 = mul v379, v377
+    constrain v380 == v377
+    v381 = load v40 -> u1
+    v382 = not v377
+    v383 = mul v382, v381
+    v384 = unchecked_add v377, v383
+    store v384 at v40
+    v385 = unchecked_mul v372, v375
+    enable_side_effects u1 1
+    v386 = load v40 -> u1
+    v387 = not v386
+    enable_side_effects v387
+    v389 = array_get v9, index u32 23 -> u8
+    v390 = eq v389, u8 145
+    v391 = not v390
+    v392 = unchecked_mul v387, v391
+    enable_side_effects v392
+    v393 = array_get v9, index u32 23 -> u8
+    v394 = lt v393, u8 145
+    v395 = mul v394, v392
+    constrain v395 == v392
+    v396 = load v40 -> u1
+    v397 = not v392
+    v398 = mul v397, v396
+    v399 = unchecked_add v392, v398
+    store v399 at v40
+    v400 = unchecked_mul v387, v390
+    enable_side_effects u1 1
+    v401 = load v40 -> u1
+    v402 = not v401
+    enable_side_effects v402
+    v404 = array_get v9, index u32 24 -> u8
+    v405 = eq v404, u8 67
+    v406 = not v405
+    v407 = unchecked_mul v402, v406
+    enable_side_effects v407
+    v408 = array_get v9, index u32 24 -> u8
+    v409 = lt v408, u8 67
+    v410 = mul v409, v407
+    constrain v410 == v407
+    v411 = load v40 -> u1
+    v412 = not v407
+    v413 = mul v412, v411
+    v414 = unchecked_add v407, v413
+    store v414 at v40
+    v415 = unchecked_mul v402, v405
+    enable_side_effects u1 1
+    v416 = load v40 -> u1
+    v417 = not v416
+    enable_side_effects v417
+    v419 = array_get v9, index u32 25 -> u8
+    v420 = eq v419, u8 225
+    v421 = not v420
+    v422 = unchecked_mul v417, v421
+    enable_side_effects v422
+    v423 = array_get v9, index u32 25 -> u8
+    v424 = lt v423, u8 225
+    v425 = mul v424, v422
+    constrain v425 == v422
+    v426 = load v40 -> u1
+    v427 = not v422
+    v428 = mul v427, v426
+    v429 = unchecked_add v422, v428
+    store v429 at v40
+    v430 = unchecked_mul v417, v420
+    enable_side_effects u1 1
+    v431 = load v40 -> u1
+    v432 = not v431
+    enable_side_effects v432
+    v434 = array_get v9, index u32 26 -> u8
+    v435 = eq v434, u8 245
+    v436 = not v435
+    v437 = unchecked_mul v432, v436
+    enable_side_effects v437
+    v438 = array_get v9, index u32 26 -> u8
+    v439 = lt v438, u8 245
+    v440 = mul v439, v437
+    constrain v440 == v437
+    v441 = load v40 -> u1
+    v442 = not v437
+    v443 = mul v442, v441
+    v444 = unchecked_add v437, v443
+    store v444 at v40
+    v445 = unchecked_mul v432, v435
+    enable_side_effects u1 1
+    v446 = load v40 -> u1
+    v447 = not v446
+    enable_side_effects v447
+    v449 = array_get v9, index u32 27 -> u8
+    v450 = eq v449, u8 147
+    v451 = not v450
+    v452 = unchecked_mul v447, v451
+    enable_side_effects v452
+    v453 = array_get v9, index u32 27 -> u8
+    v454 = lt v453, u8 147
+    v455 = mul v454, v452
+    constrain v455 == v452
+    v456 = load v40 -> u1
+    v457 = not v452
+    v458 = mul v457, v456
+    v459 = unchecked_add v452, v458
+    store v459 at v40
+    v460 = unchecked_mul v447, v450
+    enable_side_effects u1 1
+    v461 = load v40 -> u1
+    v462 = not v461
+    enable_side_effects v462
+    v464 = array_get v9, index u32 28 -> u8
+    v465 = eq v464, u8 240
+    v466 = not v465
+    v467 = unchecked_mul v462, v466
+    enable_side_effects v467
+    v468 = array_get v9, index u32 28 -> u8
+    v469 = lt v468, u8 240
+    v470 = mul v469, v467
+    constrain v470 == v467
+    v471 = load v40 -> u1
+    v472 = not v467
+    v473 = mul v472, v471
+    v474 = unchecked_add v467, v473
+    store v474 at v40
+    v475 = unchecked_mul v462, v465
+    enable_side_effects u1 1
+    v476 = load v40 -> u1
+    v477 = not v476
+    enable_side_effects v477
+    v479 = array_get v9, index u32 29 -> u8
+    v480 = eq v479, u8 0
+    v481 = not v480
+    v482 = unchecked_mul v477, v481
+    enable_side_effects v482
+    v483 = array_get v9, index u32 29 -> u8
+    constrain u1 0 == v482
+    v484 = load v40 -> u1
+    v485 = not v482
+    v486 = mul v485, v484
+    v487 = unchecked_add v482, v486
+    store v487 at v40
+    v488 = unchecked_mul v477, v480
+    enable_side_effects u1 1
+    v489 = load v40 -> u1
+    v490 = not v489
+    enable_side_effects v490
+    v492 = array_get v9, index u32 30 -> u8
+    v493 = eq v492, u8 0
+    v494 = not v493
+    v495 = unchecked_mul v490, v494
+    enable_side_effects v495
+    v496 = array_get v9, index u32 30 -> u8
+    constrain u1 0 == v495
+    v497 = load v40 -> u1
+    v498 = not v495
+    v499 = mul v498, v497
+    v500 = unchecked_add v495, v499
+    store v500 at v40
+    v501 = unchecked_mul v490, v493
+    enable_side_effects u1 1
+    v502 = load v40 -> u1
+    v503 = not v502
+    enable_side_effects v503
+    v505 = array_get v9, index u32 31 -> u8
+    v506 = eq v505, u8 1
+    v507 = not v506
+    v508 = unchecked_mul v503, v507
+    enable_side_effects v508
+    v509 = array_get v9, index u32 31 -> u8
+    v510 = eq v509, u8 0
+    v511 = cast v508 as u8
+    v512 = unchecked_mul v509, v511
+    constrain v512 == u8 0
+    v513 = load v40 -> u1
+    v514 = not v508
+    v515 = mul v514, v513
+    v516 = unchecked_add v508, v515
+    store v516 at v40
+    v517 = unchecked_mul v503, v506
+    enable_side_effects u1 1
+    v518 = load v40 -> u1
+    constrain v518 == u1 1
+    v519 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v520 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v521 = allocate -> &mut u1
+    store u1 0 at v521
+    enable_side_effects u1 1
+    v522 = load v521 -> u1
+    store u1 1 at v521
+    enable_side_effects u1 1
+    v523 = load v521 -> u1
+    v524 = not v523
+    enable_side_effects v524
+    v525 = load v521 -> u1
+    v526 = mul v523, v525
+    v527 = unchecked_add v524, v526
+    store v527 at v521
+    enable_side_effects u1 1
+    v528 = load v521 -> u1
+    v529 = not v528
+    enable_side_effects v529
+    v530 = load v521 -> u1
+    v531 = mul v528, v530
+    v532 = unchecked_add v529, v531
+    store v532 at v521
+    enable_side_effects u1 1
+    v533 = load v521 -> u1
+    v534 = not v533
+    enable_side_effects v534
+    v535 = load v521 -> u1
+    v536 = mul v533, v535
+    v537 = unchecked_add v534, v536
+    store v537 at v521
+    enable_side_effects u1 1
+    v538 = load v521 -> u1
+    v539 = not v538
+    enable_side_effects v539
+    v540 = load v521 -> u1
+    v541 = mul v538, v540
+    v542 = unchecked_add v539, v541
+    store v542 at v521
+    enable_side_effects u1 1
+    v543 = load v521 -> u1
+    v544 = not v543
+    enable_side_effects v544
+    v545 = load v521 -> u1
+    v546 = mul v543, v545
+    v547 = unchecked_add v544, v546
+    store v547 at v521
+    enable_side_effects u1 1
+    v548 = load v521 -> u1
+    v549 = not v548
+    enable_side_effects v549
+    v550 = load v521 -> u1
+    v551 = mul v548, v550
+    v552 = unchecked_add v549, v551
+    store v552 at v521
+    enable_side_effects u1 1
+    v553 = load v521 -> u1
+    v554 = not v553
+    enable_side_effects v554
+    v555 = load v521 -> u1
+    v556 = mul v553, v555
+    v557 = unchecked_add v554, v556
+    store v557 at v521
+    enable_side_effects u1 1
+    v558 = load v521 -> u1
+    v559 = not v558
+    enable_side_effects v559
+    v560 = load v521 -> u1
+    v561 = mul v558, v560
+    v562 = unchecked_add v559, v561
+    store v562 at v521
+    enable_side_effects u1 1
+    v563 = load v521 -> u1
+    v564 = not v563
+    enable_side_effects v564
+    v565 = load v521 -> u1
+    v566 = mul v563, v565
+    v567 = unchecked_add v564, v566
+    store v567 at v521
+    enable_side_effects u1 1
+    v568 = load v521 -> u1
+    v569 = not v568
+    enable_side_effects v569
+    v570 = load v521 -> u1
+    v571 = mul v568, v570
+    v572 = unchecked_add v569, v571
+    store v572 at v521
+    enable_side_effects u1 1
+    v573 = load v521 -> u1
+    v574 = not v573
+    enable_side_effects v574
+    v575 = load v521 -> u1
+    v576 = mul v573, v575
+    v577 = unchecked_add v574, v576
+    store v577 at v521
+    enable_side_effects u1 1
+    v578 = load v521 -> u1
+    v579 = not v578
+    enable_side_effects v579
+    v580 = load v521 -> u1
+    v581 = mul v578, v580
+    v582 = unchecked_add v579, v581
+    store v582 at v521
+    enable_side_effects u1 1
+    v583 = load v521 -> u1
+    v584 = not v583
+    enable_side_effects v584
+    v585 = load v521 -> u1
+    v586 = mul v583, v585
+    v587 = unchecked_add v584, v586
+    store v587 at v521
+    enable_side_effects u1 1
+    v588 = load v521 -> u1
+    v589 = not v588
+    enable_side_effects v589
+    v590 = load v521 -> u1
+    v591 = mul v588, v590
+    v592 = unchecked_add v589, v591
+    store v592 at v521
+    enable_side_effects u1 1
+    v593 = load v521 -> u1
+    v594 = not v593
+    enable_side_effects v594
+    v595 = load v521 -> u1
+    v596 = mul v593, v595
+    v597 = unchecked_add v594, v596
+    store v597 at v521
+    enable_side_effects u1 1
+    v598 = load v521 -> u1
+    v599 = not v598
+    enable_side_effects v599
+    v600 = load v521 -> u1
+    v601 = mul v598, v600
+    v602 = unchecked_add v599, v601
+    store v602 at v521
+    enable_side_effects u1 1
+    v603 = load v521 -> u1
+    v604 = not v603
+    enable_side_effects v604
+    v605 = load v521 -> u1
+    v606 = mul v603, v605
+    v607 = unchecked_add v604, v606
+    store v607 at v521
+    enable_side_effects u1 1
+    v608 = load v521 -> u1
+    v609 = not v608
+    enable_side_effects v609
+    v610 = load v521 -> u1
+    v611 = mul v608, v610
+    v612 = unchecked_add v609, v611
+    store v612 at v521
+    enable_side_effects u1 1
+    v613 = load v521 -> u1
+    v614 = not v613
+    enable_side_effects v614
+    v615 = load v521 -> u1
+    v616 = mul v613, v615
+    v617 = unchecked_add v614, v616
+    store v617 at v521
+    enable_side_effects u1 1
+    v618 = load v521 -> u1
+    v619 = not v618
+    enable_side_effects v619
+    v620 = load v521 -> u1
+    v621 = mul v618, v620
+    v622 = unchecked_add v619, v621
+    store v622 at v521
+    enable_side_effects u1 1
+    v623 = load v521 -> u1
+    v624 = not v623
+    enable_side_effects v624
+    v625 = load v521 -> u1
+    v626 = mul v623, v625
+    v627 = unchecked_add v624, v626
+    store v627 at v521
+    enable_side_effects u1 1
+    v628 = load v521 -> u1
+    v629 = not v628
+    enable_side_effects v629
+    v630 = load v521 -> u1
+    v631 = mul v628, v630
+    v632 = unchecked_add v629, v631
+    store v632 at v521
+    enable_side_effects u1 1
+    v633 = load v521 -> u1
+    v634 = not v633
+    enable_side_effects v634
+    v635 = load v521 -> u1
+    v636 = mul v633, v635
+    v637 = unchecked_add v634, v636
+    store v637 at v521
+    enable_side_effects u1 1
+    v638 = load v521 -> u1
+    v639 = not v638
+    enable_side_effects v639
+    v640 = load v521 -> u1
+    v641 = mul v638, v640
+    v642 = unchecked_add v639, v641
+    store v642 at v521
+    enable_side_effects u1 1
+    v643 = load v521 -> u1
+    v644 = not v643
+    enable_side_effects v644
+    v645 = load v521 -> u1
+    v646 = mul v643, v645
+    v647 = unchecked_add v644, v646
+    store v647 at v521
+    enable_side_effects u1 1
+    v648 = load v521 -> u1
+    v649 = not v648
+    enable_side_effects v649
+    v650 = load v521 -> u1
+    v651 = mul v648, v650
+    v652 = unchecked_add v649, v651
+    store v652 at v521
+    enable_side_effects u1 1
+    v653 = load v521 -> u1
+    v654 = not v653
+    enable_side_effects v654
+    v655 = load v521 -> u1
+    v656 = mul v653, v655
+    v657 = unchecked_add v654, v656
+    store v657 at v521
+    enable_side_effects u1 1
+    v658 = load v521 -> u1
+    v659 = not v658
+    enable_side_effects v659
+    v660 = load v521 -> u1
+    v661 = mul v658, v660
+    v662 = unchecked_add v659, v661
+    store v662 at v521
+    enable_side_effects u1 1
+    v663 = load v521 -> u1
+    v664 = not v663
+    enable_side_effects u1 1
+    v665 = load v521 -> u1
+    v666 = not v665
+    enable_side_effects u1 1
+    v667 = load v521 -> u1
+    v668 = not v667
+    enable_side_effects v668
+    v669 = load v521 -> u1
+    v670 = mul v667, v669
+    v671 = unchecked_add v668, v670
+    store v671 at v521
+    enable_side_effects u1 1
+    v672 = load v521 -> u1
+    constrain v672 == u1 1
+    v673 = allocate -> &mut [u8; 32]
+    v674 = array_get v9, index u32 0 -> u8
+    v675 = make_array [v674, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v676 = array_get v9, index u32 1 -> u8
+    v677 = make_array [v674, v676, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v678 = array_get v9, index u32 2 -> u8
+    v679 = make_array [v674, v676, v678, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v680 = array_get v9, index u32 3 -> u8
+    v681 = make_array [v674, v676, v678, v680, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v682 = array_get v9, index u32 4 -> u8
+    v683 = make_array [v674, v676, v678, v680, v682, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v684 = array_get v9, index u32 5 -> u8
+    v685 = make_array [v674, v676, v678, v680, v682, v684, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v686 = array_get v9, index u32 6 -> u8
+    v687 = make_array [v674, v676, v678, v680, v682, v684, v686, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v688 = array_get v9, index u32 7 -> u8
+    v689 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v690 = array_get v9, index u32 8 -> u8
+    v691 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v692 = array_get v9, index u32 9 -> u8
+    v693 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v694 = array_get v9, index u32 10 -> u8
+    v695 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v696 = array_get v9, index u32 11 -> u8
+    v697 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v698 = array_get v9, index u32 12 -> u8
+    v699 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v700 = array_get v9, index u32 13 -> u8
+    v701 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v702 = array_get v9, index u32 14 -> u8
+    v703 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v704 = array_get v9, index u32 15 -> u8
+    v705 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v706 = array_get v9, index u32 16 -> u8
+    v707 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v708 = array_get v9, index u32 17 -> u8
+    v709 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v710 = array_get v9, index u32 18 -> u8
+    v711 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v712 = array_get v9, index u32 19 -> u8
+    v713 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v714 = array_get v9, index u32 20 -> u8
+    v715 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v716 = array_get v9, index u32 21 -> u8
+    v717 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v718 = array_get v9, index u32 22 -> u8
+    v719 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v720 = array_get v9, index u32 23 -> u8
+    v721 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v722 = array_get v9, index u32 24 -> u8
+    v723 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v724 = array_get v9, index u32 25 -> u8
+    v725 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v726 = array_get v9, index u32 26 -> u8
+    v727 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v728 = array_get v9, index u32 27 -> u8
+    v729 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v730 = array_get v9, index u32 28 -> u8
+    v731 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, u8 0, u8 0, u8 0] : [u8; 32]
+    v732 = array_get v9, index u32 29 -> u8
+    v733 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, v732, u8 0, u8 0] : [u8; 32]
+    v734 = array_get v9, index u32 30 -> u8
+    v735 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, v732, v734, u8 0] : [u8; 32]
+    v736 = array_get v9, index u32 31 -> u8
+    v737 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, v732, v734, v736] : [u8; 32]
+    v738 = allocate -> &mut Field
+    v739 = allocate -> &mut Field
+    v740 = allocate -> &mut Field
+    v741 = cast v704 as Field
+    v742 = cast v736 as Field
+    v743 = cast v702 as Field
+    v745 = mul v743, Field 256
+    v746 = add v741, v745
+    v747 = cast v734 as Field
+    v748 = mul v747, Field 256
+    v749 = add v742, v748
+    v750 = cast v700 as Field
+    v752 = mul v750, Field 65536
+    v753 = add v746, v752
+    v754 = cast v732 as Field
+    v755 = mul v754, Field 65536
+    v756 = add v749, v755
+    v757 = cast v698 as Field
+    v759 = mul v757, Field 16777216
+    v760 = add v753, v759
+    v761 = cast v730 as Field
+    v762 = mul v761, Field 16777216
+    v763 = add v756, v762
+    v764 = cast v696 as Field
+    v766 = mul v764, Field 4294967296
+    v767 = add v760, v766
+    v768 = cast v728 as Field
+    v769 = mul v768, Field 4294967296
+    v770 = add v763, v769
+    v771 = cast v694 as Field
+    v773 = mul v771, Field 1099511627776
+    v774 = add v767, v773
+    v775 = cast v726 as Field
+    v776 = mul v775, Field 1099511627776
+    v777 = add v770, v776
+    v778 = cast v692 as Field
+    v780 = mul v778, Field 281474976710656
+    v781 = add v774, v780
+    v782 = cast v724 as Field
+    v783 = mul v782, Field 281474976710656
+    v784 = add v777, v783
+    v785 = cast v690 as Field
+    v787 = mul v785, Field 72057594037927936
+    v788 = add v781, v787
+    v789 = cast v722 as Field
+    v790 = mul v789, Field 72057594037927936
+    v791 = add v784, v790
+    v792 = cast v688 as Field
+    v794 = mul v792, Field 18446744073709551616
+    v795 = add v788, v794
+    v796 = cast v720 as Field
+    v797 = mul v796, Field 18446744073709551616
+    v798 = add v791, v797
+    v799 = cast v686 as Field
+    v801 = mul v799, Field 4722366482869645213696
+    v802 = add v795, v801
+    v803 = cast v718 as Field
+    v804 = mul v803, Field 4722366482869645213696
+    v805 = add v798, v804
+    v806 = cast v684 as Field
+    v808 = mul v806, Field 1208925819614629174706176
+    v809 = add v802, v808
+    v810 = cast v716 as Field
+    v811 = mul v810, Field 1208925819614629174706176
+    v812 = add v805, v811
+    v813 = cast v682 as Field
+    v815 = mul v813, Field 309485009821345068724781056
+    v816 = add v809, v815
+    v817 = cast v714 as Field
+    v818 = mul v817, Field 309485009821345068724781056
+    v819 = add v812, v818
+    v820 = cast v680 as Field
+    v822 = mul v820, Field 79228162514264337593543950336
+    v823 = add v816, v822
+    v824 = cast v712 as Field
+    v825 = mul v824, Field 79228162514264337593543950336
+    v826 = add v819, v825
+    v827 = cast v678 as Field
+    v829 = mul v827, Field 20282409603651670423947251286016
+    v830 = add v823, v829
+    v831 = cast v710 as Field
+    v832 = mul v831, Field 20282409603651670423947251286016
+    v833 = add v826, v832
+    v834 = cast v676 as Field
+    v836 = mul v834, Field 5192296858534827628530496329220096
+    v837 = add v830, v836
+    v838 = cast v708 as Field
+    v839 = mul v838, Field 5192296858534827628530496329220096
+    v840 = add v833, v839
+    v841 = cast v674 as Field
+    v843 = mul v841, Field 1329227995784915872903807060280344576
+    v844 = add v837, v843
+    v845 = cast v706 as Field
+    v846 = mul v845, Field 1329227995784915872903807060280344576
+    v847 = add v840, v846
+    v849 = mul v844, Field 340282366920938463463374607431768211456
+    v850 = add v847, v849
+    v851 = allocate -> &mut Field
+    store Field 0 at v851
+    v853 = eq v4, Field 0
+    enable_side_effects v853
+    v854 = not v853
+    enable_side_effects v854
+    v856 = call f1(v4, Field 0) -> u1
+    v857 = unchecked_mul v854, v856
+    enable_side_effects v857
+    v859, v860 = call f3(Field 0) -> (Field, Field)
+    v861 = cast v857 as Field
+    v862 = mul v859, v861
+    range_check v862 to 128 bits
+    v863 = cast v857 as Field
+    v864 = mul v860, v863
+    range_check v864 to 128 bits
+    v865 = mul Field 340282366920938463463374607431768211456, v860
+    v866 = add v859, v865
+    v867 = eq Field 0, v866
+    v868 = cast v857 as Field
+    v869 = mul v866, v868
+    constrain Field 0 == v869
+    v872 = call f2(Field 53438638232309528389504892708671455233, v859) -> u1
+    v873 = sub Field 53438638232309528389504892708671455233, v859
+    v875 = sub v873, Field 1
+    v876 = cast v872 as Field
+    v877 = mul v876, Field 340282366920938463463374607431768211456
+    v878 = add v875, v877
+    v880 = sub Field 64323764613183177041862057485226039389, v860
+    v881 = cast v872 as Field
+    v882 = sub v880, v881
+    v883 = cast v857 as Field
+    v884 = mul v878, v883
+    range_check v884 to 128 bits
+    v885 = cast v857 as Field
+    v886 = mul v882, v885
+    range_check v886 to 128 bits
+    v888, v889 = call f3(v4) -> (Field, Field)
+    v890 = cast v857 as Field
+    v891 = mul v888, v890
+    range_check v891 to 128 bits
+    v892 = cast v857 as Field
+    v893 = mul v889, v892
+    range_check v893 to 128 bits
+    v894 = mul Field 340282366920938463463374607431768211456, v889
+    v895 = add v888, v894
+    v896 = eq v4, v895
+    v897 = cast v857 as Field
+    v898 = mul v4, v897
+    v899 = mul v895, v897
+    constrain v898 == v899
+    v901 = call f2(Field 53438638232309528389504892708671455233, v888) -> u1
+    v902 = sub Field 53438638232309528389504892708671455233, v888
+    v903 = sub v902, Field 1
+    v904 = cast v901 as Field
+    v905 = mul v904, Field 340282366920938463463374607431768211456
+    v906 = add v903, v905
+    v907 = sub Field 64323764613183177041862057485226039389, v889
+    v908 = cast v901 as Field
+    v909 = sub v907, v908
+    v910 = cast v857 as Field
+    v911 = mul v906, v910
+    range_check v911 to 128 bits
+    v912 = cast v857 as Field
+    v913 = mul v909, v912
+    range_check v913 to 128 bits
+    v915 = call f2(v859, v888) -> u1
+    v916 = sub v859, v888
+    v917 = sub v916, Field 1
+    v918 = cast v915 as Field
+    v919 = mul v918, Field 340282366920938463463374607431768211456
+    v920 = add v917, v919
+    v921 = sub v860, v889
+    v922 = cast v915 as Field
+    v923 = sub v921, v922
+    v924 = cast v857 as Field
+    v925 = mul v920, v924
+    range_check v925 to 128 bits
+    v926 = cast v857 as Field
+    v927 = mul v923, v926
+    range_check v927 to 128 bits
+    v928 = not v856
+    v929 = unchecked_mul v854, v928
+    enable_side_effects v929
+    v931, v932 = call f3(v4) -> (Field, Field)
+    v933 = cast v929 as Field
+    v934 = mul v931, v933
+    range_check v934 to 128 bits
+    v935 = cast v929 as Field
+    v936 = mul v932, v935
+    range_check v936 to 128 bits
+    v937 = mul Field 340282366920938463463374607431768211456, v932
+    v938 = add v931, v937
+    v939 = eq v4, v938
+    v940 = cast v929 as Field
+    v941 = mul v4, v940
+    v942 = mul v938, v940
+    constrain v941 == v942
+    v944 = call f2(Field 53438638232309528389504892708671455233, v931) -> u1
+    v945 = sub Field 53438638232309528389504892708671455233, v931
+    v946 = sub v945, Field 1
+    v947 = cast v944 as Field
+    v948 = mul v947, Field 340282366920938463463374607431768211456
+    v949 = add v946, v948
+    v950 = sub Field 64323764613183177041862057485226039389, v932
+    v951 = cast v944 as Field
+    v952 = sub v950, v951
+    v953 = cast v929 as Field
+    v954 = mul v949, v953
+    range_check v954 to 128 bits
+    v955 = cast v929 as Field
+    v956 = mul v952, v955
+    range_check v956 to 128 bits
+    v958, v959 = call f3(Field 0) -> (Field, Field)
+    v960 = cast v929 as Field
+    v961 = mul v958, v960
+    range_check v961 to 128 bits
+    v962 = cast v929 as Field
+    v963 = mul v959, v962
+    range_check v963 to 128 bits
+    v964 = mul Field 340282366920938463463374607431768211456, v959
+    v965 = add v958, v964
+    v966 = eq Field 0, v965
+    v967 = cast v929 as Field
+    v968 = mul v965, v967
+    constrain Field 0 == v968
+    v970 = call f2(Field 53438638232309528389504892708671455233, v958) -> u1
+    v971 = sub Field 53438638232309528389504892708671455233, v958
+    v972 = sub v971, Field 1
+    v973 = cast v970 as Field
+    v974 = mul v973, Field 340282366920938463463374607431768211456
+    v975 = add v972, v974
+    v976 = sub Field 64323764613183177041862057485226039389, v959
+    v977 = cast v970 as Field
+    v978 = sub v976, v977
+    v979 = cast v929 as Field
+    v980 = mul v975, v979
+    range_check v980 to 128 bits
+    v981 = cast v929 as Field
+    v982 = mul v978, v981
+    range_check v982 to 128 bits
+    v984 = call f2(v931, v958) -> u1
+    v985 = sub v931, v958
+    v986 = sub v985, Field 1
+    v987 = cast v984 as Field
+    v988 = mul v987, Field 340282366920938463463374607431768211456
+    v989 = add v986, v988
+    v990 = sub v932, v959
+    v991 = cast v984 as Field
+    v992 = sub v990, v991
+    v993 = cast v929 as Field
+    v994 = mul v989, v993
+    range_check v994 to 128 bits
+    v995 = cast v929 as Field
+    v996 = mul v992, v995
+    range_check v996 to 128 bits
+    enable_side_effects v929
+    v997 = load v851 -> Field
+    v998 = not v929
+    v999 = cast v929 as Field
+    v1000 = cast v998 as Field
+    v1001 = mul v1000, v997
+    v1002 = add v999, v1001
+    store v1002 at v851
+    enable_side_effects u1 1
+    v1003 = load v851 -> Field
+    v1004 = sub v1003, v850
+    return v1004
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Removing Bit Shifts:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = allocate -> &mut Field
+    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v40 = allocate -> &mut u1
+    store u1 0 at v40
+    enable_side_effects u1 1
+    v44 = array_get v9, index u32 0 -> u8
+    v45 = eq v44, u8 48
+    v46 = not v45
+    v47 = unchecked_mul u1 1, v46
+    enable_side_effects v47
+    v48 = array_get v9, index u32 0 -> u8
+    v49 = lt v48, u8 48
+    v50 = mul v49, v47
+    constrain v50 == v47
+    v51 = load v40 -> u1
+    v52 = not v47
+    v53 = mul v52, v51
+    v54 = unchecked_add v47, v53
+    store v54 at v40
+    v55 = unchecked_mul u1 1, v45
+    enable_side_effects u1 1
+    v56 = load v40 -> u1
+    v57 = not v56
+    enable_side_effects v57
+    v59 = array_get v9, index u32 1 -> u8
+    v60 = eq v59, u8 100
+    v61 = not v60
+    v62 = unchecked_mul v57, v61
+    enable_side_effects v62
+    v63 = array_get v9, index u32 1 -> u8
+    v64 = lt v63, u8 100
+    v65 = mul v64, v62
+    constrain v65 == v62
+    v66 = load v40 -> u1
+    v67 = not v62
+    v68 = mul v67, v66
+    v69 = unchecked_add v62, v68
+    store v69 at v40
+    v70 = unchecked_mul v57, v60
+    enable_side_effects u1 1
+    v71 = load v40 -> u1
+    v72 = not v71
+    enable_side_effects v72
+    v74 = array_get v9, index u32 2 -> u8
+    v75 = eq v74, u8 78
+    v76 = not v75
+    v77 = unchecked_mul v72, v76
+    enable_side_effects v77
+    v78 = array_get v9, index u32 2 -> u8
+    v79 = lt v78, u8 78
+    v80 = mul v79, v77
+    constrain v80 == v77
+    v81 = load v40 -> u1
+    v82 = not v77
+    v83 = mul v82, v81
+    v84 = unchecked_add v77, v83
+    store v84 at v40
+    v85 = unchecked_mul v72, v75
+    enable_side_effects u1 1
+    v86 = load v40 -> u1
+    v87 = not v86
+    enable_side_effects v87
+    v89 = array_get v9, index u32 3 -> u8
+    v90 = eq v89, u8 114
+    v91 = not v90
+    v92 = unchecked_mul v87, v91
+    enable_side_effects v92
+    v93 = array_get v9, index u32 3 -> u8
+    v94 = lt v93, u8 114
+    v95 = mul v94, v92
+    constrain v95 == v92
+    v96 = load v40 -> u1
+    v97 = not v92
+    v98 = mul v97, v96
+    v99 = unchecked_add v92, v98
+    store v99 at v40
+    v100 = unchecked_mul v87, v90
+    enable_side_effects u1 1
+    v101 = load v40 -> u1
+    v102 = not v101
+    enable_side_effects v102
+    v104 = array_get v9, index u32 4 -> u8
+    v105 = eq v104, u8 225
+    v106 = not v105
+    v107 = unchecked_mul v102, v106
+    enable_side_effects v107
+    v108 = array_get v9, index u32 4 -> u8
+    v109 = lt v108, u8 225
+    v110 = mul v109, v107
+    constrain v110 == v107
+    v111 = load v40 -> u1
+    v112 = not v107
+    v113 = mul v112, v111
+    v114 = unchecked_add v107, v113
+    store v114 at v40
+    v115 = unchecked_mul v102, v105
+    enable_side_effects u1 1
+    v116 = load v40 -> u1
+    v117 = not v116
+    enable_side_effects v117
+    v119 = array_get v9, index u32 5 -> u8
+    v120 = eq v119, u8 49
+    v121 = not v120
+    v122 = unchecked_mul v117, v121
+    enable_side_effects v122
+    v123 = array_get v9, index u32 5 -> u8
+    v124 = lt v123, u8 49
+    v125 = mul v124, v122
+    constrain v125 == v122
+    v126 = load v40 -> u1
+    v127 = not v122
+    v128 = mul v127, v126
+    v129 = unchecked_add v122, v128
+    store v129 at v40
+    v130 = unchecked_mul v117, v120
+    enable_side_effects u1 1
+    v131 = load v40 -> u1
+    v132 = not v131
+    enable_side_effects v132
+    v134 = array_get v9, index u32 6 -> u8
+    v135 = eq v134, u8 160
+    v136 = not v135
+    v137 = unchecked_mul v132, v136
+    enable_side_effects v137
+    v138 = array_get v9, index u32 6 -> u8
+    v139 = lt v138, u8 160
+    v140 = mul v139, v137
+    constrain v140 == v137
+    v141 = load v40 -> u1
+    v142 = not v137
+    v143 = mul v142, v141
+    v144 = unchecked_add v137, v143
+    store v144 at v40
+    v145 = unchecked_mul v132, v135
+    enable_side_effects u1 1
+    v146 = load v40 -> u1
+    v147 = not v146
+    enable_side_effects v147
+    v149 = array_get v9, index u32 7 -> u8
+    v150 = eq v149, u8 41
+    v151 = not v150
+    v152 = unchecked_mul v147, v151
+    enable_side_effects v152
+    v153 = array_get v9, index u32 7 -> u8
+    v154 = lt v153, u8 41
+    v155 = mul v154, v152
+    constrain v155 == v152
+    v156 = load v40 -> u1
+    v157 = not v152
+    v158 = mul v157, v156
+    v159 = unchecked_add v152, v158
+    store v159 at v40
+    v160 = unchecked_mul v147, v150
+    enable_side_effects u1 1
+    v161 = load v40 -> u1
+    v162 = not v161
+    enable_side_effects v162
+    v164 = array_get v9, index u32 8 -> u8
+    v165 = eq v164, u8 184
+    v166 = not v165
+    v167 = unchecked_mul v162, v166
+    enable_side_effects v167
+    v168 = array_get v9, index u32 8 -> u8
+    v169 = lt v168, u8 184
+    v170 = mul v169, v167
+    constrain v170 == v167
+    v171 = load v40 -> u1
+    v172 = not v167
+    v173 = mul v172, v171
+    v174 = unchecked_add v167, v173
+    store v174 at v40
+    v175 = unchecked_mul v162, v165
+    enable_side_effects u1 1
+    v176 = load v40 -> u1
+    v177 = not v176
+    enable_side_effects v177
+    v179 = array_get v9, index u32 9 -> u8
+    v180 = eq v179, u8 80
+    v181 = not v180
+    v182 = unchecked_mul v177, v181
+    enable_side_effects v182
+    v183 = array_get v9, index u32 9 -> u8
+    v184 = lt v183, u8 80
+    v185 = mul v184, v182
+    constrain v185 == v182
+    v186 = load v40 -> u1
+    v187 = not v182
+    v188 = mul v187, v186
+    v189 = unchecked_add v182, v188
+    store v189 at v40
+    v190 = unchecked_mul v177, v180
+    enable_side_effects u1 1
+    v191 = load v40 -> u1
+    v192 = not v191
+    enable_side_effects v192
+    v194 = array_get v9, index u32 10 -> u8
+    v195 = eq v194, u8 69
+    v196 = not v195
+    v197 = unchecked_mul v192, v196
+    enable_side_effects v197
+    v198 = array_get v9, index u32 10 -> u8
+    v199 = lt v198, u8 69
+    v200 = mul v199, v197
+    constrain v200 == v197
+    v201 = load v40 -> u1
+    v202 = not v197
+    v203 = mul v202, v201
+    v204 = unchecked_add v197, v203
+    store v204 at v40
+    v205 = unchecked_mul v192, v195
+    enable_side_effects u1 1
+    v206 = load v40 -> u1
+    v207 = not v206
+    enable_side_effects v207
+    v209 = array_get v9, index u32 11 -> u8
+    v210 = eq v209, u8 182
+    v211 = not v210
+    v212 = unchecked_mul v207, v211
+    enable_side_effects v212
+    v213 = array_get v9, index u32 11 -> u8
+    v214 = lt v213, u8 182
+    v215 = mul v214, v212
+    constrain v215 == v212
+    v216 = load v40 -> u1
+    v217 = not v212
+    v218 = mul v217, v216
+    v219 = unchecked_add v212, v218
+    store v219 at v40
+    v220 = unchecked_mul v207, v210
+    enable_side_effects u1 1
+    v221 = load v40 -> u1
+    v222 = not v221
+    enable_side_effects v222
+    v224 = array_get v9, index u32 12 -> u8
+    v225 = eq v224, u8 129
+    v226 = not v225
+    v227 = unchecked_mul v222, v226
+    enable_side_effects v227
+    v228 = array_get v9, index u32 12 -> u8
+    v229 = lt v228, u8 129
+    v230 = mul v229, v227
+    constrain v230 == v227
+    v231 = load v40 -> u1
+    v232 = not v227
+    v233 = mul v232, v231
+    v234 = unchecked_add v227, v233
+    store v234 at v40
+    v235 = unchecked_mul v222, v225
+    enable_side_effects u1 1
+    v236 = load v40 -> u1
+    v237 = not v236
+    enable_side_effects v237
+    v239 = array_get v9, index u32 13 -> u8
+    v240 = eq v239, u8 129
+    v241 = not v240
+    v242 = unchecked_mul v237, v241
+    enable_side_effects v242
+    v243 = array_get v9, index u32 13 -> u8
+    v244 = lt v243, u8 129
+    v245 = mul v244, v242
+    constrain v245 == v242
+    v246 = load v40 -> u1
+    v247 = not v242
+    v248 = mul v247, v246
+    v249 = unchecked_add v242, v248
+    store v249 at v40
+    v250 = unchecked_mul v237, v240
+    enable_side_effects u1 1
+    v251 = load v40 -> u1
+    v252 = not v251
+    enable_side_effects v252
+    v254 = array_get v9, index u32 14 -> u8
+    v255 = eq v254, u8 88
+    v256 = not v255
+    v257 = unchecked_mul v252, v256
+    enable_side_effects v257
+    v258 = array_get v9, index u32 14 -> u8
+    v259 = lt v258, u8 88
+    v260 = mul v259, v257
+    constrain v260 == v257
+    v261 = load v40 -> u1
+    v262 = not v257
+    v263 = mul v262, v261
+    v264 = unchecked_add v257, v263
+    store v264 at v40
+    v265 = unchecked_mul v252, v255
+    enable_side_effects u1 1
+    v266 = load v40 -> u1
+    v267 = not v266
+    enable_side_effects v267
+    v269 = array_get v9, index u32 15 -> u8
+    v270 = eq v269, u8 93
+    v271 = not v270
+    v272 = unchecked_mul v267, v271
+    enable_side_effects v272
+    v273 = array_get v9, index u32 15 -> u8
+    v274 = lt v273, u8 93
+    v275 = mul v274, v272
+    constrain v275 == v272
+    v276 = load v40 -> u1
+    v277 = not v272
+    v278 = mul v277, v276
+    v279 = unchecked_add v272, v278
+    store v279 at v40
+    v280 = unchecked_mul v267, v270
+    enable_side_effects u1 1
+    v281 = load v40 -> u1
+    v282 = not v281
+    enable_side_effects v282
+    v284 = array_get v9, index u32 16 -> u8
+    v285 = eq v284, u8 40
+    v286 = not v285
+    v287 = unchecked_mul v282, v286
+    enable_side_effects v287
+    v288 = array_get v9, index u32 16 -> u8
+    v289 = lt v288, u8 40
+    v290 = mul v289, v287
+    constrain v290 == v287
+    v291 = load v40 -> u1
+    v292 = not v287
+    v293 = mul v292, v291
+    v294 = unchecked_add v287, v293
+    store v294 at v40
+    v295 = unchecked_mul v282, v285
+    enable_side_effects u1 1
+    v296 = load v40 -> u1
+    v297 = not v296
+    enable_side_effects v297
+    v299 = array_get v9, index u32 17 -> u8
+    v300 = eq v299, u8 51
+    v301 = not v300
+    v302 = unchecked_mul v297, v301
+    enable_side_effects v302
+    v303 = array_get v9, index u32 17 -> u8
+    v304 = lt v303, u8 51
+    v305 = mul v304, v302
+    constrain v305 == v302
+    v306 = load v40 -> u1
+    v307 = not v302
+    v308 = mul v307, v306
+    v309 = unchecked_add v302, v308
+    store v309 at v40
+    v310 = unchecked_mul v297, v300
+    enable_side_effects u1 1
+    v311 = load v40 -> u1
+    v312 = not v311
+    enable_side_effects v312
+    v314 = array_get v9, index u32 18 -> u8
+    v315 = eq v314, u8 232
+    v316 = not v315
+    v317 = unchecked_mul v312, v316
+    enable_side_effects v317
+    v318 = array_get v9, index u32 18 -> u8
+    v319 = lt v318, u8 232
+    v320 = mul v319, v317
+    constrain v320 == v317
+    v321 = load v40 -> u1
+    v322 = not v317
+    v323 = mul v322, v321
+    v324 = unchecked_add v317, v323
+    store v324 at v40
+    v325 = unchecked_mul v312, v315
+    enable_side_effects u1 1
+    v326 = load v40 -> u1
+    v327 = not v326
+    enable_side_effects v327
+    v329 = array_get v9, index u32 19 -> u8
+    v330 = eq v329, u8 72
+    v331 = not v330
+    v332 = unchecked_mul v327, v331
+    enable_side_effects v332
+    v333 = array_get v9, index u32 19 -> u8
+    v334 = lt v333, u8 72
+    v335 = mul v334, v332
+    constrain v335 == v332
+    v336 = load v40 -> u1
+    v337 = not v332
+    v338 = mul v337, v336
+    v339 = unchecked_add v332, v338
+    store v339 at v40
+    v340 = unchecked_mul v327, v330
+    enable_side_effects u1 1
+    v341 = load v40 -> u1
+    v342 = not v341
+    enable_side_effects v342
+    v344 = array_get v9, index u32 20 -> u8
+    v345 = eq v344, u8 121
+    v346 = not v345
+    v347 = unchecked_mul v342, v346
+    enable_side_effects v347
+    v348 = array_get v9, index u32 20 -> u8
+    v349 = lt v348, u8 121
+    v350 = mul v349, v347
+    constrain v350 == v347
+    v351 = load v40 -> u1
+    v352 = not v347
+    v353 = mul v352, v351
+    v354 = unchecked_add v347, v353
+    store v354 at v40
+    v355 = unchecked_mul v342, v345
+    enable_side_effects u1 1
+    v356 = load v40 -> u1
+    v357 = not v356
+    enable_side_effects v357
+    v359 = array_get v9, index u32 21 -> u8
+    v360 = eq v359, u8 185
+    v361 = not v360
+    v362 = unchecked_mul v357, v361
+    enable_side_effects v362
+    v363 = array_get v9, index u32 21 -> u8
+    v364 = lt v363, u8 185
+    v365 = mul v364, v362
+    constrain v365 == v362
+    v366 = load v40 -> u1
+    v367 = not v362
+    v368 = mul v367, v366
+    v369 = unchecked_add v362, v368
+    store v369 at v40
+    v370 = unchecked_mul v357, v360
+    enable_side_effects u1 1
+    v371 = load v40 -> u1
+    v372 = not v371
+    enable_side_effects v372
+    v374 = array_get v9, index u32 22 -> u8
+    v375 = eq v374, u8 112
+    v376 = not v375
+    v377 = unchecked_mul v372, v376
+    enable_side_effects v377
+    v378 = array_get v9, index u32 22 -> u8
+    v379 = lt v378, u8 112
+    v380 = mul v379, v377
+    constrain v380 == v377
+    v381 = load v40 -> u1
+    v382 = not v377
+    v383 = mul v382, v381
+    v384 = unchecked_add v377, v383
+    store v384 at v40
+    v385 = unchecked_mul v372, v375
+    enable_side_effects u1 1
+    v386 = load v40 -> u1
+    v387 = not v386
+    enable_side_effects v387
+    v389 = array_get v9, index u32 23 -> u8
+    v390 = eq v389, u8 145
+    v391 = not v390
+    v392 = unchecked_mul v387, v391
+    enable_side_effects v392
+    v393 = array_get v9, index u32 23 -> u8
+    v394 = lt v393, u8 145
+    v395 = mul v394, v392
+    constrain v395 == v392
+    v396 = load v40 -> u1
+    v397 = not v392
+    v398 = mul v397, v396
+    v399 = unchecked_add v392, v398
+    store v399 at v40
+    v400 = unchecked_mul v387, v390
+    enable_side_effects u1 1
+    v401 = load v40 -> u1
+    v402 = not v401
+    enable_side_effects v402
+    v404 = array_get v9, index u32 24 -> u8
+    v405 = eq v404, u8 67
+    v406 = not v405
+    v407 = unchecked_mul v402, v406
+    enable_side_effects v407
+    v408 = array_get v9, index u32 24 -> u8
+    v409 = lt v408, u8 67
+    v410 = mul v409, v407
+    constrain v410 == v407
+    v411 = load v40 -> u1
+    v412 = not v407
+    v413 = mul v412, v411
+    v414 = unchecked_add v407, v413
+    store v414 at v40
+    v415 = unchecked_mul v402, v405
+    enable_side_effects u1 1
+    v416 = load v40 -> u1
+    v417 = not v416
+    enable_side_effects v417
+    v419 = array_get v9, index u32 25 -> u8
+    v420 = eq v419, u8 225
+    v421 = not v420
+    v422 = unchecked_mul v417, v421
+    enable_side_effects v422
+    v423 = array_get v9, index u32 25 -> u8
+    v424 = lt v423, u8 225
+    v425 = mul v424, v422
+    constrain v425 == v422
+    v426 = load v40 -> u1
+    v427 = not v422
+    v428 = mul v427, v426
+    v429 = unchecked_add v422, v428
+    store v429 at v40
+    v430 = unchecked_mul v417, v420
+    enable_side_effects u1 1
+    v431 = load v40 -> u1
+    v432 = not v431
+    enable_side_effects v432
+    v434 = array_get v9, index u32 26 -> u8
+    v435 = eq v434, u8 245
+    v436 = not v435
+    v437 = unchecked_mul v432, v436
+    enable_side_effects v437
+    v438 = array_get v9, index u32 26 -> u8
+    v439 = lt v438, u8 245
+    v440 = mul v439, v437
+    constrain v440 == v437
+    v441 = load v40 -> u1
+    v442 = not v437
+    v443 = mul v442, v441
+    v444 = unchecked_add v437, v443
+    store v444 at v40
+    v445 = unchecked_mul v432, v435
+    enable_side_effects u1 1
+    v446 = load v40 -> u1
+    v447 = not v446
+    enable_side_effects v447
+    v449 = array_get v9, index u32 27 -> u8
+    v450 = eq v449, u8 147
+    v451 = not v450
+    v452 = unchecked_mul v447, v451
+    enable_side_effects v452
+    v453 = array_get v9, index u32 27 -> u8
+    v454 = lt v453, u8 147
+    v455 = mul v454, v452
+    constrain v455 == v452
+    v456 = load v40 -> u1
+    v457 = not v452
+    v458 = mul v457, v456
+    v459 = unchecked_add v452, v458
+    store v459 at v40
+    v460 = unchecked_mul v447, v450
+    enable_side_effects u1 1
+    v461 = load v40 -> u1
+    v462 = not v461
+    enable_side_effects v462
+    v464 = array_get v9, index u32 28 -> u8
+    v465 = eq v464, u8 240
+    v466 = not v465
+    v467 = unchecked_mul v462, v466
+    enable_side_effects v467
+    v468 = array_get v9, index u32 28 -> u8
+    v469 = lt v468, u8 240
+    v470 = mul v469, v467
+    constrain v470 == v467
+    v471 = load v40 -> u1
+    v472 = not v467
+    v473 = mul v472, v471
+    v474 = unchecked_add v467, v473
+    store v474 at v40
+    v475 = unchecked_mul v462, v465
+    enable_side_effects u1 1
+    v476 = load v40 -> u1
+    v477 = not v476
+    enable_side_effects v477
+    v479 = array_get v9, index u32 29 -> u8
+    v480 = eq v479, u8 0
+    v481 = not v480
+    v482 = unchecked_mul v477, v481
+    enable_side_effects v482
+    v483 = array_get v9, index u32 29 -> u8
+    constrain u1 0 == v482
+    v484 = load v40 -> u1
+    v485 = not v482
+    v486 = mul v485, v484
+    v487 = unchecked_add v482, v486
+    store v487 at v40
+    v488 = unchecked_mul v477, v480
+    enable_side_effects u1 1
+    v489 = load v40 -> u1
+    v490 = not v489
+    enable_side_effects v490
+    v492 = array_get v9, index u32 30 -> u8
+    v493 = eq v492, u8 0
+    v494 = not v493
+    v495 = unchecked_mul v490, v494
+    enable_side_effects v495
+    v496 = array_get v9, index u32 30 -> u8
+    constrain u1 0 == v495
+    v497 = load v40 -> u1
+    v498 = not v495
+    v499 = mul v498, v497
+    v500 = unchecked_add v495, v499
+    store v500 at v40
+    v501 = unchecked_mul v490, v493
+    enable_side_effects u1 1
+    v502 = load v40 -> u1
+    v503 = not v502
+    enable_side_effects v503
+    v505 = array_get v9, index u32 31 -> u8
+    v506 = eq v505, u8 1
+    v507 = not v506
+    v508 = unchecked_mul v503, v507
+    enable_side_effects v508
+    v509 = array_get v9, index u32 31 -> u8
+    v510 = eq v509, u8 0
+    v511 = cast v508 as u8
+    v512 = unchecked_mul v509, v511
+    constrain v512 == u8 0
+    v513 = load v40 -> u1
+    v514 = not v508
+    v515 = mul v514, v513
+    v516 = unchecked_add v508, v515
+    store v516 at v40
+    v517 = unchecked_mul v503, v506
+    enable_side_effects u1 1
+    v518 = load v40 -> u1
+    constrain v518 == u1 1
+    v519 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v520 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v521 = allocate -> &mut u1
+    store u1 0 at v521
+    enable_side_effects u1 1
+    v522 = load v521 -> u1
+    store u1 1 at v521
+    enable_side_effects u1 1
+    v523 = load v521 -> u1
+    v524 = not v523
+    enable_side_effects v524
+    v525 = load v521 -> u1
+    v526 = mul v523, v525
+    v527 = unchecked_add v524, v526
+    store v527 at v521
+    enable_side_effects u1 1
+    v528 = load v521 -> u1
+    v529 = not v528
+    enable_side_effects v529
+    v530 = load v521 -> u1
+    v531 = mul v528, v530
+    v532 = unchecked_add v529, v531
+    store v532 at v521
+    enable_side_effects u1 1
+    v533 = load v521 -> u1
+    v534 = not v533
+    enable_side_effects v534
+    v535 = load v521 -> u1
+    v536 = mul v533, v535
+    v537 = unchecked_add v534, v536
+    store v537 at v521
+    enable_side_effects u1 1
+    v538 = load v521 -> u1
+    v539 = not v538
+    enable_side_effects v539
+    v540 = load v521 -> u1
+    v541 = mul v538, v540
+    v542 = unchecked_add v539, v541
+    store v542 at v521
+    enable_side_effects u1 1
+    v543 = load v521 -> u1
+    v544 = not v543
+    enable_side_effects v544
+    v545 = load v521 -> u1
+    v546 = mul v543, v545
+    v547 = unchecked_add v544, v546
+    store v547 at v521
+    enable_side_effects u1 1
+    v548 = load v521 -> u1
+    v549 = not v548
+    enable_side_effects v549
+    v550 = load v521 -> u1
+    v551 = mul v548, v550
+    v552 = unchecked_add v549, v551
+    store v552 at v521
+    enable_side_effects u1 1
+    v553 = load v521 -> u1
+    v554 = not v553
+    enable_side_effects v554
+    v555 = load v521 -> u1
+    v556 = mul v553, v555
+    v557 = unchecked_add v554, v556
+    store v557 at v521
+    enable_side_effects u1 1
+    v558 = load v521 -> u1
+    v559 = not v558
+    enable_side_effects v559
+    v560 = load v521 -> u1
+    v561 = mul v558, v560
+    v562 = unchecked_add v559, v561
+    store v562 at v521
+    enable_side_effects u1 1
+    v563 = load v521 -> u1
+    v564 = not v563
+    enable_side_effects v564
+    v565 = load v521 -> u1
+    v566 = mul v563, v565
+    v567 = unchecked_add v564, v566
+    store v567 at v521
+    enable_side_effects u1 1
+    v568 = load v521 -> u1
+    v569 = not v568
+    enable_side_effects v569
+    v570 = load v521 -> u1
+    v571 = mul v568, v570
+    v572 = unchecked_add v569, v571
+    store v572 at v521
+    enable_side_effects u1 1
+    v573 = load v521 -> u1
+    v574 = not v573
+    enable_side_effects v574
+    v575 = load v521 -> u1
+    v576 = mul v573, v575
+    v577 = unchecked_add v574, v576
+    store v577 at v521
+    enable_side_effects u1 1
+    v578 = load v521 -> u1
+    v579 = not v578
+    enable_side_effects v579
+    v580 = load v521 -> u1
+    v581 = mul v578, v580
+    v582 = unchecked_add v579, v581
+    store v582 at v521
+    enable_side_effects u1 1
+    v583 = load v521 -> u1
+    v584 = not v583
+    enable_side_effects v584
+    v585 = load v521 -> u1
+    v586 = mul v583, v585
+    v587 = unchecked_add v584, v586
+    store v587 at v521
+    enable_side_effects u1 1
+    v588 = load v521 -> u1
+    v589 = not v588
+    enable_side_effects v589
+    v590 = load v521 -> u1
+    v591 = mul v588, v590
+    v592 = unchecked_add v589, v591
+    store v592 at v521
+    enable_side_effects u1 1
+    v593 = load v521 -> u1
+    v594 = not v593
+    enable_side_effects v594
+    v595 = load v521 -> u1
+    v596 = mul v593, v595
+    v597 = unchecked_add v594, v596
+    store v597 at v521
+    enable_side_effects u1 1
+    v598 = load v521 -> u1
+    v599 = not v598
+    enable_side_effects v599
+    v600 = load v521 -> u1
+    v601 = mul v598, v600
+    v602 = unchecked_add v599, v601
+    store v602 at v521
+    enable_side_effects u1 1
+    v603 = load v521 -> u1
+    v604 = not v603
+    enable_side_effects v604
+    v605 = load v521 -> u1
+    v606 = mul v603, v605
+    v607 = unchecked_add v604, v606
+    store v607 at v521
+    enable_side_effects u1 1
+    v608 = load v521 -> u1
+    v609 = not v608
+    enable_side_effects v609
+    v610 = load v521 -> u1
+    v611 = mul v608, v610
+    v612 = unchecked_add v609, v611
+    store v612 at v521
+    enable_side_effects u1 1
+    v613 = load v521 -> u1
+    v614 = not v613
+    enable_side_effects v614
+    v615 = load v521 -> u1
+    v616 = mul v613, v615
+    v617 = unchecked_add v614, v616
+    store v617 at v521
+    enable_side_effects u1 1
+    v618 = load v521 -> u1
+    v619 = not v618
+    enable_side_effects v619
+    v620 = load v521 -> u1
+    v621 = mul v618, v620
+    v622 = unchecked_add v619, v621
+    store v622 at v521
+    enable_side_effects u1 1
+    v623 = load v521 -> u1
+    v624 = not v623
+    enable_side_effects v624
+    v625 = load v521 -> u1
+    v626 = mul v623, v625
+    v627 = unchecked_add v624, v626
+    store v627 at v521
+    enable_side_effects u1 1
+    v628 = load v521 -> u1
+    v629 = not v628
+    enable_side_effects v629
+    v630 = load v521 -> u1
+    v631 = mul v628, v630
+    v632 = unchecked_add v629, v631
+    store v632 at v521
+    enable_side_effects u1 1
+    v633 = load v521 -> u1
+    v634 = not v633
+    enable_side_effects v634
+    v635 = load v521 -> u1
+    v636 = mul v633, v635
+    v637 = unchecked_add v634, v636
+    store v637 at v521
+    enable_side_effects u1 1
+    v638 = load v521 -> u1
+    v639 = not v638
+    enable_side_effects v639
+    v640 = load v521 -> u1
+    v641 = mul v638, v640
+    v642 = unchecked_add v639, v641
+    store v642 at v521
+    enable_side_effects u1 1
+    v643 = load v521 -> u1
+    v644 = not v643
+    enable_side_effects v644
+    v645 = load v521 -> u1
+    v646 = mul v643, v645
+    v647 = unchecked_add v644, v646
+    store v647 at v521
+    enable_side_effects u1 1
+    v648 = load v521 -> u1
+    v649 = not v648
+    enable_side_effects v649
+    v650 = load v521 -> u1
+    v651 = mul v648, v650
+    v652 = unchecked_add v649, v651
+    store v652 at v521
+    enable_side_effects u1 1
+    v653 = load v521 -> u1
+    v654 = not v653
+    enable_side_effects v654
+    v655 = load v521 -> u1
+    v656 = mul v653, v655
+    v657 = unchecked_add v654, v656
+    store v657 at v521
+    enable_side_effects u1 1
+    v658 = load v521 -> u1
+    v659 = not v658
+    enable_side_effects v659
+    v660 = load v521 -> u1
+    v661 = mul v658, v660
+    v662 = unchecked_add v659, v661
+    store v662 at v521
+    enable_side_effects u1 1
+    v663 = load v521 -> u1
+    v664 = not v663
+    enable_side_effects u1 1
+    v665 = load v521 -> u1
+    v666 = not v665
+    enable_side_effects u1 1
+    v667 = load v521 -> u1
+    v668 = not v667
+    enable_side_effects v668
+    v669 = load v521 -> u1
+    v670 = mul v667, v669
+    v671 = unchecked_add v668, v670
+    store v671 at v521
+    enable_side_effects u1 1
+    v672 = load v521 -> u1
+    constrain v672 == u1 1
+    v673 = allocate -> &mut [u8; 32]
+    v674 = array_get v9, index u32 0 -> u8
+    v675 = make_array [v674, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v676 = array_get v9, index u32 1 -> u8
+    v677 = make_array [v674, v676, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v678 = array_get v9, index u32 2 -> u8
+    v679 = make_array [v674, v676, v678, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v680 = array_get v9, index u32 3 -> u8
+    v681 = make_array [v674, v676, v678, v680, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v682 = array_get v9, index u32 4 -> u8
+    v683 = make_array [v674, v676, v678, v680, v682, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v684 = array_get v9, index u32 5 -> u8
+    v685 = make_array [v674, v676, v678, v680, v682, v684, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v686 = array_get v9, index u32 6 -> u8
+    v687 = make_array [v674, v676, v678, v680, v682, v684, v686, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v688 = array_get v9, index u32 7 -> u8
+    v689 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v690 = array_get v9, index u32 8 -> u8
+    v691 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v692 = array_get v9, index u32 9 -> u8
+    v693 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v694 = array_get v9, index u32 10 -> u8
+    v695 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v696 = array_get v9, index u32 11 -> u8
+    v697 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v698 = array_get v9, index u32 12 -> u8
+    v699 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v700 = array_get v9, index u32 13 -> u8
+    v701 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v702 = array_get v9, index u32 14 -> u8
+    v703 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v704 = array_get v9, index u32 15 -> u8
+    v705 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v706 = array_get v9, index u32 16 -> u8
+    v707 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v708 = array_get v9, index u32 17 -> u8
+    v709 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v710 = array_get v9, index u32 18 -> u8
+    v711 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v712 = array_get v9, index u32 19 -> u8
+    v713 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v714 = array_get v9, index u32 20 -> u8
+    v715 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v716 = array_get v9, index u32 21 -> u8
+    v717 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v718 = array_get v9, index u32 22 -> u8
+    v719 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v720 = array_get v9, index u32 23 -> u8
+    v721 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v722 = array_get v9, index u32 24 -> u8
+    v723 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v724 = array_get v9, index u32 25 -> u8
+    v725 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v726 = array_get v9, index u32 26 -> u8
+    v727 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v728 = array_get v9, index u32 27 -> u8
+    v729 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v730 = array_get v9, index u32 28 -> u8
+    v731 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, u8 0, u8 0, u8 0] : [u8; 32]
+    v732 = array_get v9, index u32 29 -> u8
+    v733 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, v732, u8 0, u8 0] : [u8; 32]
+    v734 = array_get v9, index u32 30 -> u8
+    v735 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, v732, v734, u8 0] : [u8; 32]
+    v736 = array_get v9, index u32 31 -> u8
+    v737 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, v732, v734, v736] : [u8; 32]
+    v738 = allocate -> &mut Field
+    v739 = allocate -> &mut Field
+    v740 = allocate -> &mut Field
+    v741 = cast v704 as Field
+    v742 = cast v736 as Field
+    v743 = cast v702 as Field
+    v745 = mul v743, Field 256
+    v746 = add v741, v745
+    v747 = cast v734 as Field
+    v748 = mul v747, Field 256
+    v749 = add v742, v748
+    v750 = cast v700 as Field
+    v752 = mul v750, Field 65536
+    v753 = add v746, v752
+    v754 = cast v732 as Field
+    v755 = mul v754, Field 65536
+    v756 = add v749, v755
+    v757 = cast v698 as Field
+    v759 = mul v757, Field 16777216
+    v760 = add v753, v759
+    v761 = cast v730 as Field
+    v762 = mul v761, Field 16777216
+    v763 = add v756, v762
+    v764 = cast v696 as Field
+    v766 = mul v764, Field 4294967296
+    v767 = add v760, v766
+    v768 = cast v728 as Field
+    v769 = mul v768, Field 4294967296
+    v770 = add v763, v769
+    v771 = cast v694 as Field
+    v773 = mul v771, Field 1099511627776
+    v774 = add v767, v773
+    v775 = cast v726 as Field
+    v776 = mul v775, Field 1099511627776
+    v777 = add v770, v776
+    v778 = cast v692 as Field
+    v780 = mul v778, Field 281474976710656
+    v781 = add v774, v780
+    v782 = cast v724 as Field
+    v783 = mul v782, Field 281474976710656
+    v784 = add v777, v783
+    v785 = cast v690 as Field
+    v787 = mul v785, Field 72057594037927936
+    v788 = add v781, v787
+    v789 = cast v722 as Field
+    v790 = mul v789, Field 72057594037927936
+    v791 = add v784, v790
+    v792 = cast v688 as Field
+    v794 = mul v792, Field 18446744073709551616
+    v795 = add v788, v794
+    v796 = cast v720 as Field
+    v797 = mul v796, Field 18446744073709551616
+    v798 = add v791, v797
+    v799 = cast v686 as Field
+    v801 = mul v799, Field 4722366482869645213696
+    v802 = add v795, v801
+    v803 = cast v718 as Field
+    v804 = mul v803, Field 4722366482869645213696
+    v805 = add v798, v804
+    v806 = cast v684 as Field
+    v808 = mul v806, Field 1208925819614629174706176
+    v809 = add v802, v808
+    v810 = cast v716 as Field
+    v811 = mul v810, Field 1208925819614629174706176
+    v812 = add v805, v811
+    v813 = cast v682 as Field
+    v815 = mul v813, Field 309485009821345068724781056
+    v816 = add v809, v815
+    v817 = cast v714 as Field
+    v818 = mul v817, Field 309485009821345068724781056
+    v819 = add v812, v818
+    v820 = cast v680 as Field
+    v822 = mul v820, Field 79228162514264337593543950336
+    v823 = add v816, v822
+    v824 = cast v712 as Field
+    v825 = mul v824, Field 79228162514264337593543950336
+    v826 = add v819, v825
+    v827 = cast v678 as Field
+    v829 = mul v827, Field 20282409603651670423947251286016
+    v830 = add v823, v829
+    v831 = cast v710 as Field
+    v832 = mul v831, Field 20282409603651670423947251286016
+    v833 = add v826, v832
+    v834 = cast v676 as Field
+    v836 = mul v834, Field 5192296858534827628530496329220096
+    v837 = add v830, v836
+    v838 = cast v708 as Field
+    v839 = mul v838, Field 5192296858534827628530496329220096
+    v840 = add v833, v839
+    v841 = cast v674 as Field
+    v843 = mul v841, Field 1329227995784915872903807060280344576
+    v844 = add v837, v843
+    v845 = cast v706 as Field
+    v846 = mul v845, Field 1329227995784915872903807060280344576
+    v847 = add v840, v846
+    v849 = mul v844, Field 340282366920938463463374607431768211456
+    v850 = add v847, v849
+    v851 = allocate -> &mut Field
+    store Field 0 at v851
+    v853 = eq v4, Field 0
+    enable_side_effects v853
+    v854 = not v853
+    enable_side_effects v854
+    v856 = call f1(v4, Field 0) -> u1
+    v857 = unchecked_mul v854, v856
+    enable_side_effects v857
+    v859, v860 = call f3(Field 0) -> (Field, Field)
+    v861 = cast v857 as Field
+    v862 = mul v859, v861
+    range_check v862 to 128 bits
+    v863 = cast v857 as Field
+    v864 = mul v860, v863
+    range_check v864 to 128 bits
+    v865 = mul Field 340282366920938463463374607431768211456, v860
+    v866 = add v859, v865
+    v867 = eq Field 0, v866
+    v868 = cast v857 as Field
+    v869 = mul v866, v868
+    constrain Field 0 == v869
+    v872 = call f2(Field 53438638232309528389504892708671455233, v859) -> u1
+    v873 = sub Field 53438638232309528389504892708671455233, v859
+    v875 = sub v873, Field 1
+    v876 = cast v872 as Field
+    v877 = mul v876, Field 340282366920938463463374607431768211456
+    v878 = add v875, v877
+    v880 = sub Field 64323764613183177041862057485226039389, v860
+    v881 = cast v872 as Field
+    v882 = sub v880, v881
+    v883 = cast v857 as Field
+    v884 = mul v878, v883
+    range_check v884 to 128 bits
+    v885 = cast v857 as Field
+    v886 = mul v882, v885
+    range_check v886 to 128 bits
+    v888, v889 = call f3(v4) -> (Field, Field)
+    v890 = cast v857 as Field
+    v891 = mul v888, v890
+    range_check v891 to 128 bits
+    v892 = cast v857 as Field
+    v893 = mul v889, v892
+    range_check v893 to 128 bits
+    v894 = mul Field 340282366920938463463374607431768211456, v889
+    v895 = add v888, v894
+    v896 = eq v4, v895
+    v897 = cast v857 as Field
+    v898 = mul v4, v897
+    v899 = mul v895, v897
+    constrain v898 == v899
+    v901 = call f2(Field 53438638232309528389504892708671455233, v888) -> u1
+    v902 = sub Field 53438638232309528389504892708671455233, v888
+    v903 = sub v902, Field 1
+    v904 = cast v901 as Field
+    v905 = mul v904, Field 340282366920938463463374607431768211456
+    v906 = add v903, v905
+    v907 = sub Field 64323764613183177041862057485226039389, v889
+    v908 = cast v901 as Field
+    v909 = sub v907, v908
+    v910 = cast v857 as Field
+    v911 = mul v906, v910
+    range_check v911 to 128 bits
+    v912 = cast v857 as Field
+    v913 = mul v909, v912
+    range_check v913 to 128 bits
+    v915 = call f2(v859, v888) -> u1
+    v916 = sub v859, v888
+    v917 = sub v916, Field 1
+    v918 = cast v915 as Field
+    v919 = mul v918, Field 340282366920938463463374607431768211456
+    v920 = add v917, v919
+    v921 = sub v860, v889
+    v922 = cast v915 as Field
+    v923 = sub v921, v922
+    v924 = cast v857 as Field
+    v925 = mul v920, v924
+    range_check v925 to 128 bits
+    v926 = cast v857 as Field
+    v927 = mul v923, v926
+    range_check v927 to 128 bits
+    v928 = not v856
+    v929 = unchecked_mul v854, v928
+    enable_side_effects v929
+    v931, v932 = call f3(v4) -> (Field, Field)
+    v933 = cast v929 as Field
+    v934 = mul v931, v933
+    range_check v934 to 128 bits
+    v935 = cast v929 as Field
+    v936 = mul v932, v935
+    range_check v936 to 128 bits
+    v937 = mul Field 340282366920938463463374607431768211456, v932
+    v938 = add v931, v937
+    v939 = eq v4, v938
+    v940 = cast v929 as Field
+    v941 = mul v4, v940
+    v942 = mul v938, v940
+    constrain v941 == v942
+    v944 = call f2(Field 53438638232309528389504892708671455233, v931) -> u1
+    v945 = sub Field 53438638232309528389504892708671455233, v931
+    v946 = sub v945, Field 1
+    v947 = cast v944 as Field
+    v948 = mul v947, Field 340282366920938463463374607431768211456
+    v949 = add v946, v948
+    v950 = sub Field 64323764613183177041862057485226039389, v932
+    v951 = cast v944 as Field
+    v952 = sub v950, v951
+    v953 = cast v929 as Field
+    v954 = mul v949, v953
+    range_check v954 to 128 bits
+    v955 = cast v929 as Field
+    v956 = mul v952, v955
+    range_check v956 to 128 bits
+    v958, v959 = call f3(Field 0) -> (Field, Field)
+    v960 = cast v929 as Field
+    v961 = mul v958, v960
+    range_check v961 to 128 bits
+    v962 = cast v929 as Field
+    v963 = mul v959, v962
+    range_check v963 to 128 bits
+    v964 = mul Field 340282366920938463463374607431768211456, v959
+    v965 = add v958, v964
+    v966 = eq Field 0, v965
+    v967 = cast v929 as Field
+    v968 = mul v965, v967
+    constrain Field 0 == v968
+    v970 = call f2(Field 53438638232309528389504892708671455233, v958) -> u1
+    v971 = sub Field 53438638232309528389504892708671455233, v958
+    v972 = sub v971, Field 1
+    v973 = cast v970 as Field
+    v974 = mul v973, Field 340282366920938463463374607431768211456
+    v975 = add v972, v974
+    v976 = sub Field 64323764613183177041862057485226039389, v959
+    v977 = cast v970 as Field
+    v978 = sub v976, v977
+    v979 = cast v929 as Field
+    v980 = mul v975, v979
+    range_check v980 to 128 bits
+    v981 = cast v929 as Field
+    v982 = mul v978, v981
+    range_check v982 to 128 bits
+    v984 = call f2(v931, v958) -> u1
+    v985 = sub v931, v958
+    v986 = sub v985, Field 1
+    v987 = cast v984 as Field
+    v988 = mul v987, Field 340282366920938463463374607431768211456
+    v989 = add v986, v988
+    v990 = sub v932, v959
+    v991 = cast v984 as Field
+    v992 = sub v990, v991
+    v993 = cast v929 as Field
+    v994 = mul v989, v993
+    range_check v994 to 128 bits
+    v995 = cast v929 as Field
+    v996 = mul v992, v995
+    range_check v996 to 128 bits
+    enable_side_effects v929
+    v997 = load v851 -> Field
+    v998 = not v929
+    v999 = cast v929 as Field
+    v1000 = cast v998 as Field
+    v1001 = mul v1000, v997
+    v1002 = add v999, v1001
+    store v1002 at v851
+    enable_side_effects u1 1
+    v1003 = load v851 -> Field
+    v1004 = sub v1003, v850
+    return v1004
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Mem2Reg (3rd):
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = allocate -> &mut Field
+    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v40 = allocate -> &mut u1
+    enable_side_effects u1 1
+    v43 = array_get v9, index u32 0 -> u8
+    v44 = eq v43, u8 48
+    v45 = not v44
+    enable_side_effects v45
+    v46 = array_get v9, index u32 0 -> u8
+    v47 = lt v46, u8 48
+    v48 = mul v47, v45
+    constrain v48 == v45
+    enable_side_effects u1 1
+    enable_side_effects v44
+    v50 = array_get v9, index u32 1 -> u8
+    v51 = eq v50, u8 100
+    v52 = not v51
+    v53 = mul v44, v52
+    enable_side_effects v53
+    v54 = array_get v9, index u32 1 -> u8
+    v55 = lt v54, u8 100
+    v56 = mul v55, v53
+    constrain v56 == v53
+    v57 = not v53
+    v58 = mul v57, v45
+    v59 = unchecked_add v53, v58
+    v60 = mul v44, v51
+    enable_side_effects u1 1
+    v61 = not v59
+    enable_side_effects v61
+    v63 = array_get v9, index u32 2 -> u8
+    v64 = eq v63, u8 78
+    v65 = not v64
+    v66 = mul v61, v65
+    enable_side_effects v66
+    v67 = array_get v9, index u32 2 -> u8
+    v68 = lt v67, u8 78
+    v69 = mul v68, v66
+    constrain v69 == v66
+    v70 = not v66
+    v71 = mul v70, v59
+    v72 = unchecked_add v66, v71
+    v73 = mul v61, v64
+    enable_side_effects u1 1
+    v74 = not v72
+    enable_side_effects v74
+    v76 = array_get v9, index u32 3 -> u8
+    v77 = eq v76, u8 114
+    v78 = not v77
+    v79 = mul v74, v78
+    enable_side_effects v79
+    v80 = array_get v9, index u32 3 -> u8
+    v81 = lt v80, u8 114
+    v82 = mul v81, v79
+    constrain v82 == v79
+    v83 = not v79
+    v84 = mul v83, v72
+    v85 = unchecked_add v79, v84
+    v86 = mul v74, v77
+    enable_side_effects u1 1
+    v87 = not v85
+    enable_side_effects v87
+    v89 = array_get v9, index u32 4 -> u8
+    v90 = eq v89, u8 225
+    v91 = not v90
+    v92 = mul v87, v91
+    enable_side_effects v92
+    v93 = array_get v9, index u32 4 -> u8
+    v94 = lt v93, u8 225
+    v95 = mul v94, v92
+    constrain v95 == v92
+    v96 = not v92
+    v97 = mul v96, v85
+    v98 = unchecked_add v92, v97
+    v99 = mul v87, v90
+    enable_side_effects u1 1
+    v100 = not v98
+    enable_side_effects v100
+    v102 = array_get v9, index u32 5 -> u8
+    v103 = eq v102, u8 49
+    v104 = not v103
+    v105 = mul v100, v104
+    enable_side_effects v105
+    v106 = array_get v9, index u32 5 -> u8
+    v107 = lt v106, u8 49
+    v108 = mul v107, v105
+    constrain v108 == v105
+    v109 = not v105
+    v110 = mul v109, v98
+    v111 = unchecked_add v105, v110
+    v112 = mul v100, v103
+    enable_side_effects u1 1
+    v113 = not v111
+    enable_side_effects v113
+    v115 = array_get v9, index u32 6 -> u8
+    v116 = eq v115, u8 160
+    v117 = not v116
+    v118 = mul v113, v117
+    enable_side_effects v118
+    v119 = array_get v9, index u32 6 -> u8
+    v120 = lt v119, u8 160
+    v121 = mul v120, v118
+    constrain v121 == v118
+    v122 = not v118
+    v123 = mul v122, v111
+    v124 = unchecked_add v118, v123
+    v125 = mul v113, v116
+    enable_side_effects u1 1
+    v126 = not v124
+    enable_side_effects v126
+    v128 = array_get v9, index u32 7 -> u8
+    v129 = eq v128, u8 41
+    v130 = not v129
+    v131 = mul v126, v130
+    enable_side_effects v131
+    v132 = array_get v9, index u32 7 -> u8
+    v133 = lt v132, u8 41
+    v134 = mul v133, v131
+    constrain v134 == v131
+    v135 = not v131
+    v136 = mul v135, v124
+    v137 = unchecked_add v131, v136
+    v138 = mul v126, v129
+    enable_side_effects u1 1
+    v139 = not v137
+    enable_side_effects v139
+    v141 = array_get v9, index u32 8 -> u8
+    v142 = eq v141, u8 184
+    v143 = not v142
+    v144 = mul v139, v143
+    enable_side_effects v144
+    v145 = array_get v9, index u32 8 -> u8
+    v146 = lt v145, u8 184
+    v147 = mul v146, v144
+    constrain v147 == v144
+    v148 = not v144
+    v149 = mul v148, v137
+    v150 = unchecked_add v144, v149
+    v151 = mul v139, v142
+    enable_side_effects u1 1
+    v152 = not v150
+    enable_side_effects v152
+    v154 = array_get v9, index u32 9 -> u8
+    v155 = eq v154, u8 80
+    v156 = not v155
+    v157 = mul v152, v156
+    enable_side_effects v157
+    v158 = array_get v9, index u32 9 -> u8
+    v159 = lt v158, u8 80
+    v160 = mul v159, v157
+    constrain v160 == v157
+    v161 = not v157
+    v162 = mul v161, v150
+    v163 = unchecked_add v157, v162
+    v164 = mul v152, v155
+    enable_side_effects u1 1
+    v165 = not v163
+    enable_side_effects v165
+    v167 = array_get v9, index u32 10 -> u8
+    v168 = eq v167, u8 69
+    v169 = not v168
+    v170 = mul v165, v169
+    enable_side_effects v170
+    v171 = array_get v9, index u32 10 -> u8
+    v172 = lt v171, u8 69
+    v173 = mul v172, v170
+    constrain v173 == v170
+    v174 = not v170
+    v175 = mul v174, v163
+    v176 = unchecked_add v170, v175
+    v177 = mul v165, v168
+    enable_side_effects u1 1
+    v178 = not v176
+    enable_side_effects v178
+    v180 = array_get v9, index u32 11 -> u8
+    v181 = eq v180, u8 182
+    v182 = not v181
+    v183 = mul v178, v182
+    enable_side_effects v183
+    v184 = array_get v9, index u32 11 -> u8
+    v185 = lt v184, u8 182
+    v186 = mul v185, v183
+    constrain v186 == v183
+    v187 = not v183
+    v188 = mul v187, v176
+    v189 = unchecked_add v183, v188
+    v190 = mul v178, v181
+    enable_side_effects u1 1
+    v191 = not v189
+    enable_side_effects v191
+    v193 = array_get v9, index u32 12 -> u8
+    v194 = eq v193, u8 129
+    v195 = not v194
+    v196 = mul v191, v195
+    enable_side_effects v196
+    v197 = array_get v9, index u32 12 -> u8
+    v198 = lt v197, u8 129
+    v199 = mul v198, v196
+    constrain v199 == v196
+    v200 = not v196
+    v201 = mul v200, v189
+    v202 = unchecked_add v196, v201
+    v203 = mul v191, v194
+    enable_side_effects u1 1
+    v204 = not v202
+    enable_side_effects v204
+    v206 = array_get v9, index u32 13 -> u8
+    v207 = eq v206, u8 129
+    v208 = not v207
+    v209 = mul v204, v208
+    enable_side_effects v209
+    v210 = array_get v9, index u32 13 -> u8
+    v211 = lt v210, u8 129
+    v212 = mul v211, v209
+    constrain v212 == v209
+    v213 = not v209
+    v214 = mul v213, v202
+    v215 = unchecked_add v209, v214
+    v216 = mul v204, v207
+    enable_side_effects u1 1
+    v217 = not v215
+    enable_side_effects v217
+    v219 = array_get v9, index u32 14 -> u8
+    v220 = eq v219, u8 88
+    v221 = not v220
+    v222 = mul v217, v221
+    enable_side_effects v222
+    v223 = array_get v9, index u32 14 -> u8
+    v224 = lt v223, u8 88
+    v225 = mul v224, v222
+    constrain v225 == v222
+    v226 = not v222
+    v227 = mul v226, v215
+    v228 = unchecked_add v222, v227
+    v229 = mul v217, v220
+    enable_side_effects u1 1
+    v230 = not v228
+    enable_side_effects v230
+    v232 = array_get v9, index u32 15 -> u8
+    v233 = eq v232, u8 93
+    v234 = not v233
+    v235 = mul v230, v234
+    enable_side_effects v235
+    v236 = array_get v9, index u32 15 -> u8
+    v237 = lt v236, u8 93
+    v238 = mul v237, v235
+    constrain v238 == v235
+    v239 = not v235
+    v240 = mul v239, v228
+    v241 = unchecked_add v235, v240
+    v242 = mul v230, v233
+    enable_side_effects u1 1
+    v243 = not v241
+    enable_side_effects v243
+    v245 = array_get v9, index u32 16 -> u8
+    v246 = eq v245, u8 40
+    v247 = not v246
+    v248 = mul v243, v247
+    enable_side_effects v248
+    v249 = array_get v9, index u32 16 -> u8
+    v250 = lt v249, u8 40
+    v251 = mul v250, v248
+    constrain v251 == v248
+    v252 = not v248
+    v253 = mul v252, v241
+    v254 = unchecked_add v248, v253
+    v255 = mul v243, v246
+    enable_side_effects u1 1
+    v256 = not v254
+    enable_side_effects v256
+    v258 = array_get v9, index u32 17 -> u8
+    v259 = eq v258, u8 51
+    v260 = not v259
+    v261 = mul v256, v260
+    enable_side_effects v261
+    v262 = array_get v9, index u32 17 -> u8
+    v263 = lt v262, u8 51
+    v264 = mul v263, v261
+    constrain v264 == v261
+    v265 = not v261
+    v266 = mul v265, v254
+    v267 = unchecked_add v261, v266
+    v268 = mul v256, v259
+    enable_side_effects u1 1
+    v269 = not v267
+    enable_side_effects v269
+    v271 = array_get v9, index u32 18 -> u8
+    v272 = eq v271, u8 232
+    v273 = not v272
+    v274 = mul v269, v273
+    enable_side_effects v274
+    v275 = array_get v9, index u32 18 -> u8
+    v276 = lt v275, u8 232
+    v277 = mul v276, v274
+    constrain v277 == v274
+    v278 = not v274
+    v279 = mul v278, v267
+    v280 = unchecked_add v274, v279
+    v281 = mul v269, v272
+    enable_side_effects u1 1
+    v282 = not v280
+    enable_side_effects v282
+    v284 = array_get v9, index u32 19 -> u8
+    v285 = eq v284, u8 72
+    v286 = not v285
+    v287 = mul v282, v286
+    enable_side_effects v287
+    v288 = array_get v9, index u32 19 -> u8
+    v289 = lt v288, u8 72
+    v290 = mul v289, v287
+    constrain v290 == v287
+    v291 = not v287
+    v292 = mul v291, v280
+    v293 = unchecked_add v287, v292
+    v294 = mul v282, v285
+    enable_side_effects u1 1
+    v295 = not v293
+    enable_side_effects v295
+    v297 = array_get v9, index u32 20 -> u8
+    v298 = eq v297, u8 121
+    v299 = not v298
+    v300 = mul v295, v299
+    enable_side_effects v300
+    v301 = array_get v9, index u32 20 -> u8
+    v302 = lt v301, u8 121
+    v303 = mul v302, v300
+    constrain v303 == v300
+    v304 = not v300
+    v305 = mul v304, v293
+    v306 = unchecked_add v300, v305
+    v307 = mul v295, v298
+    enable_side_effects u1 1
+    v308 = not v306
+    enable_side_effects v308
+    v310 = array_get v9, index u32 21 -> u8
+    v311 = eq v310, u8 185
+    v312 = not v311
+    v313 = mul v308, v312
+    enable_side_effects v313
+    v314 = array_get v9, index u32 21 -> u8
+    v315 = lt v314, u8 185
+    v316 = mul v315, v313
+    constrain v316 == v313
+    v317 = not v313
+    v318 = mul v317, v306
+    v319 = unchecked_add v313, v318
+    v320 = mul v308, v311
+    enable_side_effects u1 1
+    v321 = not v319
+    enable_side_effects v321
+    v323 = array_get v9, index u32 22 -> u8
+    v324 = eq v323, u8 112
+    v325 = not v324
+    v326 = mul v321, v325
+    enable_side_effects v326
+    v327 = array_get v9, index u32 22 -> u8
+    v328 = lt v327, u8 112
+    v329 = mul v328, v326
+    constrain v329 == v326
+    v330 = not v326
+    v331 = mul v330, v319
+    v332 = unchecked_add v326, v331
+    v333 = mul v321, v324
+    enable_side_effects u1 1
+    v334 = not v332
+    enable_side_effects v334
+    v336 = array_get v9, index u32 23 -> u8
+    v337 = eq v336, u8 145
+    v338 = not v337
+    v339 = mul v334, v338
+    enable_side_effects v339
+    v340 = array_get v9, index u32 23 -> u8
+    v341 = lt v340, u8 145
+    v342 = mul v341, v339
+    constrain v342 == v339
+    v343 = not v339
+    v344 = mul v343, v332
+    v345 = unchecked_add v339, v344
+    v346 = mul v334, v337
+    enable_side_effects u1 1
+    v347 = not v345
+    enable_side_effects v347
+    v349 = array_get v9, index u32 24 -> u8
+    v350 = eq v349, u8 67
+    v351 = not v350
+    v352 = mul v347, v351
+    enable_side_effects v352
+    v353 = array_get v9, index u32 24 -> u8
+    v354 = lt v353, u8 67
+    v355 = mul v354, v352
+    constrain v355 == v352
+    v356 = not v352
+    v357 = mul v356, v345
+    v358 = unchecked_add v352, v357
+    v359 = mul v347, v350
+    enable_side_effects u1 1
+    v360 = not v358
+    enable_side_effects v360
+    v362 = array_get v9, index u32 25 -> u8
+    v363 = eq v362, u8 225
+    v364 = not v363
+    v365 = mul v360, v364
+    enable_side_effects v365
+    v366 = array_get v9, index u32 25 -> u8
+    v367 = lt v366, u8 225
+    v368 = mul v367, v365
+    constrain v368 == v365
+    v369 = not v365
+    v370 = mul v369, v358
+    v371 = unchecked_add v365, v370
+    v372 = mul v360, v363
+    enable_side_effects u1 1
+    v373 = not v371
+    enable_side_effects v373
+    v375 = array_get v9, index u32 26 -> u8
+    v376 = eq v375, u8 245
+    v377 = not v376
+    v378 = mul v373, v377
+    enable_side_effects v378
+    v379 = array_get v9, index u32 26 -> u8
+    v380 = lt v379, u8 245
+    v381 = mul v380, v378
+    constrain v381 == v378
+    v382 = not v378
+    v383 = mul v382, v371
+    v384 = unchecked_add v378, v383
+    v385 = mul v373, v376
+    enable_side_effects u1 1
+    v386 = not v384
+    enable_side_effects v386
+    v388 = array_get v9, index u32 27 -> u8
+    v389 = eq v388, u8 147
+    v390 = not v389
+    v391 = mul v386, v390
+    enable_side_effects v391
+    v392 = array_get v9, index u32 27 -> u8
+    v393 = lt v392, u8 147
+    v394 = mul v393, v391
+    constrain v394 == v391
+    v395 = not v391
+    v396 = mul v395, v384
+    v397 = unchecked_add v391, v396
+    v398 = mul v386, v389
+    enable_side_effects u1 1
+    v399 = not v397
+    enable_side_effects v399
+    v401 = array_get v9, index u32 28 -> u8
+    v402 = eq v401, u8 240
+    v403 = not v402
+    v404 = mul v399, v403
+    enable_side_effects v404
+    v405 = array_get v9, index u32 28 -> u8
+    v406 = lt v405, u8 240
+    v407 = mul v406, v404
+    constrain v407 == v404
+    v408 = not v404
+    v409 = mul v408, v397
+    v410 = unchecked_add v404, v409
+    v411 = mul v399, v402
+    enable_side_effects u1 1
+    v412 = not v410
+    enable_side_effects v412
+    v414 = array_get v9, index u32 29 -> u8
+    v415 = eq v414, u8 0
+    v416 = not v415
+    v417 = mul v412, v416
+    enable_side_effects v417
+    v418 = array_get v9, index u32 29 -> u8
+    constrain u1 0 == v417
+    v420 = not v417
+    v421 = mul v420, v410
+    v422 = unchecked_add v417, v421
+    v423 = mul v412, v415
+    enable_side_effects u1 1
+    v424 = not v422
+    enable_side_effects v424
+    v426 = array_get v9, index u32 30 -> u8
+    v427 = eq v426, u8 0
+    v428 = not v427
+    v429 = mul v424, v428
+    enable_side_effects v429
+    v430 = array_get v9, index u32 30 -> u8
+    constrain u1 0 == v429
+    v431 = not v429
+    v432 = mul v431, v422
+    v433 = unchecked_add v429, v432
+    v434 = mul v424, v427
+    enable_side_effects u1 1
+    v435 = not v433
+    enable_side_effects v435
+    v437 = array_get v9, index u32 31 -> u8
+    v438 = eq v437, u8 1
+    v439 = not v438
+    v440 = mul v435, v439
+    enable_side_effects v440
+    v441 = array_get v9, index u32 31 -> u8
+    v442 = eq v441, u8 0
+    v443 = cast v440 as u8
+    v444 = unchecked_mul v441, v443
+    constrain v444 == u8 0
+    v445 = not v440
+    v446 = mul v445, v433
+    v447 = unchecked_add v440, v446
+    v448 = mul v435, v438
+    enable_side_effects u1 1
+    constrain v447 == u1 1
+    v449 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v450 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v451 = allocate -> &mut u1
+    enable_side_effects u1 1
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    enable_side_effects u1 1
+    enable_side_effects u1 1
+    enable_side_effects u1 0
+    enable_side_effects u1 1
+    v452 = allocate -> &mut [u8; 32]
+    v453 = array_get v9, index u32 0 -> u8
+    v454 = make_array [v453, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v455 = array_get v9, index u32 1 -> u8
+    v456 = make_array [v453, v455, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v457 = array_get v9, index u32 2 -> u8
+    v458 = make_array [v453, v455, v457, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v459 = array_get v9, index u32 3 -> u8
+    v460 = make_array [v453, v455, v457, v459, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v461 = array_get v9, index u32 4 -> u8
+    v462 = make_array [v453, v455, v457, v459, v461, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v463 = array_get v9, index u32 5 -> u8
+    v464 = make_array [v453, v455, v457, v459, v461, v463, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v465 = array_get v9, index u32 6 -> u8
+    v466 = make_array [v453, v455, v457, v459, v461, v463, v465, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v467 = array_get v9, index u32 7 -> u8
+    v468 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v469 = array_get v9, index u32 8 -> u8
+    v470 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v471 = array_get v9, index u32 9 -> u8
+    v472 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v473 = array_get v9, index u32 10 -> u8
+    v474 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v475 = array_get v9, index u32 11 -> u8
+    v476 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v477 = array_get v9, index u32 12 -> u8
+    v478 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v479 = array_get v9, index u32 13 -> u8
+    v480 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v481 = array_get v9, index u32 14 -> u8
+    v482 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v483 = array_get v9, index u32 15 -> u8
+    v484 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v485 = array_get v9, index u32 16 -> u8
+    v486 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v487 = array_get v9, index u32 17 -> u8
+    v488 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v489 = array_get v9, index u32 18 -> u8
+    v490 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v491 = array_get v9, index u32 19 -> u8
+    v492 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v493 = array_get v9, index u32 20 -> u8
+    v494 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v495 = array_get v9, index u32 21 -> u8
+    v496 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v497 = array_get v9, index u32 22 -> u8
+    v498 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v499 = array_get v9, index u32 23 -> u8
+    v500 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v501 = array_get v9, index u32 24 -> u8
+    v502 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v503 = array_get v9, index u32 25 -> u8
+    v504 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v505 = array_get v9, index u32 26 -> u8
+    v506 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v507 = array_get v9, index u32 27 -> u8
+    v508 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v509 = array_get v9, index u32 28 -> u8
+    v510 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, u8 0, u8 0, u8 0] : [u8; 32]
+    v511 = array_get v9, index u32 29 -> u8
+    v512 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, u8 0, u8 0] : [u8; 32]
+    v513 = array_get v9, index u32 30 -> u8
+    v514 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, v513, u8 0] : [u8; 32]
+    v515 = array_get v9, index u32 31 -> u8
+    v516 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, v513, v515] : [u8; 32]
+    v517 = allocate -> &mut Field
+    v518 = allocate -> &mut Field
+    v519 = allocate -> &mut Field
+    v520 = cast v483 as Field
+    v521 = cast v515 as Field
+    v522 = cast v481 as Field
+    v524 = mul v522, Field 256
+    v525 = add v520, v524
+    v526 = cast v513 as Field
+    v527 = mul v526, Field 256
+    v528 = add v521, v527
+    v529 = cast v479 as Field
+    v531 = mul v529, Field 65536
+    v532 = add v525, v531
+    v533 = cast v511 as Field
+    v534 = mul v533, Field 65536
+    v535 = add v528, v534
+    v536 = cast v477 as Field
+    v538 = mul v536, Field 16777216
+    v539 = add v532, v538
+    v540 = cast v509 as Field
+    v541 = mul v540, Field 16777216
+    v542 = add v535, v541
+    v543 = cast v475 as Field
+    v545 = mul v543, Field 4294967296
+    v546 = add v539, v545
+    v547 = cast v507 as Field
+    v548 = mul v547, Field 4294967296
+    v549 = add v542, v548
+    v550 = cast v473 as Field
+    v552 = mul v550, Field 1099511627776
+    v553 = add v546, v552
+    v554 = cast v505 as Field
+    v555 = mul v554, Field 1099511627776
+    v556 = add v549, v555
+    v557 = cast v471 as Field
+    v559 = mul v557, Field 281474976710656
+    v560 = add v553, v559
+    v561 = cast v503 as Field
+    v562 = mul v561, Field 281474976710656
+    v563 = add v556, v562
+    v564 = cast v469 as Field
+    v566 = mul v564, Field 72057594037927936
+    v567 = add v560, v566
+    v568 = cast v501 as Field
+    v569 = mul v568, Field 72057594037927936
+    v570 = add v563, v569
+    v571 = cast v467 as Field
+    v573 = mul v571, Field 18446744073709551616
+    v574 = add v567, v573
+    v575 = cast v499 as Field
+    v576 = mul v575, Field 18446744073709551616
+    v577 = add v570, v576
+    v578 = cast v465 as Field
+    v580 = mul v578, Field 4722366482869645213696
+    v581 = add v574, v580
+    v582 = cast v497 as Field
+    v583 = mul v582, Field 4722366482869645213696
+    v584 = add v577, v583
+    v585 = cast v463 as Field
+    v587 = mul v585, Field 1208925819614629174706176
+    v588 = add v581, v587
+    v589 = cast v495 as Field
+    v590 = mul v589, Field 1208925819614629174706176
+    v591 = add v584, v590
+    v592 = cast v461 as Field
+    v594 = mul v592, Field 309485009821345068724781056
+    v595 = add v588, v594
+    v596 = cast v493 as Field
+    v597 = mul v596, Field 309485009821345068724781056
+    v598 = add v591, v597
+    v599 = cast v459 as Field
+    v601 = mul v599, Field 79228162514264337593543950336
+    v602 = add v595, v601
+    v603 = cast v491 as Field
+    v604 = mul v603, Field 79228162514264337593543950336
+    v605 = add v598, v604
+    v606 = cast v457 as Field
+    v608 = mul v606, Field 20282409603651670423947251286016
+    v609 = add v602, v608
+    v610 = cast v489 as Field
+    v611 = mul v610, Field 20282409603651670423947251286016
+    v612 = add v605, v611
+    v613 = cast v455 as Field
+    v615 = mul v613, Field 5192296858534827628530496329220096
+    v616 = add v609, v615
+    v617 = cast v487 as Field
+    v618 = mul v617, Field 5192296858534827628530496329220096
+    v619 = add v612, v618
+    v620 = cast v453 as Field
+    v622 = mul v620, Field 1329227995784915872903807060280344576
+    v623 = add v616, v622
+    v624 = cast v485 as Field
+    v625 = mul v624, Field 1329227995784915872903807060280344576
+    v626 = add v619, v625
+    v628 = mul v623, Field 340282366920938463463374607431768211456
+    v629 = add v626, v628
+    v630 = allocate -> &mut Field
+    v632 = eq v4, Field 0
+    enable_side_effects v632
+    v633 = not v632
+    enable_side_effects v633
+    v635 = call f1(v4, Field 0) -> u1
+    v636 = mul v633, v635
+    enable_side_effects v636
+    v638, v639 = call f3(Field 0) -> (Field, Field)
+    v640 = cast v636 as Field
+    v641 = mul v638, v640
+    range_check v641 to 128 bits
+    v642 = cast v636 as Field
+    v643 = mul v639, v642
+    range_check v643 to 128 bits
+    v644 = mul Field 340282366920938463463374607431768211456, v639
+    v645 = add v638, v644
+    v646 = eq Field 0, v645
+    v647 = cast v636 as Field
+    v648 = mul v645, v647
+    constrain Field 0 == v648
+    v651 = call f2(Field 53438638232309528389504892708671455233, v638) -> u1
+    v652 = sub Field 53438638232309528389504892708671455233, v638
+    v654 = sub v652, Field 1
+    v655 = cast v651 as Field
+    v656 = mul v655, Field 340282366920938463463374607431768211456
+    v657 = add v654, v656
+    v659 = sub Field 64323764613183177041862057485226039389, v639
+    v660 = cast v651 as Field
+    v661 = sub v659, v660
+    v662 = cast v636 as Field
+    v663 = mul v657, v662
+    range_check v663 to 128 bits
+    v664 = cast v636 as Field
+    v665 = mul v661, v664
+    range_check v665 to 128 bits
+    v667, v668 = call f3(v4) -> (Field, Field)
+    v669 = cast v636 as Field
+    v670 = mul v667, v669
+    range_check v670 to 128 bits
+    v671 = cast v636 as Field
+    v672 = mul v668, v671
+    range_check v672 to 128 bits
+    v673 = mul Field 340282366920938463463374607431768211456, v668
+    v674 = add v667, v673
+    v675 = eq v4, v674
+    v676 = cast v636 as Field
+    v677 = mul v4, v676
+    v678 = mul v674, v676
+    constrain v677 == v678
+    v680 = call f2(Field 53438638232309528389504892708671455233, v667) -> u1
+    v681 = sub Field 53438638232309528389504892708671455233, v667
+    v682 = sub v681, Field 1
+    v683 = cast v680 as Field
+    v684 = mul v683, Field 340282366920938463463374607431768211456
+    v685 = add v682, v684
+    v686 = sub Field 64323764613183177041862057485226039389, v668
+    v687 = cast v680 as Field
+    v688 = sub v686, v687
+    v689 = cast v636 as Field
+    v690 = mul v685, v689
+    range_check v690 to 128 bits
+    v691 = cast v636 as Field
+    v692 = mul v688, v691
+    range_check v692 to 128 bits
+    v694 = call f2(v638, v667) -> u1
+    v695 = sub v638, v667
+    v696 = sub v695, Field 1
+    v697 = cast v694 as Field
+    v698 = mul v697, Field 340282366920938463463374607431768211456
+    v699 = add v696, v698
+    v700 = sub v639, v668
+    v701 = cast v694 as Field
+    v702 = sub v700, v701
+    v703 = cast v636 as Field
+    v704 = mul v699, v703
+    range_check v704 to 128 bits
+    v705 = cast v636 as Field
+    v706 = mul v702, v705
+    range_check v706 to 128 bits
+    v707 = not v635
+    v708 = mul v633, v707
+    enable_side_effects v708
+    v710, v711 = call f3(v4) -> (Field, Field)
+    v712 = cast v708 as Field
+    v713 = mul v710, v712
+    range_check v713 to 128 bits
+    v714 = cast v708 as Field
+    v715 = mul v711, v714
+    range_check v715 to 128 bits
+    v716 = mul Field 340282366920938463463374607431768211456, v711
+    v717 = add v710, v716
+    v718 = eq v4, v717
+    v719 = cast v708 as Field
+    v720 = mul v4, v719
+    v721 = mul v717, v719
+    constrain v720 == v721
+    v723 = call f2(Field 53438638232309528389504892708671455233, v710) -> u1
+    v724 = sub Field 53438638232309528389504892708671455233, v710
+    v725 = sub v724, Field 1
+    v726 = cast v723 as Field
+    v727 = mul v726, Field 340282366920938463463374607431768211456
+    v728 = add v725, v727
+    v729 = sub Field 64323764613183177041862057485226039389, v711
+    v730 = cast v723 as Field
+    v731 = sub v729, v730
+    v732 = cast v708 as Field
+    v733 = mul v728, v732
+    range_check v733 to 128 bits
+    v734 = cast v708 as Field
+    v735 = mul v731, v734
+    range_check v735 to 128 bits
+    v737, v738 = call f3(Field 0) -> (Field, Field)
+    v739 = cast v708 as Field
+    v740 = mul v737, v739
+    range_check v740 to 128 bits
+    v741 = cast v708 as Field
+    v742 = mul v738, v741
+    range_check v742 to 128 bits
+    v743 = mul Field 340282366920938463463374607431768211456, v738
+    v744 = add v737, v743
+    v745 = eq Field 0, v744
+    v746 = cast v708 as Field
+    v747 = mul v744, v746
+    constrain Field 0 == v747
+    v749 = call f2(Field 53438638232309528389504892708671455233, v737) -> u1
+    v750 = sub Field 53438638232309528389504892708671455233, v737
+    v751 = sub v750, Field 1
+    v752 = cast v749 as Field
+    v753 = mul v752, Field 340282366920938463463374607431768211456
+    v754 = add v751, v753
+    v755 = sub Field 64323764613183177041862057485226039389, v738
+    v756 = cast v749 as Field
+    v757 = sub v755, v756
+    v758 = cast v708 as Field
+    v759 = mul v754, v758
+    range_check v759 to 128 bits
+    v760 = cast v708 as Field
+    v761 = mul v757, v760
+    range_check v761 to 128 bits
+    v763 = call f2(v710, v737) -> u1
+    v764 = sub v710, v737
+    v765 = sub v764, Field 1
+    v766 = cast v763 as Field
+    v767 = mul v766, Field 340282366920938463463374607431768211456
+    v768 = add v765, v767
+    v769 = sub v711, v738
+    v770 = cast v763 as Field
+    v771 = sub v769, v770
+    v772 = cast v708 as Field
+    v773 = mul v768, v772
+    range_check v773 to 128 bits
+    v774 = cast v708 as Field
+    v775 = mul v771, v774
+    range_check v775 to 128 bits
+    enable_side_effects v708
+    v776 = not v708
+    v777 = cast v708 as Field
+    v778 = cast v776 as Field
+    enable_side_effects u1 1
+    v779 = sub v777, v629
+    return v779
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Inlining (2nd):
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = allocate -> &mut Field
+    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v40 = allocate -> &mut u1
+    enable_side_effects u1 1
+    v43 = array_get v9, index u32 0 -> u8
+    v44 = eq v43, u8 48
+    v45 = not v44
+    enable_side_effects v45
+    v46 = array_get v9, index u32 0 -> u8
+    v47 = lt v46, u8 48
+    v48 = mul v47, v45
+    constrain v48 == v45
+    enable_side_effects v44
+    v50 = array_get v9, index u32 1 -> u8
+    v51 = eq v50, u8 100
+    v52 = not v51
+    v53 = mul v44, v52
+    enable_side_effects v53
+    v54 = array_get v9, index u32 1 -> u8
+    v55 = lt v54, u8 100
+    v56 = mul v55, v53
+    constrain v56 == v53
+    v57 = not v53
+    v58 = mul v57, v45
+    v59 = unchecked_add v53, v58
+    v60 = mul v44, v51
+    enable_side_effects u1 1
+    v61 = not v59
+    enable_side_effects v61
+    v63 = array_get v9, index u32 2 -> u8
+    v64 = eq v63, u8 78
+    v65 = not v64
+    v66 = mul v61, v65
+    enable_side_effects v66
+    v67 = array_get v9, index u32 2 -> u8
+    v68 = lt v67, u8 78
+    v69 = mul v68, v66
+    constrain v69 == v66
+    v70 = not v66
+    v71 = mul v70, v59
+    v72 = unchecked_add v66, v71
+    v73 = mul v61, v64
+    enable_side_effects u1 1
+    v74 = not v72
+    enable_side_effects v74
+    v76 = array_get v9, index u32 3 -> u8
+    v77 = eq v76, u8 114
+    v78 = not v77
+    v79 = mul v74, v78
+    enable_side_effects v79
+    v80 = array_get v9, index u32 3 -> u8
+    v81 = lt v80, u8 114
+    v82 = mul v81, v79
+    constrain v82 == v79
+    v83 = not v79
+    v84 = mul v83, v72
+    v85 = unchecked_add v79, v84
+    v86 = mul v74, v77
+    enable_side_effects u1 1
+    v87 = not v85
+    enable_side_effects v87
+    v89 = array_get v9, index u32 4 -> u8
+    v90 = eq v89, u8 225
+    v91 = not v90
+    v92 = mul v87, v91
+    enable_side_effects v92
+    v93 = array_get v9, index u32 4 -> u8
+    v94 = lt v93, u8 225
+    v95 = mul v94, v92
+    constrain v95 == v92
+    v96 = not v92
+    v97 = mul v96, v85
+    v98 = unchecked_add v92, v97
+    v99 = mul v87, v90
+    enable_side_effects u1 1
+    v100 = not v98
+    enable_side_effects v100
+    v102 = array_get v9, index u32 5 -> u8
+    v103 = eq v102, u8 49
+    v104 = not v103
+    v105 = mul v100, v104
+    enable_side_effects v105
+    v106 = array_get v9, index u32 5 -> u8
+    v107 = lt v106, u8 49
+    v108 = mul v107, v105
+    constrain v108 == v105
+    v109 = not v105
+    v110 = mul v109, v98
+    v111 = unchecked_add v105, v110
+    v112 = mul v100, v103
+    enable_side_effects u1 1
+    v113 = not v111
+    enable_side_effects v113
+    v115 = array_get v9, index u32 6 -> u8
+    v116 = eq v115, u8 160
+    v117 = not v116
+    v118 = mul v113, v117
+    enable_side_effects v118
+    v119 = array_get v9, index u32 6 -> u8
+    v120 = lt v119, u8 160
+    v121 = mul v120, v118
+    constrain v121 == v118
+    v122 = not v118
+    v123 = mul v122, v111
+    v124 = unchecked_add v118, v123
+    v125 = mul v113, v116
+    enable_side_effects u1 1
+    v126 = not v124
+    enable_side_effects v126
+    v128 = array_get v9, index u32 7 -> u8
+    v129 = eq v128, u8 41
+    v130 = not v129
+    v131 = mul v126, v130
+    enable_side_effects v131
+    v132 = array_get v9, index u32 7 -> u8
+    v133 = lt v132, u8 41
+    v134 = mul v133, v131
+    constrain v134 == v131
+    v135 = not v131
+    v136 = mul v135, v124
+    v137 = unchecked_add v131, v136
+    v138 = mul v126, v129
+    enable_side_effects u1 1
+    v139 = not v137
+    enable_side_effects v139
+    v141 = array_get v9, index u32 8 -> u8
+    v142 = eq v141, u8 184
+    v143 = not v142
+    v144 = mul v139, v143
+    enable_side_effects v144
+    v145 = array_get v9, index u32 8 -> u8
+    v146 = lt v145, u8 184
+    v147 = mul v146, v144
+    constrain v147 == v144
+    v148 = not v144
+    v149 = mul v148, v137
+    v150 = unchecked_add v144, v149
+    v151 = mul v139, v142
+    enable_side_effects u1 1
+    v152 = not v150
+    enable_side_effects v152
+    v154 = array_get v9, index u32 9 -> u8
+    v155 = eq v154, u8 80
+    v156 = not v155
+    v157 = mul v152, v156
+    enable_side_effects v157
+    v158 = array_get v9, index u32 9 -> u8
+    v159 = lt v158, u8 80
+    v160 = mul v159, v157
+    constrain v160 == v157
+    v161 = not v157
+    v162 = mul v161, v150
+    v163 = unchecked_add v157, v162
+    v164 = mul v152, v155
+    enable_side_effects u1 1
+    v165 = not v163
+    enable_side_effects v165
+    v167 = array_get v9, index u32 10 -> u8
+    v168 = eq v167, u8 69
+    v169 = not v168
+    v170 = mul v165, v169
+    enable_side_effects v170
+    v171 = array_get v9, index u32 10 -> u8
+    v172 = lt v171, u8 69
+    v173 = mul v172, v170
+    constrain v173 == v170
+    v174 = not v170
+    v175 = mul v174, v163
+    v176 = unchecked_add v170, v175
+    v177 = mul v165, v168
+    enable_side_effects u1 1
+    v178 = not v176
+    enable_side_effects v178
+    v180 = array_get v9, index u32 11 -> u8
+    v181 = eq v180, u8 182
+    v182 = not v181
+    v183 = mul v178, v182
+    enable_side_effects v183
+    v184 = array_get v9, index u32 11 -> u8
+    v185 = lt v184, u8 182
+    v186 = mul v185, v183
+    constrain v186 == v183
+    v187 = not v183
+    v188 = mul v187, v176
+    v189 = unchecked_add v183, v188
+    v190 = mul v178, v181
+    enable_side_effects u1 1
+    v191 = not v189
+    enable_side_effects v191
+    v193 = array_get v9, index u32 12 -> u8
+    v194 = eq v193, u8 129
+    v195 = not v194
+    v196 = mul v191, v195
+    enable_side_effects v196
+    v197 = array_get v9, index u32 12 -> u8
+    v198 = lt v197, u8 129
+    v199 = mul v198, v196
+    constrain v199 == v196
+    v200 = not v196
+    v201 = mul v200, v189
+    v202 = unchecked_add v196, v201
+    v203 = mul v191, v194
+    enable_side_effects u1 1
+    v204 = not v202
+    enable_side_effects v204
+    v206 = array_get v9, index u32 13 -> u8
+    v207 = eq v206, u8 129
+    v208 = not v207
+    v209 = mul v204, v208
+    enable_side_effects v209
+    v210 = array_get v9, index u32 13 -> u8
+    v211 = lt v210, u8 129
+    v212 = mul v211, v209
+    constrain v212 == v209
+    v213 = not v209
+    v214 = mul v213, v202
+    v215 = unchecked_add v209, v214
+    v216 = mul v204, v207
+    enable_side_effects u1 1
+    v217 = not v215
+    enable_side_effects v217
+    v219 = array_get v9, index u32 14 -> u8
+    v220 = eq v219, u8 88
+    v221 = not v220
+    v222 = mul v217, v221
+    enable_side_effects v222
+    v223 = array_get v9, index u32 14 -> u8
+    v224 = lt v223, u8 88
+    v225 = mul v224, v222
+    constrain v225 == v222
+    v226 = not v222
+    v227 = mul v226, v215
+    v228 = unchecked_add v222, v227
+    v229 = mul v217, v220
+    enable_side_effects u1 1
+    v230 = not v228
+    enable_side_effects v230
+    v232 = array_get v9, index u32 15 -> u8
+    v233 = eq v232, u8 93
+    v234 = not v233
+    v235 = mul v230, v234
+    enable_side_effects v235
+    v236 = array_get v9, index u32 15 -> u8
+    v237 = lt v236, u8 93
+    v238 = mul v237, v235
+    constrain v238 == v235
+    v239 = not v235
+    v240 = mul v239, v228
+    v241 = unchecked_add v235, v240
+    v242 = mul v230, v233
+    enable_side_effects u1 1
+    v243 = not v241
+    enable_side_effects v243
+    v245 = array_get v9, index u32 16 -> u8
+    v246 = eq v245, u8 40
+    v247 = not v246
+    v248 = mul v243, v247
+    enable_side_effects v248
+    v249 = array_get v9, index u32 16 -> u8
+    v250 = lt v249, u8 40
+    v251 = mul v250, v248
+    constrain v251 == v248
+    v252 = not v248
+    v253 = mul v252, v241
+    v254 = unchecked_add v248, v253
+    v255 = mul v243, v246
+    enable_side_effects u1 1
+    v256 = not v254
+    enable_side_effects v256
+    v258 = array_get v9, index u32 17 -> u8
+    v259 = eq v258, u8 51
+    v260 = not v259
+    v261 = mul v256, v260
+    enable_side_effects v261
+    v262 = array_get v9, index u32 17 -> u8
+    v263 = lt v262, u8 51
+    v264 = mul v263, v261
+    constrain v264 == v261
+    v265 = not v261
+    v266 = mul v265, v254
+    v267 = unchecked_add v261, v266
+    v268 = mul v256, v259
+    enable_side_effects u1 1
+    v269 = not v267
+    enable_side_effects v269
+    v271 = array_get v9, index u32 18 -> u8
+    v272 = eq v271, u8 232
+    v273 = not v272
+    v274 = mul v269, v273
+    enable_side_effects v274
+    v275 = array_get v9, index u32 18 -> u8
+    v276 = lt v275, u8 232
+    v277 = mul v276, v274
+    constrain v277 == v274
+    v278 = not v274
+    v279 = mul v278, v267
+    v280 = unchecked_add v274, v279
+    v281 = mul v269, v272
+    enable_side_effects u1 1
+    v282 = not v280
+    enable_side_effects v282
+    v284 = array_get v9, index u32 19 -> u8
+    v285 = eq v284, u8 72
+    v286 = not v285
+    v287 = mul v282, v286
+    enable_side_effects v287
+    v288 = array_get v9, index u32 19 -> u8
+    v289 = lt v288, u8 72
+    v290 = mul v289, v287
+    constrain v290 == v287
+    v291 = not v287
+    v292 = mul v291, v280
+    v293 = unchecked_add v287, v292
+    v294 = mul v282, v285
+    enable_side_effects u1 1
+    v295 = not v293
+    enable_side_effects v295
+    v297 = array_get v9, index u32 20 -> u8
+    v298 = eq v297, u8 121
+    v299 = not v298
+    v300 = mul v295, v299
+    enable_side_effects v300
+    v301 = array_get v9, index u32 20 -> u8
+    v302 = lt v301, u8 121
+    v303 = mul v302, v300
+    constrain v303 == v300
+    v304 = not v300
+    v305 = mul v304, v293
+    v306 = unchecked_add v300, v305
+    v307 = mul v295, v298
+    enable_side_effects u1 1
+    v308 = not v306
+    enable_side_effects v308
+    v310 = array_get v9, index u32 21 -> u8
+    v311 = eq v310, u8 185
+    v312 = not v311
+    v313 = mul v308, v312
+    enable_side_effects v313
+    v314 = array_get v9, index u32 21 -> u8
+    v315 = lt v314, u8 185
+    v316 = mul v315, v313
+    constrain v316 == v313
+    v317 = not v313
+    v318 = mul v317, v306
+    v319 = unchecked_add v313, v318
+    v320 = mul v308, v311
+    enable_side_effects u1 1
+    v321 = not v319
+    enable_side_effects v321
+    v323 = array_get v9, index u32 22 -> u8
+    v324 = eq v323, u8 112
+    v325 = not v324
+    v326 = mul v321, v325
+    enable_side_effects v326
+    v327 = array_get v9, index u32 22 -> u8
+    v328 = lt v327, u8 112
+    v329 = mul v328, v326
+    constrain v329 == v326
+    v330 = not v326
+    v331 = mul v330, v319
+    v332 = unchecked_add v326, v331
+    v333 = mul v321, v324
+    enable_side_effects u1 1
+    v334 = not v332
+    enable_side_effects v334
+    v336 = array_get v9, index u32 23 -> u8
+    v337 = eq v336, u8 145
+    v338 = not v337
+    v339 = mul v334, v338
+    enable_side_effects v339
+    v340 = array_get v9, index u32 23 -> u8
+    v341 = lt v340, u8 145
+    v342 = mul v341, v339
+    constrain v342 == v339
+    v343 = not v339
+    v344 = mul v343, v332
+    v345 = unchecked_add v339, v344
+    v346 = mul v334, v337
+    enable_side_effects u1 1
+    v347 = not v345
+    enable_side_effects v347
+    v349 = array_get v9, index u32 24 -> u8
+    v350 = eq v349, u8 67
+    v351 = not v350
+    v352 = mul v347, v351
+    enable_side_effects v352
+    v353 = array_get v9, index u32 24 -> u8
+    v354 = lt v353, u8 67
+    v355 = mul v354, v352
+    constrain v355 == v352
+    v356 = not v352
+    v357 = mul v356, v345
+    v358 = unchecked_add v352, v357
+    v359 = mul v347, v350
+    enable_side_effects u1 1
+    v360 = not v358
+    enable_side_effects v360
+    v362 = array_get v9, index u32 25 -> u8
+    v363 = eq v362, u8 225
+    v364 = not v363
+    v365 = mul v360, v364
+    enable_side_effects v365
+    v366 = array_get v9, index u32 25 -> u8
+    v367 = lt v366, u8 225
+    v368 = mul v367, v365
+    constrain v368 == v365
+    v369 = not v365
+    v370 = mul v369, v358
+    v371 = unchecked_add v365, v370
+    v372 = mul v360, v363
+    enable_side_effects u1 1
+    v373 = not v371
+    enable_side_effects v373
+    v375 = array_get v9, index u32 26 -> u8
+    v376 = eq v375, u8 245
+    v377 = not v376
+    v378 = mul v373, v377
+    enable_side_effects v378
+    v379 = array_get v9, index u32 26 -> u8
+    v380 = lt v379, u8 245
+    v381 = mul v380, v378
+    constrain v381 == v378
+    v382 = not v378
+    v383 = mul v382, v371
+    v384 = unchecked_add v378, v383
+    v385 = mul v373, v376
+    enable_side_effects u1 1
+    v386 = not v384
+    enable_side_effects v386
+    v388 = array_get v9, index u32 27 -> u8
+    v389 = eq v388, u8 147
+    v390 = not v389
+    v391 = mul v386, v390
+    enable_side_effects v391
+    v392 = array_get v9, index u32 27 -> u8
+    v393 = lt v392, u8 147
+    v394 = mul v393, v391
+    constrain v394 == v391
+    v395 = not v391
+    v396 = mul v395, v384
+    v397 = unchecked_add v391, v396
+    v398 = mul v386, v389
+    enable_side_effects u1 1
+    v399 = not v397
+    enable_side_effects v399
+    v401 = array_get v9, index u32 28 -> u8
+    v402 = eq v401, u8 240
+    v403 = not v402
+    v404 = mul v399, v403
+    enable_side_effects v404
+    v405 = array_get v9, index u32 28 -> u8
+    v406 = lt v405, u8 240
+    v407 = mul v406, v404
+    constrain v407 == v404
+    v408 = not v404
+    v409 = mul v408, v397
+    v410 = unchecked_add v404, v409
+    v411 = mul v399, v402
+    enable_side_effects u1 1
+    v412 = not v410
+    enable_side_effects v412
+    v414 = array_get v9, index u32 29 -> u8
+    v415 = eq v414, u8 0
+    v416 = not v415
+    v417 = mul v412, v416
+    enable_side_effects v417
+    v418 = array_get v9, index u32 29 -> u8
+    constrain u1 0 == v417
+    v420 = not v417
+    v421 = mul v420, v410
+    v422 = unchecked_add v417, v421
+    v423 = mul v412, v415
+    enable_side_effects u1 1
+    v424 = not v422
+    enable_side_effects v424
+    v426 = array_get v9, index u32 30 -> u8
+    v427 = eq v426, u8 0
+    v428 = not v427
+    v429 = mul v424, v428
+    enable_side_effects v429
+    v430 = array_get v9, index u32 30 -> u8
+    constrain u1 0 == v429
+    v431 = not v429
+    v432 = mul v431, v422
+    v433 = unchecked_add v429, v432
+    v434 = mul v424, v427
+    enable_side_effects u1 1
+    v435 = not v433
+    enable_side_effects v435
+    v437 = array_get v9, index u32 31 -> u8
+    v438 = eq v437, u8 1
+    v439 = not v438
+    v440 = mul v435, v439
+    enable_side_effects v440
+    v441 = array_get v9, index u32 31 -> u8
+    v442 = eq v441, u8 0
+    v443 = cast v440 as u8
+    v444 = unchecked_mul v441, v443
+    constrain v444 == u8 0
+    v445 = not v440
+    v446 = mul v445, v433
+    v447 = unchecked_add v440, v446
+    v448 = mul v435, v438
+    enable_side_effects u1 1
+    constrain v447 == u1 1
+    v449 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v450 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v451 = allocate -> &mut u1
+    enable_side_effects u1 1
+    v452 = allocate -> &mut [u8; 32]
+    v453 = array_get v9, index u32 0 -> u8
+    v454 = make_array [v453, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v455 = array_get v9, index u32 1 -> u8
+    v456 = make_array [v453, v455, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v457 = array_get v9, index u32 2 -> u8
+    v458 = make_array [v453, v455, v457, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v459 = array_get v9, index u32 3 -> u8
+    v460 = make_array [v453, v455, v457, v459, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v461 = array_get v9, index u32 4 -> u8
+    v462 = make_array [v453, v455, v457, v459, v461, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v463 = array_get v9, index u32 5 -> u8
+    v464 = make_array [v453, v455, v457, v459, v461, v463, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v465 = array_get v9, index u32 6 -> u8
+    v466 = make_array [v453, v455, v457, v459, v461, v463, v465, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v467 = array_get v9, index u32 7 -> u8
+    v468 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v469 = array_get v9, index u32 8 -> u8
+    v470 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v471 = array_get v9, index u32 9 -> u8
+    v472 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v473 = array_get v9, index u32 10 -> u8
+    v474 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v475 = array_get v9, index u32 11 -> u8
+    v476 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v477 = array_get v9, index u32 12 -> u8
+    v478 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v479 = array_get v9, index u32 13 -> u8
+    v480 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v481 = array_get v9, index u32 14 -> u8
+    v482 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v483 = array_get v9, index u32 15 -> u8
+    v484 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v485 = array_get v9, index u32 16 -> u8
+    v486 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v487 = array_get v9, index u32 17 -> u8
+    v488 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v489 = array_get v9, index u32 18 -> u8
+    v490 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v491 = array_get v9, index u32 19 -> u8
+    v492 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v493 = array_get v9, index u32 20 -> u8
+    v494 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v495 = array_get v9, index u32 21 -> u8
+    v496 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v497 = array_get v9, index u32 22 -> u8
+    v498 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v499 = array_get v9, index u32 23 -> u8
+    v500 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v501 = array_get v9, index u32 24 -> u8
+    v502 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v503 = array_get v9, index u32 25 -> u8
+    v504 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v505 = array_get v9, index u32 26 -> u8
+    v506 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v507 = array_get v9, index u32 27 -> u8
+    v508 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v509 = array_get v9, index u32 28 -> u8
+    v510 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, u8 0, u8 0, u8 0] : [u8; 32]
+    v511 = array_get v9, index u32 29 -> u8
+    v512 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, u8 0, u8 0] : [u8; 32]
+    v513 = array_get v9, index u32 30 -> u8
+    v514 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, v513, u8 0] : [u8; 32]
+    v515 = array_get v9, index u32 31 -> u8
+    v516 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, v513, v515] : [u8; 32]
+    v517 = allocate -> &mut Field
+    v518 = allocate -> &mut Field
+    v519 = allocate -> &mut Field
+    v520 = cast v483 as Field
+    v521 = cast v515 as Field
+    v522 = cast v481 as Field
+    v524 = mul v522, Field 256
+    v525 = add v520, v524
+    v526 = cast v513 as Field
+    v527 = mul v526, Field 256
+    v528 = add v521, v527
+    v529 = cast v479 as Field
+    v531 = mul v529, Field 65536
+    v532 = add v525, v531
+    v533 = cast v511 as Field
+    v534 = mul v533, Field 65536
+    v535 = add v528, v534
+    v536 = cast v477 as Field
+    v538 = mul v536, Field 16777216
+    v539 = add v532, v538
+    v540 = cast v509 as Field
+    v541 = mul v540, Field 16777216
+    v542 = add v535, v541
+    v543 = cast v475 as Field
+    v545 = mul v543, Field 4294967296
+    v546 = add v539, v545
+    v547 = cast v507 as Field
+    v548 = mul v547, Field 4294967296
+    v549 = add v542, v548
+    v550 = cast v473 as Field
+    v552 = mul v550, Field 1099511627776
+    v553 = add v546, v552
+    v554 = cast v505 as Field
+    v555 = mul v554, Field 1099511627776
+    v556 = add v549, v555
+    v557 = cast v471 as Field
+    v559 = mul v557, Field 281474976710656
+    v560 = add v553, v559
+    v561 = cast v503 as Field
+    v562 = mul v561, Field 281474976710656
+    v563 = add v556, v562
+    v564 = cast v469 as Field
+    v566 = mul v564, Field 72057594037927936
+    v567 = add v560, v566
+    v568 = cast v501 as Field
+    v569 = mul v568, Field 72057594037927936
+    v570 = add v563, v569
+    v571 = cast v467 as Field
+    v573 = mul v571, Field 18446744073709551616
+    v574 = add v567, v573
+    v575 = cast v499 as Field
+    v576 = mul v575, Field 18446744073709551616
+    v577 = add v570, v576
+    v578 = cast v465 as Field
+    v580 = mul v578, Field 4722366482869645213696
+    v581 = add v574, v580
+    v582 = cast v497 as Field
+    v583 = mul v582, Field 4722366482869645213696
+    v584 = add v577, v583
+    v585 = cast v463 as Field
+    v587 = mul v585, Field 1208925819614629174706176
+    v588 = add v581, v587
+    v589 = cast v495 as Field
+    v590 = mul v589, Field 1208925819614629174706176
+    v591 = add v584, v590
+    v592 = cast v461 as Field
+    v594 = mul v592, Field 309485009821345068724781056
+    v595 = add v588, v594
+    v596 = cast v493 as Field
+    v597 = mul v596, Field 309485009821345068724781056
+    v598 = add v591, v597
+    v599 = cast v459 as Field
+    v601 = mul v599, Field 79228162514264337593543950336
+    v602 = add v595, v601
+    v603 = cast v491 as Field
+    v604 = mul v603, Field 79228162514264337593543950336
+    v605 = add v598, v604
+    v606 = cast v457 as Field
+    v608 = mul v606, Field 20282409603651670423947251286016
+    v609 = add v602, v608
+    v610 = cast v489 as Field
+    v611 = mul v610, Field 20282409603651670423947251286016
+    v612 = add v605, v611
+    v613 = cast v455 as Field
+    v615 = mul v613, Field 5192296858534827628530496329220096
+    v616 = add v609, v615
+    v617 = cast v487 as Field
+    v618 = mul v617, Field 5192296858534827628530496329220096
+    v619 = add v612, v618
+    v620 = cast v453 as Field
+    v622 = mul v620, Field 1329227995784915872903807060280344576
+    v623 = add v616, v622
+    v624 = cast v485 as Field
+    v625 = mul v624, Field 1329227995784915872903807060280344576
+    v626 = add v619, v625
+    v628 = mul v623, Field 340282366920938463463374607431768211456
+    v629 = add v626, v628
+    v630 = allocate -> &mut Field
+    v632 = eq v4, Field 0
+    enable_side_effects v632
+    v633 = not v632
+    enable_side_effects v633
+    v635 = call f1(v4, Field 0) -> u1
+    v636 = mul v633, v635
+    enable_side_effects v636
+    v638, v639 = call f3(Field 0) -> (Field, Field)
+    v640 = cast v636 as Field
+    v641 = mul v638, v640
+    range_check v641 to 128 bits
+    v642 = cast v636 as Field
+    v643 = mul v639, v642
+    range_check v643 to 128 bits
+    v644 = mul Field 340282366920938463463374607431768211456, v639
+    v645 = add v638, v644
+    v646 = eq Field 0, v645
+    v647 = cast v636 as Field
+    v648 = mul v645, v647
+    constrain Field 0 == v648
+    v651 = call f2(Field 53438638232309528389504892708671455233, v638) -> u1
+    v652 = sub Field 53438638232309528389504892708671455233, v638
+    v654 = sub v652, Field 1
+    v655 = cast v651 as Field
+    v656 = mul v655, Field 340282366920938463463374607431768211456
+    v657 = add v654, v656
+    v659 = sub Field 64323764613183177041862057485226039389, v639
+    v660 = cast v651 as Field
+    v661 = sub v659, v660
+    v662 = cast v636 as Field
+    v663 = mul v657, v662
+    range_check v663 to 128 bits
+    v664 = cast v636 as Field
+    v665 = mul v661, v664
+    range_check v665 to 128 bits
+    v667, v668 = call f3(v4) -> (Field, Field)
+    v669 = cast v636 as Field
+    v670 = mul v667, v669
+    range_check v670 to 128 bits
+    v671 = cast v636 as Field
+    v672 = mul v668, v671
+    range_check v672 to 128 bits
+    v673 = mul Field 340282366920938463463374607431768211456, v668
+    v674 = add v667, v673
+    v675 = eq v4, v674
+    v676 = cast v636 as Field
+    v677 = mul v4, v676
+    v678 = mul v674, v676
+    constrain v677 == v678
+    v680 = call f2(Field 53438638232309528389504892708671455233, v667) -> u1
+    v681 = sub Field 53438638232309528389504892708671455233, v667
+    v682 = sub v681, Field 1
+    v683 = cast v680 as Field
+    v684 = mul v683, Field 340282366920938463463374607431768211456
+    v685 = add v682, v684
+    v686 = sub Field 64323764613183177041862057485226039389, v668
+    v687 = cast v680 as Field
+    v688 = sub v686, v687
+    v689 = cast v636 as Field
+    v690 = mul v685, v689
+    range_check v690 to 128 bits
+    v691 = cast v636 as Field
+    v692 = mul v688, v691
+    range_check v692 to 128 bits
+    v694 = call f2(v638, v667) -> u1
+    v695 = sub v638, v667
+    v696 = sub v695, Field 1
+    v697 = cast v694 as Field
+    v698 = mul v697, Field 340282366920938463463374607431768211456
+    v699 = add v696, v698
+    v700 = sub v639, v668
+    v701 = cast v694 as Field
+    v702 = sub v700, v701
+    v703 = cast v636 as Field
+    v704 = mul v699, v703
+    range_check v704 to 128 bits
+    v705 = cast v636 as Field
+    v706 = mul v702, v705
+    range_check v706 to 128 bits
+    v707 = not v635
+    v708 = mul v633, v707
+    enable_side_effects v708
+    v710, v711 = call f3(v4) -> (Field, Field)
+    v712 = cast v708 as Field
+    v713 = mul v710, v712
+    range_check v713 to 128 bits
+    v714 = cast v708 as Field
+    v715 = mul v711, v714
+    range_check v715 to 128 bits
+    v716 = mul Field 340282366920938463463374607431768211456, v711
+    v717 = add v710, v716
+    v718 = eq v4, v717
+    v719 = cast v708 as Field
+    v720 = mul v4, v719
+    v721 = mul v717, v719
+    constrain v720 == v721
+    v723 = call f2(Field 53438638232309528389504892708671455233, v710) -> u1
+    v724 = sub Field 53438638232309528389504892708671455233, v710
+    v725 = sub v724, Field 1
+    v726 = cast v723 as Field
+    v727 = mul v726, Field 340282366920938463463374607431768211456
+    v728 = add v725, v727
+    v729 = sub Field 64323764613183177041862057485226039389, v711
+    v730 = cast v723 as Field
+    v731 = sub v729, v730
+    v732 = cast v708 as Field
+    v733 = mul v728, v732
+    range_check v733 to 128 bits
+    v734 = cast v708 as Field
+    v735 = mul v731, v734
+    range_check v735 to 128 bits
+    v737, v738 = call f3(Field 0) -> (Field, Field)
+    v739 = cast v708 as Field
+    v740 = mul v737, v739
+    range_check v740 to 128 bits
+    v741 = cast v708 as Field
+    v742 = mul v738, v741
+    range_check v742 to 128 bits
+    v743 = mul Field 340282366920938463463374607431768211456, v738
+    v744 = add v737, v743
+    v745 = eq Field 0, v744
+    v746 = cast v708 as Field
+    v747 = mul v744, v746
+    constrain Field 0 == v747
+    v749 = call f2(Field 53438638232309528389504892708671455233, v737) -> u1
+    v750 = sub Field 53438638232309528389504892708671455233, v737
+    v751 = sub v750, Field 1
+    v752 = cast v749 as Field
+    v753 = mul v752, Field 340282366920938463463374607431768211456
+    v754 = add v751, v753
+    v755 = sub Field 64323764613183177041862057485226039389, v738
+    v756 = cast v749 as Field
+    v757 = sub v755, v756
+    v758 = cast v708 as Field
+    v759 = mul v754, v758
+    range_check v759 to 128 bits
+    v760 = cast v708 as Field
+    v761 = mul v757, v760
+    range_check v761 to 128 bits
+    v763 = call f2(v710, v737) -> u1
+    v764 = sub v710, v737
+    v765 = sub v764, Field 1
+    v766 = cast v763 as Field
+    v767 = mul v766, Field 340282366920938463463374607431768211456
+    v768 = add v765, v767
+    v769 = sub v711, v738
+    v770 = cast v763 as Field
+    v771 = sub v769, v770
+    v772 = cast v708 as Field
+    v773 = mul v768, v772
+    range_check v773 to 128 bits
+    v774 = cast v708 as Field
+    v775 = mul v771, v774
+    range_check v775 to 128 bits
+    enable_side_effects v708
+    v776 = not v708
+    v777 = cast v708 as Field
+    v778 = cast v776 as Field
+    enable_side_effects u1 1
+    v779 = sub v777, v629
+    return v779
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Remove IfElse:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = allocate -> &mut Field
+    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v40 = allocate -> &mut u1
+    enable_side_effects u1 1
+    v43 = array_get v9, index u32 0 -> u8
+    v44 = eq v43, u8 48
+    v45 = not v44
+    enable_side_effects v45
+    v46 = array_get v9, index u32 0 -> u8
+    v47 = lt v46, u8 48
+    v48 = mul v47, v45
+    constrain v48 == v45
+    enable_side_effects v44
+    v50 = array_get v9, index u32 1 -> u8
+    v51 = eq v50, u8 100
+    v52 = not v51
+    v53 = mul v44, v52
+    enable_side_effects v53
+    v54 = array_get v9, index u32 1 -> u8
+    v55 = lt v54, u8 100
+    v56 = mul v55, v53
+    constrain v56 == v53
+    v57 = not v53
+    v58 = mul v57, v45
+    v59 = unchecked_add v53, v58
+    v60 = mul v44, v51
+    enable_side_effects u1 1
+    v61 = not v59
+    enable_side_effects v61
+    v63 = array_get v9, index u32 2 -> u8
+    v64 = eq v63, u8 78
+    v65 = not v64
+    v66 = mul v61, v65
+    enable_side_effects v66
+    v67 = array_get v9, index u32 2 -> u8
+    v68 = lt v67, u8 78
+    v69 = mul v68, v66
+    constrain v69 == v66
+    v70 = not v66
+    v71 = mul v70, v59
+    v72 = unchecked_add v66, v71
+    v73 = mul v61, v64
+    enable_side_effects u1 1
+    v74 = not v72
+    enable_side_effects v74
+    v76 = array_get v9, index u32 3 -> u8
+    v77 = eq v76, u8 114
+    v78 = not v77
+    v79 = mul v74, v78
+    enable_side_effects v79
+    v80 = array_get v9, index u32 3 -> u8
+    v81 = lt v80, u8 114
+    v82 = mul v81, v79
+    constrain v82 == v79
+    v83 = not v79
+    v84 = mul v83, v72
+    v85 = unchecked_add v79, v84
+    v86 = mul v74, v77
+    enable_side_effects u1 1
+    v87 = not v85
+    enable_side_effects v87
+    v89 = array_get v9, index u32 4 -> u8
+    v90 = eq v89, u8 225
+    v91 = not v90
+    v92 = mul v87, v91
+    enable_side_effects v92
+    v93 = array_get v9, index u32 4 -> u8
+    v94 = lt v93, u8 225
+    v95 = mul v94, v92
+    constrain v95 == v92
+    v96 = not v92
+    v97 = mul v96, v85
+    v98 = unchecked_add v92, v97
+    v99 = mul v87, v90
+    enable_side_effects u1 1
+    v100 = not v98
+    enable_side_effects v100
+    v102 = array_get v9, index u32 5 -> u8
+    v103 = eq v102, u8 49
+    v104 = not v103
+    v105 = mul v100, v104
+    enable_side_effects v105
+    v106 = array_get v9, index u32 5 -> u8
+    v107 = lt v106, u8 49
+    v108 = mul v107, v105
+    constrain v108 == v105
+    v109 = not v105
+    v110 = mul v109, v98
+    v111 = unchecked_add v105, v110
+    v112 = mul v100, v103
+    enable_side_effects u1 1
+    v113 = not v111
+    enable_side_effects v113
+    v115 = array_get v9, index u32 6 -> u8
+    v116 = eq v115, u8 160
+    v117 = not v116
+    v118 = mul v113, v117
+    enable_side_effects v118
+    v119 = array_get v9, index u32 6 -> u8
+    v120 = lt v119, u8 160
+    v121 = mul v120, v118
+    constrain v121 == v118
+    v122 = not v118
+    v123 = mul v122, v111
+    v124 = unchecked_add v118, v123
+    v125 = mul v113, v116
+    enable_side_effects u1 1
+    v126 = not v124
+    enable_side_effects v126
+    v128 = array_get v9, index u32 7 -> u8
+    v129 = eq v128, u8 41
+    v130 = not v129
+    v131 = mul v126, v130
+    enable_side_effects v131
+    v132 = array_get v9, index u32 7 -> u8
+    v133 = lt v132, u8 41
+    v134 = mul v133, v131
+    constrain v134 == v131
+    v135 = not v131
+    v136 = mul v135, v124
+    v137 = unchecked_add v131, v136
+    v138 = mul v126, v129
+    enable_side_effects u1 1
+    v139 = not v137
+    enable_side_effects v139
+    v141 = array_get v9, index u32 8 -> u8
+    v142 = eq v141, u8 184
+    v143 = not v142
+    v144 = mul v139, v143
+    enable_side_effects v144
+    v145 = array_get v9, index u32 8 -> u8
+    v146 = lt v145, u8 184
+    v147 = mul v146, v144
+    constrain v147 == v144
+    v148 = not v144
+    v149 = mul v148, v137
+    v150 = unchecked_add v144, v149
+    v151 = mul v139, v142
+    enable_side_effects u1 1
+    v152 = not v150
+    enable_side_effects v152
+    v154 = array_get v9, index u32 9 -> u8
+    v155 = eq v154, u8 80
+    v156 = not v155
+    v157 = mul v152, v156
+    enable_side_effects v157
+    v158 = array_get v9, index u32 9 -> u8
+    v159 = lt v158, u8 80
+    v160 = mul v159, v157
+    constrain v160 == v157
+    v161 = not v157
+    v162 = mul v161, v150
+    v163 = unchecked_add v157, v162
+    v164 = mul v152, v155
+    enable_side_effects u1 1
+    v165 = not v163
+    enable_side_effects v165
+    v167 = array_get v9, index u32 10 -> u8
+    v168 = eq v167, u8 69
+    v169 = not v168
+    v170 = mul v165, v169
+    enable_side_effects v170
+    v171 = array_get v9, index u32 10 -> u8
+    v172 = lt v171, u8 69
+    v173 = mul v172, v170
+    constrain v173 == v170
+    v174 = not v170
+    v175 = mul v174, v163
+    v176 = unchecked_add v170, v175
+    v177 = mul v165, v168
+    enable_side_effects u1 1
+    v178 = not v176
+    enable_side_effects v178
+    v180 = array_get v9, index u32 11 -> u8
+    v181 = eq v180, u8 182
+    v182 = not v181
+    v183 = mul v178, v182
+    enable_side_effects v183
+    v184 = array_get v9, index u32 11 -> u8
+    v185 = lt v184, u8 182
+    v186 = mul v185, v183
+    constrain v186 == v183
+    v187 = not v183
+    v188 = mul v187, v176
+    v189 = unchecked_add v183, v188
+    v190 = mul v178, v181
+    enable_side_effects u1 1
+    v191 = not v189
+    enable_side_effects v191
+    v193 = array_get v9, index u32 12 -> u8
+    v194 = eq v193, u8 129
+    v195 = not v194
+    v196 = mul v191, v195
+    enable_side_effects v196
+    v197 = array_get v9, index u32 12 -> u8
+    v198 = lt v197, u8 129
+    v199 = mul v198, v196
+    constrain v199 == v196
+    v200 = not v196
+    v201 = mul v200, v189
+    v202 = unchecked_add v196, v201
+    v203 = mul v191, v194
+    enable_side_effects u1 1
+    v204 = not v202
+    enable_side_effects v204
+    v206 = array_get v9, index u32 13 -> u8
+    v207 = eq v206, u8 129
+    v208 = not v207
+    v209 = mul v204, v208
+    enable_side_effects v209
+    v210 = array_get v9, index u32 13 -> u8
+    v211 = lt v210, u8 129
+    v212 = mul v211, v209
+    constrain v212 == v209
+    v213 = not v209
+    v214 = mul v213, v202
+    v215 = unchecked_add v209, v214
+    v216 = mul v204, v207
+    enable_side_effects u1 1
+    v217 = not v215
+    enable_side_effects v217
+    v219 = array_get v9, index u32 14 -> u8
+    v220 = eq v219, u8 88
+    v221 = not v220
+    v222 = mul v217, v221
+    enable_side_effects v222
+    v223 = array_get v9, index u32 14 -> u8
+    v224 = lt v223, u8 88
+    v225 = mul v224, v222
+    constrain v225 == v222
+    v226 = not v222
+    v227 = mul v226, v215
+    v228 = unchecked_add v222, v227
+    v229 = mul v217, v220
+    enable_side_effects u1 1
+    v230 = not v228
+    enable_side_effects v230
+    v232 = array_get v9, index u32 15 -> u8
+    v233 = eq v232, u8 93
+    v234 = not v233
+    v235 = mul v230, v234
+    enable_side_effects v235
+    v236 = array_get v9, index u32 15 -> u8
+    v237 = lt v236, u8 93
+    v238 = mul v237, v235
+    constrain v238 == v235
+    v239 = not v235
+    v240 = mul v239, v228
+    v241 = unchecked_add v235, v240
+    v242 = mul v230, v233
+    enable_side_effects u1 1
+    v243 = not v241
+    enable_side_effects v243
+    v245 = array_get v9, index u32 16 -> u8
+    v246 = eq v245, u8 40
+    v247 = not v246
+    v248 = mul v243, v247
+    enable_side_effects v248
+    v249 = array_get v9, index u32 16 -> u8
+    v250 = lt v249, u8 40
+    v251 = mul v250, v248
+    constrain v251 == v248
+    v252 = not v248
+    v253 = mul v252, v241
+    v254 = unchecked_add v248, v253
+    v255 = mul v243, v246
+    enable_side_effects u1 1
+    v256 = not v254
+    enable_side_effects v256
+    v258 = array_get v9, index u32 17 -> u8
+    v259 = eq v258, u8 51
+    v260 = not v259
+    v261 = mul v256, v260
+    enable_side_effects v261
+    v262 = array_get v9, index u32 17 -> u8
+    v263 = lt v262, u8 51
+    v264 = mul v263, v261
+    constrain v264 == v261
+    v265 = not v261
+    v266 = mul v265, v254
+    v267 = unchecked_add v261, v266
+    v268 = mul v256, v259
+    enable_side_effects u1 1
+    v269 = not v267
+    enable_side_effects v269
+    v271 = array_get v9, index u32 18 -> u8
+    v272 = eq v271, u8 232
+    v273 = not v272
+    v274 = mul v269, v273
+    enable_side_effects v274
+    v275 = array_get v9, index u32 18 -> u8
+    v276 = lt v275, u8 232
+    v277 = mul v276, v274
+    constrain v277 == v274
+    v278 = not v274
+    v279 = mul v278, v267
+    v280 = unchecked_add v274, v279
+    v281 = mul v269, v272
+    enable_side_effects u1 1
+    v282 = not v280
+    enable_side_effects v282
+    v284 = array_get v9, index u32 19 -> u8
+    v285 = eq v284, u8 72
+    v286 = not v285
+    v287 = mul v282, v286
+    enable_side_effects v287
+    v288 = array_get v9, index u32 19 -> u8
+    v289 = lt v288, u8 72
+    v290 = mul v289, v287
+    constrain v290 == v287
+    v291 = not v287
+    v292 = mul v291, v280
+    v293 = unchecked_add v287, v292
+    v294 = mul v282, v285
+    enable_side_effects u1 1
+    v295 = not v293
+    enable_side_effects v295
+    v297 = array_get v9, index u32 20 -> u8
+    v298 = eq v297, u8 121
+    v299 = not v298
+    v300 = mul v295, v299
+    enable_side_effects v300
+    v301 = array_get v9, index u32 20 -> u8
+    v302 = lt v301, u8 121
+    v303 = mul v302, v300
+    constrain v303 == v300
+    v304 = not v300
+    v305 = mul v304, v293
+    v306 = unchecked_add v300, v305
+    v307 = mul v295, v298
+    enable_side_effects u1 1
+    v308 = not v306
+    enable_side_effects v308
+    v310 = array_get v9, index u32 21 -> u8
+    v311 = eq v310, u8 185
+    v312 = not v311
+    v313 = mul v308, v312
+    enable_side_effects v313
+    v314 = array_get v9, index u32 21 -> u8
+    v315 = lt v314, u8 185
+    v316 = mul v315, v313
+    constrain v316 == v313
+    v317 = not v313
+    v318 = mul v317, v306
+    v319 = unchecked_add v313, v318
+    v320 = mul v308, v311
+    enable_side_effects u1 1
+    v321 = not v319
+    enable_side_effects v321
+    v323 = array_get v9, index u32 22 -> u8
+    v324 = eq v323, u8 112
+    v325 = not v324
+    v326 = mul v321, v325
+    enable_side_effects v326
+    v327 = array_get v9, index u32 22 -> u8
+    v328 = lt v327, u8 112
+    v329 = mul v328, v326
+    constrain v329 == v326
+    v330 = not v326
+    v331 = mul v330, v319
+    v332 = unchecked_add v326, v331
+    v333 = mul v321, v324
+    enable_side_effects u1 1
+    v334 = not v332
+    enable_side_effects v334
+    v336 = array_get v9, index u32 23 -> u8
+    v337 = eq v336, u8 145
+    v338 = not v337
+    v339 = mul v334, v338
+    enable_side_effects v339
+    v340 = array_get v9, index u32 23 -> u8
+    v341 = lt v340, u8 145
+    v342 = mul v341, v339
+    constrain v342 == v339
+    v343 = not v339
+    v344 = mul v343, v332
+    v345 = unchecked_add v339, v344
+    v346 = mul v334, v337
+    enable_side_effects u1 1
+    v347 = not v345
+    enable_side_effects v347
+    v349 = array_get v9, index u32 24 -> u8
+    v350 = eq v349, u8 67
+    v351 = not v350
+    v352 = mul v347, v351
+    enable_side_effects v352
+    v353 = array_get v9, index u32 24 -> u8
+    v354 = lt v353, u8 67
+    v355 = mul v354, v352
+    constrain v355 == v352
+    v356 = not v352
+    v357 = mul v356, v345
+    v358 = unchecked_add v352, v357
+    v359 = mul v347, v350
+    enable_side_effects u1 1
+    v360 = not v358
+    enable_side_effects v360
+    v362 = array_get v9, index u32 25 -> u8
+    v363 = eq v362, u8 225
+    v364 = not v363
+    v365 = mul v360, v364
+    enable_side_effects v365
+    v366 = array_get v9, index u32 25 -> u8
+    v367 = lt v366, u8 225
+    v368 = mul v367, v365
+    constrain v368 == v365
+    v369 = not v365
+    v370 = mul v369, v358
+    v371 = unchecked_add v365, v370
+    v372 = mul v360, v363
+    enable_side_effects u1 1
+    v373 = not v371
+    enable_side_effects v373
+    v375 = array_get v9, index u32 26 -> u8
+    v376 = eq v375, u8 245
+    v377 = not v376
+    v378 = mul v373, v377
+    enable_side_effects v378
+    v379 = array_get v9, index u32 26 -> u8
+    v380 = lt v379, u8 245
+    v381 = mul v380, v378
+    constrain v381 == v378
+    v382 = not v378
+    v383 = mul v382, v371
+    v384 = unchecked_add v378, v383
+    v385 = mul v373, v376
+    enable_side_effects u1 1
+    v386 = not v384
+    enable_side_effects v386
+    v388 = array_get v9, index u32 27 -> u8
+    v389 = eq v388, u8 147
+    v390 = not v389
+    v391 = mul v386, v390
+    enable_side_effects v391
+    v392 = array_get v9, index u32 27 -> u8
+    v393 = lt v392, u8 147
+    v394 = mul v393, v391
+    constrain v394 == v391
+    v395 = not v391
+    v396 = mul v395, v384
+    v397 = unchecked_add v391, v396
+    v398 = mul v386, v389
+    enable_side_effects u1 1
+    v399 = not v397
+    enable_side_effects v399
+    v401 = array_get v9, index u32 28 -> u8
+    v402 = eq v401, u8 240
+    v403 = not v402
+    v404 = mul v399, v403
+    enable_side_effects v404
+    v405 = array_get v9, index u32 28 -> u8
+    v406 = lt v405, u8 240
+    v407 = mul v406, v404
+    constrain v407 == v404
+    v408 = not v404
+    v409 = mul v408, v397
+    v410 = unchecked_add v404, v409
+    v411 = mul v399, v402
+    enable_side_effects u1 1
+    v412 = not v410
+    enable_side_effects v412
+    v414 = array_get v9, index u32 29 -> u8
+    v415 = eq v414, u8 0
+    v416 = not v415
+    v417 = mul v412, v416
+    enable_side_effects v417
+    v418 = array_get v9, index u32 29 -> u8
+    constrain u1 0 == v417
+    v420 = not v417
+    v421 = mul v420, v410
+    v422 = unchecked_add v417, v421
+    v423 = mul v412, v415
+    enable_side_effects u1 1
+    v424 = not v422
+    enable_side_effects v424
+    v426 = array_get v9, index u32 30 -> u8
+    v427 = eq v426, u8 0
+    v428 = not v427
+    v429 = mul v424, v428
+    enable_side_effects v429
+    v430 = array_get v9, index u32 30 -> u8
+    constrain u1 0 == v429
+    v431 = not v429
+    v432 = mul v431, v422
+    v433 = unchecked_add v429, v432
+    v434 = mul v424, v427
+    enable_side_effects u1 1
+    v435 = not v433
+    enable_side_effects v435
+    v437 = array_get v9, index u32 31 -> u8
+    v438 = eq v437, u8 1
+    v439 = not v438
+    v440 = mul v435, v439
+    enable_side_effects v440
+    v441 = array_get v9, index u32 31 -> u8
+    v442 = eq v441, u8 0
+    v443 = cast v440 as u8
+    v444 = unchecked_mul v441, v443
+    constrain v444 == u8 0
+    v445 = not v440
+    v446 = mul v445, v433
+    v447 = unchecked_add v440, v446
+    v448 = mul v435, v438
+    enable_side_effects u1 1
+    constrain v447 == u1 1
+    v449 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v450 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v451 = allocate -> &mut u1
+    enable_side_effects u1 1
+    v452 = allocate -> &mut [u8; 32]
+    v453 = array_get v9, index u32 0 -> u8
+    v454 = make_array [v453, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v455 = array_get v9, index u32 1 -> u8
+    v456 = make_array [v453, v455, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v457 = array_get v9, index u32 2 -> u8
+    v458 = make_array [v453, v455, v457, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v459 = array_get v9, index u32 3 -> u8
+    v460 = make_array [v453, v455, v457, v459, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v461 = array_get v9, index u32 4 -> u8
+    v462 = make_array [v453, v455, v457, v459, v461, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v463 = array_get v9, index u32 5 -> u8
+    v464 = make_array [v453, v455, v457, v459, v461, v463, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v465 = array_get v9, index u32 6 -> u8
+    v466 = make_array [v453, v455, v457, v459, v461, v463, v465, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v467 = array_get v9, index u32 7 -> u8
+    v468 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v469 = array_get v9, index u32 8 -> u8
+    v470 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v471 = array_get v9, index u32 9 -> u8
+    v472 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v473 = array_get v9, index u32 10 -> u8
+    v474 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v475 = array_get v9, index u32 11 -> u8
+    v476 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v477 = array_get v9, index u32 12 -> u8
+    v478 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v479 = array_get v9, index u32 13 -> u8
+    v480 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v481 = array_get v9, index u32 14 -> u8
+    v482 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v483 = array_get v9, index u32 15 -> u8
+    v484 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v485 = array_get v9, index u32 16 -> u8
+    v486 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v487 = array_get v9, index u32 17 -> u8
+    v488 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v489 = array_get v9, index u32 18 -> u8
+    v490 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v491 = array_get v9, index u32 19 -> u8
+    v492 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v493 = array_get v9, index u32 20 -> u8
+    v494 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v495 = array_get v9, index u32 21 -> u8
+    v496 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v497 = array_get v9, index u32 22 -> u8
+    v498 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v499 = array_get v9, index u32 23 -> u8
+    v500 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v501 = array_get v9, index u32 24 -> u8
+    v502 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v503 = array_get v9, index u32 25 -> u8
+    v504 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v505 = array_get v9, index u32 26 -> u8
+    v506 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v507 = array_get v9, index u32 27 -> u8
+    v508 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v509 = array_get v9, index u32 28 -> u8
+    v510 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, u8 0, u8 0, u8 0] : [u8; 32]
+    v511 = array_get v9, index u32 29 -> u8
+    v512 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, u8 0, u8 0] : [u8; 32]
+    v513 = array_get v9, index u32 30 -> u8
+    v514 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, v513, u8 0] : [u8; 32]
+    v515 = array_get v9, index u32 31 -> u8
+    v516 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, v513, v515] : [u8; 32]
+    v517 = allocate -> &mut Field
+    v518 = allocate -> &mut Field
+    v519 = allocate -> &mut Field
+    v520 = cast v483 as Field
+    v521 = cast v515 as Field
+    v522 = cast v481 as Field
+    v524 = mul v522, Field 256
+    v525 = add v520, v524
+    v526 = cast v513 as Field
+    v527 = mul v526, Field 256
+    v528 = add v521, v527
+    v529 = cast v479 as Field
+    v531 = mul v529, Field 65536
+    v532 = add v525, v531
+    v533 = cast v511 as Field
+    v534 = mul v533, Field 65536
+    v535 = add v528, v534
+    v536 = cast v477 as Field
+    v538 = mul v536, Field 16777216
+    v539 = add v532, v538
+    v540 = cast v509 as Field
+    v541 = mul v540, Field 16777216
+    v542 = add v535, v541
+    v543 = cast v475 as Field
+    v545 = mul v543, Field 4294967296
+    v546 = add v539, v545
+    v547 = cast v507 as Field
+    v548 = mul v547, Field 4294967296
+    v549 = add v542, v548
+    v550 = cast v473 as Field
+    v552 = mul v550, Field 1099511627776
+    v553 = add v546, v552
+    v554 = cast v505 as Field
+    v555 = mul v554, Field 1099511627776
+    v556 = add v549, v555
+    v557 = cast v471 as Field
+    v559 = mul v557, Field 281474976710656
+    v560 = add v553, v559
+    v561 = cast v503 as Field
+    v562 = mul v561, Field 281474976710656
+    v563 = add v556, v562
+    v564 = cast v469 as Field
+    v566 = mul v564, Field 72057594037927936
+    v567 = add v560, v566
+    v568 = cast v501 as Field
+    v569 = mul v568, Field 72057594037927936
+    v570 = add v563, v569
+    v571 = cast v467 as Field
+    v573 = mul v571, Field 18446744073709551616
+    v574 = add v567, v573
+    v575 = cast v499 as Field
+    v576 = mul v575, Field 18446744073709551616
+    v577 = add v570, v576
+    v578 = cast v465 as Field
+    v580 = mul v578, Field 4722366482869645213696
+    v581 = add v574, v580
+    v582 = cast v497 as Field
+    v583 = mul v582, Field 4722366482869645213696
+    v584 = add v577, v583
+    v585 = cast v463 as Field
+    v587 = mul v585, Field 1208925819614629174706176
+    v588 = add v581, v587
+    v589 = cast v495 as Field
+    v590 = mul v589, Field 1208925819614629174706176
+    v591 = add v584, v590
+    v592 = cast v461 as Field
+    v594 = mul v592, Field 309485009821345068724781056
+    v595 = add v588, v594
+    v596 = cast v493 as Field
+    v597 = mul v596, Field 309485009821345068724781056
+    v598 = add v591, v597
+    v599 = cast v459 as Field
+    v601 = mul v599, Field 79228162514264337593543950336
+    v602 = add v595, v601
+    v603 = cast v491 as Field
+    v604 = mul v603, Field 79228162514264337593543950336
+    v605 = add v598, v604
+    v606 = cast v457 as Field
+    v608 = mul v606, Field 20282409603651670423947251286016
+    v609 = add v602, v608
+    v610 = cast v489 as Field
+    v611 = mul v610, Field 20282409603651670423947251286016
+    v612 = add v605, v611
+    v613 = cast v455 as Field
+    v615 = mul v613, Field 5192296858534827628530496329220096
+    v616 = add v609, v615
+    v617 = cast v487 as Field
+    v618 = mul v617, Field 5192296858534827628530496329220096
+    v619 = add v612, v618
+    v620 = cast v453 as Field
+    v622 = mul v620, Field 1329227995784915872903807060280344576
+    v623 = add v616, v622
+    v624 = cast v485 as Field
+    v625 = mul v624, Field 1329227995784915872903807060280344576
+    v626 = add v619, v625
+    v628 = mul v623, Field 340282366920938463463374607431768211456
+    v629 = add v626, v628
+    v630 = allocate -> &mut Field
+    v632 = eq v4, Field 0
+    enable_side_effects v632
+    v633 = not v632
+    enable_side_effects v633
+    v635 = call f1(v4, Field 0) -> u1
+    v636 = mul v633, v635
+    enable_side_effects v636
+    v638, v639 = call f3(Field 0) -> (Field, Field)
+    v640 = cast v636 as Field
+    v641 = mul v638, v640
+    range_check v641 to 128 bits
+    v642 = cast v636 as Field
+    v643 = mul v639, v642
+    range_check v643 to 128 bits
+    v644 = mul Field 340282366920938463463374607431768211456, v639
+    v645 = add v638, v644
+    v646 = eq Field 0, v645
+    v647 = cast v636 as Field
+    v648 = mul v645, v647
+    constrain Field 0 == v648
+    v651 = call f2(Field 53438638232309528389504892708671455233, v638) -> u1
+    v652 = sub Field 53438638232309528389504892708671455233, v638
+    v654 = sub v652, Field 1
+    v655 = cast v651 as Field
+    v656 = mul v655, Field 340282366920938463463374607431768211456
+    v657 = add v654, v656
+    v659 = sub Field 64323764613183177041862057485226039389, v639
+    v660 = cast v651 as Field
+    v661 = sub v659, v660
+    v662 = cast v636 as Field
+    v663 = mul v657, v662
+    range_check v663 to 128 bits
+    v664 = cast v636 as Field
+    v665 = mul v661, v664
+    range_check v665 to 128 bits
+    v667, v668 = call f3(v4) -> (Field, Field)
+    v669 = cast v636 as Field
+    v670 = mul v667, v669
+    range_check v670 to 128 bits
+    v671 = cast v636 as Field
+    v672 = mul v668, v671
+    range_check v672 to 128 bits
+    v673 = mul Field 340282366920938463463374607431768211456, v668
+    v674 = add v667, v673
+    v675 = eq v4, v674
+    v676 = cast v636 as Field
+    v677 = mul v4, v676
+    v678 = mul v674, v676
+    constrain v677 == v678
+    v680 = call f2(Field 53438638232309528389504892708671455233, v667) -> u1
+    v681 = sub Field 53438638232309528389504892708671455233, v667
+    v682 = sub v681, Field 1
+    v683 = cast v680 as Field
+    v684 = mul v683, Field 340282366920938463463374607431768211456
+    v685 = add v682, v684
+    v686 = sub Field 64323764613183177041862057485226039389, v668
+    v687 = cast v680 as Field
+    v688 = sub v686, v687
+    v689 = cast v636 as Field
+    v690 = mul v685, v689
+    range_check v690 to 128 bits
+    v691 = cast v636 as Field
+    v692 = mul v688, v691
+    range_check v692 to 128 bits
+    v694 = call f2(v638, v667) -> u1
+    v695 = sub v638, v667
+    v696 = sub v695, Field 1
+    v697 = cast v694 as Field
+    v698 = mul v697, Field 340282366920938463463374607431768211456
+    v699 = add v696, v698
+    v700 = sub v639, v668
+    v701 = cast v694 as Field
+    v702 = sub v700, v701
+    v703 = cast v636 as Field
+    v704 = mul v699, v703
+    range_check v704 to 128 bits
+    v705 = cast v636 as Field
+    v706 = mul v702, v705
+    range_check v706 to 128 bits
+    v707 = not v635
+    v708 = mul v633, v707
+    enable_side_effects v708
+    v710, v711 = call f3(v4) -> (Field, Field)
+    v712 = cast v708 as Field
+    v713 = mul v710, v712
+    range_check v713 to 128 bits
+    v714 = cast v708 as Field
+    v715 = mul v711, v714
+    range_check v715 to 128 bits
+    v716 = mul Field 340282366920938463463374607431768211456, v711
+    v717 = add v710, v716
+    v718 = eq v4, v717
+    v719 = cast v708 as Field
+    v720 = mul v4, v719
+    v721 = mul v717, v719
+    constrain v720 == v721
+    v723 = call f2(Field 53438638232309528389504892708671455233, v710) -> u1
+    v724 = sub Field 53438638232309528389504892708671455233, v710
+    v725 = sub v724, Field 1
+    v726 = cast v723 as Field
+    v727 = mul v726, Field 340282366920938463463374607431768211456
+    v728 = add v725, v727
+    v729 = sub Field 64323764613183177041862057485226039389, v711
+    v730 = cast v723 as Field
+    v731 = sub v729, v730
+    v732 = cast v708 as Field
+    v733 = mul v728, v732
+    range_check v733 to 128 bits
+    v734 = cast v708 as Field
+    v735 = mul v731, v734
+    range_check v735 to 128 bits
+    v737, v738 = call f3(Field 0) -> (Field, Field)
+    v739 = cast v708 as Field
+    v740 = mul v737, v739
+    range_check v740 to 128 bits
+    v741 = cast v708 as Field
+    v742 = mul v738, v741
+    range_check v742 to 128 bits
+    v743 = mul Field 340282366920938463463374607431768211456, v738
+    v744 = add v737, v743
+    v745 = eq Field 0, v744
+    v746 = cast v708 as Field
+    v747 = mul v744, v746
+    constrain Field 0 == v747
+    v749 = call f2(Field 53438638232309528389504892708671455233, v737) -> u1
+    v750 = sub Field 53438638232309528389504892708671455233, v737
+    v751 = sub v750, Field 1
+    v752 = cast v749 as Field
+    v753 = mul v752, Field 340282366920938463463374607431768211456
+    v754 = add v751, v753
+    v755 = sub Field 64323764613183177041862057485226039389, v738
+    v756 = cast v749 as Field
+    v757 = sub v755, v756
+    v758 = cast v708 as Field
+    v759 = mul v754, v758
+    range_check v759 to 128 bits
+    v760 = cast v708 as Field
+    v761 = mul v757, v760
+    range_check v761 to 128 bits
+    v763 = call f2(v710, v737) -> u1
+    v764 = sub v710, v737
+    v765 = sub v764, Field 1
+    v766 = cast v763 as Field
+    v767 = mul v766, Field 340282366920938463463374607431768211456
+    v768 = add v765, v767
+    v769 = sub v711, v738
+    v770 = cast v763 as Field
+    v771 = sub v769, v770
+    v772 = cast v708 as Field
+    v773 = mul v768, v772
+    range_check v773 to 128 bits
+    v774 = cast v708 as Field
+    v775 = mul v771, v774
+    range_check v775 to 128 bits
+    enable_side_effects v708
+    v776 = not v708
+    v777 = cast v708 as Field
+    v778 = cast v776 as Field
+    enable_side_effects u1 1
+    v779 = sub v777, v629
+    return v779
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Constant Folding:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = allocate -> &mut Field
+    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v40 = allocate -> &mut u1
+    enable_side_effects u1 1
+    v43 = array_get v9, index u32 0 -> u8
+    v44 = eq v43, u8 48
+    v45 = not v44
+    enable_side_effects v45
+    v46 = lt v43, u8 48
+    v47 = mul v46, v45
+    constrain v47 == v45
+    enable_side_effects v44
+    v49 = array_get v9, index u32 1 -> u8
+    v50 = eq v49, u8 100
+    v51 = not v50
+    v52 = mul v44, v51
+    enable_side_effects v52
+    v53 = lt v49, u8 100
+    v54 = mul v53, v52
+    constrain v54 == v52
+    v55 = not v52
+    v56 = mul v55, v45
+    v57 = unchecked_add v52, v56
+    v58 = mul v44, v50
+    enable_side_effects u1 1
+    v59 = not v57
+    enable_side_effects v59
+    v61 = array_get v9, index u32 2 -> u8
+    v62 = eq v61, u8 78
+    v63 = not v62
+    v64 = mul v59, v63
+    enable_side_effects v64
+    v65 = lt v61, u8 78
+    v66 = mul v65, v64
+    constrain v66 == v64
+    v67 = not v64
+    v68 = mul v67, v57
+    v69 = unchecked_add v64, v68
+    v70 = mul v59, v62
+    enable_side_effects u1 1
+    v71 = not v69
+    enable_side_effects v71
+    v73 = array_get v9, index u32 3 -> u8
+    v74 = eq v73, u8 114
+    v75 = not v74
+    v76 = mul v71, v75
+    enable_side_effects v76
+    v77 = lt v73, u8 114
+    v78 = mul v77, v76
+    constrain v78 == v76
+    v79 = not v76
+    v80 = mul v79, v69
+    v81 = unchecked_add v76, v80
+    v82 = mul v71, v74
+    enable_side_effects u1 1
+    v83 = not v81
+    enable_side_effects v83
+    v85 = array_get v9, index u32 4 -> u8
+    v86 = eq v85, u8 225
+    v87 = not v86
+    v88 = mul v83, v87
+    enable_side_effects v88
+    v89 = lt v85, u8 225
+    v90 = mul v89, v88
+    constrain v90 == v88
+    v91 = not v88
+    v92 = mul v91, v81
+    v93 = unchecked_add v88, v92
+    v94 = mul v83, v86
+    enable_side_effects u1 1
+    v95 = not v93
+    enable_side_effects v95
+    v97 = array_get v9, index u32 5 -> u8
+    v98 = eq v97, u8 49
+    v99 = not v98
+    v100 = mul v95, v99
+    enable_side_effects v100
+    v101 = lt v97, u8 49
+    v102 = mul v101, v100
+    constrain v102 == v100
+    v103 = not v100
+    v104 = mul v103, v93
+    v105 = unchecked_add v100, v104
+    v106 = mul v95, v98
+    enable_side_effects u1 1
+    v107 = not v105
+    enable_side_effects v107
+    v109 = array_get v9, index u32 6 -> u8
+    v110 = eq v109, u8 160
+    v111 = not v110
+    v112 = mul v107, v111
+    enable_side_effects v112
+    v113 = lt v109, u8 160
+    v114 = mul v113, v112
+    constrain v114 == v112
+    v115 = not v112
+    v116 = mul v115, v105
+    v117 = unchecked_add v112, v116
+    v118 = mul v107, v110
+    enable_side_effects u1 1
+    v119 = not v117
+    enable_side_effects v119
+    v121 = array_get v9, index u32 7 -> u8
+    v122 = eq v121, u8 41
+    v123 = not v122
+    v124 = mul v119, v123
+    enable_side_effects v124
+    v125 = lt v121, u8 41
+    v126 = mul v125, v124
+    constrain v126 == v124
+    v127 = not v124
+    v128 = mul v127, v117
+    v129 = unchecked_add v124, v128
+    v130 = mul v119, v122
+    enable_side_effects u1 1
+    v131 = not v129
+    enable_side_effects v131
+    v133 = array_get v9, index u32 8 -> u8
+    v134 = eq v133, u8 184
+    v135 = not v134
+    v136 = mul v131, v135
+    enable_side_effects v136
+    v137 = lt v133, u8 184
+    v138 = mul v137, v136
+    constrain v138 == v136
+    v139 = not v136
+    v140 = mul v139, v129
+    v141 = unchecked_add v136, v140
+    v142 = mul v131, v134
+    enable_side_effects u1 1
+    v143 = not v141
+    enable_side_effects v143
+    v145 = array_get v9, index u32 9 -> u8
+    v146 = eq v145, u8 80
+    v147 = not v146
+    v148 = mul v143, v147
+    enable_side_effects v148
+    v149 = lt v145, u8 80
+    v150 = mul v149, v148
+    constrain v150 == v148
+    v151 = not v148
+    v152 = mul v151, v141
+    v153 = unchecked_add v148, v152
+    v154 = mul v143, v146
+    enable_side_effects u1 1
+    v155 = not v153
+    enable_side_effects v155
+    v157 = array_get v9, index u32 10 -> u8
+    v158 = eq v157, u8 69
+    v159 = not v158
+    v160 = mul v155, v159
+    enable_side_effects v160
+    v161 = lt v157, u8 69
+    v162 = mul v161, v160
+    constrain v162 == v160
+    v163 = not v160
+    v164 = mul v163, v153
+    v165 = unchecked_add v160, v164
+    v166 = mul v155, v158
+    enable_side_effects u1 1
+    v167 = not v165
+    enable_side_effects v167
+    v169 = array_get v9, index u32 11 -> u8
+    v170 = eq v169, u8 182
+    v171 = not v170
+    v172 = mul v167, v171
+    enable_side_effects v172
+    v173 = lt v169, u8 182
+    v174 = mul v173, v172
+    constrain v174 == v172
+    v175 = not v172
+    v176 = mul v175, v165
+    v177 = unchecked_add v172, v176
+    v178 = mul v167, v170
+    enable_side_effects u1 1
+    v179 = not v177
+    enable_side_effects v179
+    v181 = array_get v9, index u32 12 -> u8
+    v182 = eq v181, u8 129
+    v183 = not v182
+    v184 = mul v179, v183
+    enable_side_effects v184
+    v185 = lt v181, u8 129
+    v186 = mul v185, v184
+    constrain v186 == v184
+    v187 = not v184
+    v188 = mul v187, v177
+    v189 = unchecked_add v184, v188
+    v190 = mul v179, v182
+    enable_side_effects u1 1
+    v191 = not v189
+    enable_side_effects v191
+    v193 = array_get v9, index u32 13 -> u8
+    v194 = eq v193, u8 129
+    v195 = not v194
+    v196 = mul v191, v195
+    enable_side_effects v196
+    v197 = lt v193, u8 129
+    v198 = mul v197, v196
+    constrain v198 == v196
+    v199 = not v196
+    v200 = mul v199, v189
+    v201 = unchecked_add v196, v200
+    v202 = mul v191, v194
+    enable_side_effects u1 1
+    v203 = not v201
+    enable_side_effects v203
+    v205 = array_get v9, index u32 14 -> u8
+    v206 = eq v205, u8 88
+    v207 = not v206
+    v208 = mul v203, v207
+    enable_side_effects v208
+    v209 = lt v205, u8 88
+    v210 = mul v209, v208
+    constrain v210 == v208
+    v211 = not v208
+    v212 = mul v211, v201
+    v213 = unchecked_add v208, v212
+    v214 = mul v203, v206
+    enable_side_effects u1 1
+    v215 = not v213
+    enable_side_effects v215
+    v217 = array_get v9, index u32 15 -> u8
+    v218 = eq v217, u8 93
+    v219 = not v218
+    v220 = mul v215, v219
+    enable_side_effects v220
+    v221 = lt v217, u8 93
+    v222 = mul v221, v220
+    constrain v222 == v220
+    v223 = not v220
+    v224 = mul v223, v213
+    v225 = unchecked_add v220, v224
+    v226 = mul v215, v218
+    enable_side_effects u1 1
+    v227 = not v225
+    enable_side_effects v227
+    v229 = array_get v9, index u32 16 -> u8
+    v230 = eq v229, u8 40
+    v231 = not v230
+    v232 = mul v227, v231
+    enable_side_effects v232
+    v233 = lt v229, u8 40
+    v234 = mul v233, v232
+    constrain v234 == v232
+    v235 = not v232
+    v236 = mul v235, v225
+    v237 = unchecked_add v232, v236
+    v238 = mul v227, v230
+    enable_side_effects u1 1
+    v239 = not v237
+    enable_side_effects v239
+    v241 = array_get v9, index u32 17 -> u8
+    v242 = eq v241, u8 51
+    v243 = not v242
+    v244 = mul v239, v243
+    enable_side_effects v244
+    v245 = lt v241, u8 51
+    v246 = mul v245, v244
+    constrain v246 == v244
+    v247 = not v244
+    v248 = mul v247, v237
+    v249 = unchecked_add v244, v248
+    v250 = mul v239, v242
+    enable_side_effects u1 1
+    v251 = not v249
+    enable_side_effects v251
+    v253 = array_get v9, index u32 18 -> u8
+    v254 = eq v253, u8 232
+    v255 = not v254
+    v256 = mul v251, v255
+    enable_side_effects v256
+    v257 = lt v253, u8 232
+    v258 = mul v257, v256
+    constrain v258 == v256
+    v259 = not v256
+    v260 = mul v259, v249
+    v261 = unchecked_add v256, v260
+    v262 = mul v251, v254
+    enable_side_effects u1 1
+    v263 = not v261
+    enable_side_effects v263
+    v265 = array_get v9, index u32 19 -> u8
+    v266 = eq v265, u8 72
+    v267 = not v266
+    v268 = mul v263, v267
+    enable_side_effects v268
+    v269 = lt v265, u8 72
+    v270 = mul v269, v268
+    constrain v270 == v268
+    v271 = not v268
+    v272 = mul v271, v261
+    v273 = unchecked_add v268, v272
+    v274 = mul v263, v266
+    enable_side_effects u1 1
+    v275 = not v273
+    enable_side_effects v275
+    v277 = array_get v9, index u32 20 -> u8
+    v278 = eq v277, u8 121
+    v279 = not v278
+    v280 = mul v275, v279
+    enable_side_effects v280
+    v281 = lt v277, u8 121
+    v282 = mul v281, v280
+    constrain v282 == v280
+    v283 = not v280
+    v284 = mul v283, v273
+    v285 = unchecked_add v280, v284
+    v286 = mul v275, v278
+    enable_side_effects u1 1
+    v287 = not v285
+    enable_side_effects v287
+    v289 = array_get v9, index u32 21 -> u8
+    v290 = eq v289, u8 185
+    v291 = not v290
+    v292 = mul v287, v291
+    enable_side_effects v292
+    v293 = lt v289, u8 185
+    v294 = mul v293, v292
+    constrain v294 == v292
+    v295 = not v292
+    v296 = mul v295, v285
+    v297 = unchecked_add v292, v296
+    v298 = mul v287, v290
+    enable_side_effects u1 1
+    v299 = not v297
+    enable_side_effects v299
+    v301 = array_get v9, index u32 22 -> u8
+    v302 = eq v301, u8 112
+    v303 = not v302
+    v304 = mul v299, v303
+    enable_side_effects v304
+    v305 = lt v301, u8 112
+    v306 = mul v305, v304
+    constrain v306 == v304
+    v307 = not v304
+    v308 = mul v307, v297
+    v309 = unchecked_add v304, v308
+    v310 = mul v299, v302
+    enable_side_effects u1 1
+    v311 = not v309
+    enable_side_effects v311
+    v313 = array_get v9, index u32 23 -> u8
+    v314 = eq v313, u8 145
+    v315 = not v314
+    v316 = mul v311, v315
+    enable_side_effects v316
+    v317 = lt v313, u8 145
+    v318 = mul v317, v316
+    constrain v318 == v316
+    v319 = not v316
+    v320 = mul v319, v309
+    v321 = unchecked_add v316, v320
+    v322 = mul v311, v314
+    enable_side_effects u1 1
+    v323 = not v321
+    enable_side_effects v323
+    v325 = array_get v9, index u32 24 -> u8
+    v326 = eq v325, u8 67
+    v327 = not v326
+    v328 = mul v323, v327
+    enable_side_effects v328
+    v329 = lt v325, u8 67
+    v330 = mul v329, v328
+    constrain v330 == v328
+    v331 = not v328
+    v332 = mul v331, v321
+    v333 = unchecked_add v328, v332
+    v334 = mul v323, v326
+    enable_side_effects u1 1
+    v335 = not v333
+    enable_side_effects v335
+    v337 = array_get v9, index u32 25 -> u8
+    v338 = eq v337, u8 225
+    v339 = not v338
+    v340 = mul v335, v339
+    enable_side_effects v340
+    v341 = lt v337, u8 225
+    v342 = mul v341, v340
+    constrain v342 == v340
+    v343 = not v340
+    v344 = mul v343, v333
+    v345 = unchecked_add v340, v344
+    v346 = mul v335, v338
+    enable_side_effects u1 1
+    v347 = not v345
+    enable_side_effects v347
+    v349 = array_get v9, index u32 26 -> u8
+    v350 = eq v349, u8 245
+    v351 = not v350
+    v352 = mul v347, v351
+    enable_side_effects v352
+    v353 = lt v349, u8 245
+    v354 = mul v353, v352
+    constrain v354 == v352
+    v355 = not v352
+    v356 = mul v355, v345
+    v357 = unchecked_add v352, v356
+    v358 = mul v347, v350
+    enable_side_effects u1 1
+    v359 = not v357
+    enable_side_effects v359
+    v361 = array_get v9, index u32 27 -> u8
+    v362 = eq v361, u8 147
+    v363 = not v362
+    v364 = mul v359, v363
+    enable_side_effects v364
+    v365 = lt v361, u8 147
+    v366 = mul v365, v364
+    constrain v366 == v364
+    v367 = not v364
+    v368 = mul v367, v357
+    v369 = unchecked_add v364, v368
+    v370 = mul v359, v362
+    enable_side_effects u1 1
+    v371 = not v369
+    enable_side_effects v371
+    v373 = array_get v9, index u32 28 -> u8
+    v374 = eq v373, u8 240
+    v375 = not v374
+    v376 = mul v371, v375
+    enable_side_effects v376
+    v377 = lt v373, u8 240
+    v378 = mul v377, v376
+    constrain v378 == v376
+    v379 = not v376
+    v380 = mul v379, v369
+    v381 = unchecked_add v376, v380
+    v382 = mul v371, v374
+    enable_side_effects u1 1
+    v383 = not v381
+    enable_side_effects v383
+    v385 = array_get v9, index u32 29 -> u8
+    v386 = eq v385, u8 0
+    v387 = not v386
+    v388 = mul v383, v387
+    enable_side_effects v388
+    constrain u1 0 == v388
+    v390 = not v388
+    v391 = mul v390, v381
+    v392 = unchecked_add v388, v391
+    v393 = mul v383, v386
+    enable_side_effects u1 1
+    v394 = not v392
+    enable_side_effects v394
+    v396 = array_get v9, index u32 30 -> u8
+    v397 = eq v396, u8 0
+    v398 = not v397
+    v399 = mul v394, v398
+    enable_side_effects v399
+    constrain u1 0 == v399
+    v400 = not v399
+    v401 = mul v400, v392
+    v402 = unchecked_add v399, v401
+    v403 = mul v394, v397
+    enable_side_effects u1 1
+    v404 = not v402
+    enable_side_effects v404
+    v406 = array_get v9, index u32 31 -> u8
+    v407 = eq v406, u8 1
+    v408 = not v407
+    v409 = mul v404, v408
+    enable_side_effects v409
+    v410 = eq v406, u8 0
+    v411 = cast v409 as u8
+    v412 = unchecked_mul v406, v411
+    constrain v412 == u8 0
+    v413 = not v409
+    v414 = mul v413, v402
+    v415 = unchecked_add v409, v414
+    v416 = mul v404, v407
+    enable_side_effects u1 1
+    constrain v415 == u1 1
+    v417 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v418 = allocate -> &mut u1
+    enable_side_effects u1 1
+    v419 = allocate -> &mut [u8; 32]
+    v420 = make_array [v43, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v421 = make_array [v43, v49, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v422 = make_array [v43, v49, v61, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v423 = make_array [v43, v49, v61, v73, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v424 = make_array [v43, v49, v61, v73, v85, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v425 = make_array [v43, v49, v61, v73, v85, v97, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v426 = make_array [v43, v49, v61, v73, v85, v97, v109, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v427 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v428 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v429 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v430 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v431 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v432 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v433 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v434 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v435 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v436 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v437 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v438 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v439 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v440 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v441 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v442 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v443 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v444 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v445 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v446 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v447 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v448 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, u8 0, u8 0, u8 0] : [u8; 32]
+    v449 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, u8 0, u8 0] : [u8; 32]
+    v450 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v396, u8 0] : [u8; 32]
+    v451 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v396, v406] : [u8; 32]
+    v452 = allocate -> &mut Field
+    v453 = allocate -> &mut Field
+    v454 = allocate -> &mut Field
+    v455 = cast v217 as Field
+    v456 = cast v406 as Field
+    v457 = cast v205 as Field
+    v459 = mul v457, Field 256
+    v460 = add v455, v459
+    v461 = cast v396 as Field
+    v462 = mul v461, Field 256
+    v463 = add v456, v462
+    v464 = cast v193 as Field
+    v466 = mul v464, Field 65536
+    v467 = add v460, v466
+    v468 = cast v385 as Field
+    v469 = mul v468, Field 65536
+    v470 = add v463, v469
+    v471 = cast v181 as Field
+    v473 = mul v471, Field 16777216
+    v474 = add v467, v473
+    v475 = cast v373 as Field
+    v476 = mul v475, Field 16777216
+    v477 = add v470, v476
+    v478 = cast v169 as Field
+    v480 = mul v478, Field 4294967296
+    v481 = add v474, v480
+    v482 = cast v361 as Field
+    v483 = mul v482, Field 4294967296
+    v484 = add v477, v483
+    v485 = cast v157 as Field
+    v487 = mul v485, Field 1099511627776
+    v488 = add v481, v487
+    v489 = cast v349 as Field
+    v490 = mul v489, Field 1099511627776
+    v491 = add v484, v490
+    v492 = cast v145 as Field
+    v494 = mul v492, Field 281474976710656
+    v495 = add v488, v494
+    v496 = cast v337 as Field
+    v497 = mul v496, Field 281474976710656
+    v498 = add v491, v497
+    v499 = cast v133 as Field
+    v501 = mul v499, Field 72057594037927936
+    v502 = add v495, v501
+    v503 = cast v325 as Field
+    v504 = mul v503, Field 72057594037927936
+    v505 = add v498, v504
+    v506 = cast v121 as Field
+    v508 = mul v506, Field 18446744073709551616
+    v509 = add v502, v508
+    v510 = cast v313 as Field
+    v511 = mul v510, Field 18446744073709551616
+    v512 = add v505, v511
+    v513 = cast v109 as Field
+    v515 = mul v513, Field 4722366482869645213696
+    v516 = add v509, v515
+    v517 = cast v301 as Field
+    v518 = mul v517, Field 4722366482869645213696
+    v519 = add v512, v518
+    v520 = cast v97 as Field
+    v522 = mul v520, Field 1208925819614629174706176
+    v523 = add v516, v522
+    v524 = cast v289 as Field
+    v525 = mul v524, Field 1208925819614629174706176
+    v526 = add v519, v525
+    v527 = cast v85 as Field
+    v529 = mul v527, Field 309485009821345068724781056
+    v530 = add v523, v529
+    v531 = cast v277 as Field
+    v532 = mul v531, Field 309485009821345068724781056
+    v533 = add v526, v532
+    v534 = cast v73 as Field
+    v536 = mul v534, Field 79228162514264337593543950336
+    v537 = add v530, v536
+    v538 = cast v265 as Field
+    v539 = mul v538, Field 79228162514264337593543950336
+    v540 = add v533, v539
+    v541 = cast v61 as Field
+    v543 = mul v541, Field 20282409603651670423947251286016
+    v544 = add v537, v543
+    v545 = cast v253 as Field
+    v546 = mul v545, Field 20282409603651670423947251286016
+    v547 = add v540, v546
+    v548 = cast v49 as Field
+    v550 = mul v548, Field 5192296858534827628530496329220096
+    v551 = add v544, v550
+    v552 = cast v241 as Field
+    v553 = mul v552, Field 5192296858534827628530496329220096
+    v554 = add v547, v553
+    v555 = cast v43 as Field
+    v557 = mul v555, Field 1329227995784915872903807060280344576
+    v558 = add v551, v557
+    v559 = cast v229 as Field
+    v560 = mul v559, Field 1329227995784915872903807060280344576
+    v561 = add v554, v560
+    v563 = mul v558, Field 340282366920938463463374607431768211456
+    v564 = add v561, v563
+    v565 = allocate -> &mut Field
+    v567 = eq v4, Field 0
+    enable_side_effects v567
+    v568 = not v567
+    enable_side_effects v568
+    v570 = call f1(v4, Field 0) -> u1
+    v571 = mul v568, v570
+    enable_side_effects v571
+    v573, v574 = call f3(Field 0) -> (Field, Field)
+    v575 = cast v571 as Field
+    v576 = mul v573, v575
+    range_check v576 to 128 bits
+    v577 = mul v574, v575
+    range_check v577 to 128 bits
+    v578 = mul Field 340282366920938463463374607431768211456, v574
+    v579 = add v573, v578
+    v580 = eq Field 0, v579
+    v581 = mul v579, v575
+    constrain Field 0 == v581
+    v584 = call f2(Field 53438638232309528389504892708671455233, v573) -> u1
+    v585 = sub Field 53438638232309528389504892708671455233, v573
+    v587 = sub v585, Field 1
+    v588 = cast v584 as Field
+    v589 = mul v588, Field 340282366920938463463374607431768211456
+    v590 = add v587, v589
+    v592 = sub Field 64323764613183177041862057485226039389, v574
+    v593 = sub v592, v588
+    v594 = mul v590, v575
+    range_check v594 to 128 bits
+    v595 = mul v593, v575
+    range_check v595 to 128 bits
+    v597, v598 = call f3(v4) -> (Field, Field)
+    v599 = mul v597, v575
+    range_check v599 to 128 bits
+    v600 = mul v598, v575
+    range_check v600 to 128 bits
+    v601 = mul Field 340282366920938463463374607431768211456, v598
+    v602 = add v597, v601
+    v603 = eq v4, v602
+    v604 = mul v4, v575
+    v605 = mul v602, v575
+    constrain v604 == v605
+    v607 = call f2(Field 53438638232309528389504892708671455233, v597) -> u1
+    v608 = sub Field 53438638232309528389504892708671455233, v597
+    v609 = sub v608, Field 1
+    v610 = cast v607 as Field
+    v611 = mul v610, Field 340282366920938463463374607431768211456
+    v612 = add v609, v611
+    v613 = sub Field 64323764613183177041862057485226039389, v598
+    v614 = sub v613, v610
+    v615 = mul v612, v575
+    range_check v615 to 128 bits
+    v616 = mul v614, v575
+    range_check v616 to 128 bits
+    v618 = call f2(v573, v597) -> u1
+    v619 = sub v573, v597
+    v620 = sub v619, Field 1
+    v621 = cast v618 as Field
+    v622 = mul v621, Field 340282366920938463463374607431768211456
+    v623 = add v620, v622
+    v624 = sub v574, v598
+    v625 = sub v624, v621
+    v626 = mul v623, v575
+    range_check v626 to 128 bits
+    v627 = mul v625, v575
+    range_check v627 to 128 bits
+    v628 = not v570
+    v629 = mul v568, v628
+    enable_side_effects v629
+    v631, v632 = call f3(v4) -> (Field, Field)
+    v633 = cast v629 as Field
+    v634 = mul v631, v633
+    range_check v634 to 128 bits
+    v635 = mul v632, v633
+    range_check v635 to 128 bits
+    v636 = mul Field 340282366920938463463374607431768211456, v632
+    v637 = add v631, v636
+    v638 = eq v4, v637
+    v639 = mul v4, v633
+    v640 = mul v637, v633
+    constrain v639 == v640
+    v642 = call f2(Field 53438638232309528389504892708671455233, v631) -> u1
+    v643 = sub Field 53438638232309528389504892708671455233, v631
+    v644 = sub v643, Field 1
+    v645 = cast v642 as Field
+    v646 = mul v645, Field 340282366920938463463374607431768211456
+    v647 = add v644, v646
+    v648 = sub Field 64323764613183177041862057485226039389, v632
+    v649 = sub v648, v645
+    v650 = mul v647, v633
+    range_check v650 to 128 bits
+    v651 = mul v649, v633
+    range_check v651 to 128 bits
+    v653, v654 = call f3(Field 0) -> (Field, Field)
+    v655 = mul v653, v633
+    range_check v655 to 128 bits
+    v656 = mul v654, v633
+    range_check v656 to 128 bits
+    v657 = mul Field 340282366920938463463374607431768211456, v654
+    v658 = add v653, v657
+    v659 = eq Field 0, v658
+    v660 = mul v658, v633
+    constrain Field 0 == v660
+    v662 = call f2(Field 53438638232309528389504892708671455233, v653) -> u1
+    v663 = sub Field 53438638232309528389504892708671455233, v653
+    v664 = sub v663, Field 1
+    v665 = cast v662 as Field
+    v666 = mul v665, Field 340282366920938463463374607431768211456
+    v667 = add v664, v666
+    v668 = sub Field 64323764613183177041862057485226039389, v654
+    v669 = sub v668, v665
+    v670 = mul v667, v633
+    range_check v670 to 128 bits
+    v671 = mul v669, v633
+    range_check v671 to 128 bits
+    v673 = call f2(v631, v653) -> u1
+    v674 = sub v631, v653
+    v675 = sub v674, Field 1
+    v676 = cast v673 as Field
+    v677 = mul v676, Field 340282366920938463463374607431768211456
+    v678 = add v675, v677
+    v679 = sub v632, v654
+    v680 = sub v679, v676
+    v681 = mul v678, v633
+    range_check v681 to 128 bits
+    v682 = mul v680, v633
+    range_check v682 to 128 bits
+    enable_side_effects v629
+    v683 = not v629
+    v684 = cast v683 as Field
+    enable_side_effects u1 1
+    v685 = sub v633, v564
+    return v685
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After EnableSideEffectsIf removal:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = allocate -> &mut Field
+    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v40 = allocate -> &mut u1
+    v42 = array_get v9, index u32 0 -> u8
+    v43 = eq v42, u8 48
+    v44 = not v43
+    v45 = lt v42, u8 48
+    enable_side_effects v44
+    v46 = mul v45, v44
+    constrain v46 == v44
+    enable_side_effects v43
+    v48 = array_get v9, index u32 1 -> u8
+    v49 = eq v48, u8 100
+    v50 = not v49
+    v51 = mul v43, v50
+    v52 = lt v48, u8 100
+    enable_side_effects v51
+    v53 = mul v52, v51
+    constrain v53 == v51
+    v54 = not v51
+    v55 = mul v54, v44
+    v56 = unchecked_add v51, v55
+    v57 = mul v43, v49
+    enable_side_effects u1 1
+    v59 = not v56
+    enable_side_effects v59
+    v61 = array_get v9, index u32 2 -> u8
+    v62 = eq v61, u8 78
+    v63 = not v62
+    v64 = mul v59, v63
+    v65 = lt v61, u8 78
+    enable_side_effects v64
+    v66 = mul v65, v64
+    constrain v66 == v64
+    v67 = not v64
+    v68 = mul v67, v56
+    v69 = unchecked_add v64, v68
+    v70 = mul v59, v62
+    enable_side_effects u1 1
+    v71 = not v69
+    enable_side_effects v71
+    v73 = array_get v9, index u32 3 -> u8
+    v74 = eq v73, u8 114
+    v75 = not v74
+    v76 = mul v71, v75
+    v77 = lt v73, u8 114
+    enable_side_effects v76
+    v78 = mul v77, v76
+    constrain v78 == v76
+    v79 = not v76
+    v80 = mul v79, v69
+    v81 = unchecked_add v76, v80
+    v82 = mul v71, v74
+    enable_side_effects u1 1
+    v83 = not v81
+    enable_side_effects v83
+    v85 = array_get v9, index u32 4 -> u8
+    v86 = eq v85, u8 225
+    v87 = not v86
+    v88 = mul v83, v87
+    v89 = lt v85, u8 225
+    enable_side_effects v88
+    v90 = mul v89, v88
+    constrain v90 == v88
+    v91 = not v88
+    v92 = mul v91, v81
+    v93 = unchecked_add v88, v92
+    v94 = mul v83, v86
+    enable_side_effects u1 1
+    v95 = not v93
+    enable_side_effects v95
+    v97 = array_get v9, index u32 5 -> u8
+    v98 = eq v97, u8 49
+    v99 = not v98
+    v100 = mul v95, v99
+    v101 = lt v97, u8 49
+    enable_side_effects v100
+    v102 = mul v101, v100
+    constrain v102 == v100
+    v103 = not v100
+    v104 = mul v103, v93
+    v105 = unchecked_add v100, v104
+    v106 = mul v95, v98
+    enable_side_effects u1 1
+    v107 = not v105
+    enable_side_effects v107
+    v109 = array_get v9, index u32 6 -> u8
+    v110 = eq v109, u8 160
+    v111 = not v110
+    v112 = mul v107, v111
+    v113 = lt v109, u8 160
+    enable_side_effects v112
+    v114 = mul v113, v112
+    constrain v114 == v112
+    v115 = not v112
+    v116 = mul v115, v105
+    v117 = unchecked_add v112, v116
+    v118 = mul v107, v110
+    enable_side_effects u1 1
+    v119 = not v117
+    enable_side_effects v119
+    v121 = array_get v9, index u32 7 -> u8
+    v122 = eq v121, u8 41
+    v123 = not v122
+    v124 = mul v119, v123
+    v125 = lt v121, u8 41
+    enable_side_effects v124
+    v126 = mul v125, v124
+    constrain v126 == v124
+    v127 = not v124
+    v128 = mul v127, v117
+    v129 = unchecked_add v124, v128
+    v130 = mul v119, v122
+    enable_side_effects u1 1
+    v131 = not v129
+    enable_side_effects v131
+    v133 = array_get v9, index u32 8 -> u8
+    v134 = eq v133, u8 184
+    v135 = not v134
+    v136 = mul v131, v135
+    v137 = lt v133, u8 184
+    enable_side_effects v136
+    v138 = mul v137, v136
+    constrain v138 == v136
+    v139 = not v136
+    v140 = mul v139, v129
+    v141 = unchecked_add v136, v140
+    v142 = mul v131, v134
+    enable_side_effects u1 1
+    v143 = not v141
+    enable_side_effects v143
+    v145 = array_get v9, index u32 9 -> u8
+    v146 = eq v145, u8 80
+    v147 = not v146
+    v148 = mul v143, v147
+    v149 = lt v145, u8 80
+    enable_side_effects v148
+    v150 = mul v149, v148
+    constrain v150 == v148
+    v151 = not v148
+    v152 = mul v151, v141
+    v153 = unchecked_add v148, v152
+    v154 = mul v143, v146
+    enable_side_effects u1 1
+    v155 = not v153
+    enable_side_effects v155
+    v157 = array_get v9, index u32 10 -> u8
+    v158 = eq v157, u8 69
+    v159 = not v158
+    v160 = mul v155, v159
+    v161 = lt v157, u8 69
+    enable_side_effects v160
+    v162 = mul v161, v160
+    constrain v162 == v160
+    v163 = not v160
+    v164 = mul v163, v153
+    v165 = unchecked_add v160, v164
+    v166 = mul v155, v158
+    enable_side_effects u1 1
+    v167 = not v165
+    enable_side_effects v167
+    v169 = array_get v9, index u32 11 -> u8
+    v170 = eq v169, u8 182
+    v171 = not v170
+    v172 = mul v167, v171
+    v173 = lt v169, u8 182
+    enable_side_effects v172
+    v174 = mul v173, v172
+    constrain v174 == v172
+    v175 = not v172
+    v176 = mul v175, v165
+    v177 = unchecked_add v172, v176
+    v178 = mul v167, v170
+    enable_side_effects u1 1
+    v179 = not v177
+    enable_side_effects v179
+    v181 = array_get v9, index u32 12 -> u8
+    v182 = eq v181, u8 129
+    v183 = not v182
+    v184 = mul v179, v183
+    v185 = lt v181, u8 129
+    enable_side_effects v184
+    v186 = mul v185, v184
+    constrain v186 == v184
+    v187 = not v184
+    v188 = mul v187, v177
+    v189 = unchecked_add v184, v188
+    v190 = mul v179, v182
+    enable_side_effects u1 1
+    v191 = not v189
+    enable_side_effects v191
+    v193 = array_get v9, index u32 13 -> u8
+    v194 = eq v193, u8 129
+    v195 = not v194
+    v196 = mul v191, v195
+    v197 = lt v193, u8 129
+    enable_side_effects v196
+    v198 = mul v197, v196
+    constrain v198 == v196
+    v199 = not v196
+    v200 = mul v199, v189
+    v201 = unchecked_add v196, v200
+    v202 = mul v191, v194
+    enable_side_effects u1 1
+    v203 = not v201
+    enable_side_effects v203
+    v205 = array_get v9, index u32 14 -> u8
+    v206 = eq v205, u8 88
+    v207 = not v206
+    v208 = mul v203, v207
+    v209 = lt v205, u8 88
+    enable_side_effects v208
+    v210 = mul v209, v208
+    constrain v210 == v208
+    v211 = not v208
+    v212 = mul v211, v201
+    v213 = unchecked_add v208, v212
+    v214 = mul v203, v206
+    enable_side_effects u1 1
+    v215 = not v213
+    enable_side_effects v215
+    v217 = array_get v9, index u32 15 -> u8
+    v218 = eq v217, u8 93
+    v219 = not v218
+    v220 = mul v215, v219
+    v221 = lt v217, u8 93
+    enable_side_effects v220
+    v222 = mul v221, v220
+    constrain v222 == v220
+    v223 = not v220
+    v224 = mul v223, v213
+    v225 = unchecked_add v220, v224
+    v226 = mul v215, v218
+    enable_side_effects u1 1
+    v227 = not v225
+    enable_side_effects v227
+    v229 = array_get v9, index u32 16 -> u8
+    v230 = eq v229, u8 40
+    v231 = not v230
+    v232 = mul v227, v231
+    v233 = lt v229, u8 40
+    enable_side_effects v232
+    v234 = mul v233, v232
+    constrain v234 == v232
+    v235 = not v232
+    v236 = mul v235, v225
+    v237 = unchecked_add v232, v236
+    v238 = mul v227, v230
+    enable_side_effects u1 1
+    v239 = not v237
+    enable_side_effects v239
+    v241 = array_get v9, index u32 17 -> u8
+    v242 = eq v241, u8 51
+    v243 = not v242
+    v244 = mul v239, v243
+    v245 = lt v241, u8 51
+    enable_side_effects v244
+    v246 = mul v245, v244
+    constrain v246 == v244
+    v247 = not v244
+    v248 = mul v247, v237
+    v249 = unchecked_add v244, v248
+    v250 = mul v239, v242
+    enable_side_effects u1 1
+    v251 = not v249
+    enable_side_effects v251
+    v253 = array_get v9, index u32 18 -> u8
+    v254 = eq v253, u8 232
+    v255 = not v254
+    v256 = mul v251, v255
+    v257 = lt v253, u8 232
+    enable_side_effects v256
+    v258 = mul v257, v256
+    constrain v258 == v256
+    v259 = not v256
+    v260 = mul v259, v249
+    v261 = unchecked_add v256, v260
+    v262 = mul v251, v254
+    enable_side_effects u1 1
+    v263 = not v261
+    enable_side_effects v263
+    v265 = array_get v9, index u32 19 -> u8
+    v266 = eq v265, u8 72
+    v267 = not v266
+    v268 = mul v263, v267
+    v269 = lt v265, u8 72
+    enable_side_effects v268
+    v270 = mul v269, v268
+    constrain v270 == v268
+    v271 = not v268
+    v272 = mul v271, v261
+    v273 = unchecked_add v268, v272
+    v274 = mul v263, v266
+    enable_side_effects u1 1
+    v275 = not v273
+    enable_side_effects v275
+    v277 = array_get v9, index u32 20 -> u8
+    v278 = eq v277, u8 121
+    v279 = not v278
+    v280 = mul v275, v279
+    v281 = lt v277, u8 121
+    enable_side_effects v280
+    v282 = mul v281, v280
+    constrain v282 == v280
+    v283 = not v280
+    v284 = mul v283, v273
+    v285 = unchecked_add v280, v284
+    v286 = mul v275, v278
+    enable_side_effects u1 1
+    v287 = not v285
+    enable_side_effects v287
+    v289 = array_get v9, index u32 21 -> u8
+    v290 = eq v289, u8 185
+    v291 = not v290
+    v292 = mul v287, v291
+    v293 = lt v289, u8 185
+    enable_side_effects v292
+    v294 = mul v293, v292
+    constrain v294 == v292
+    v295 = not v292
+    v296 = mul v295, v285
+    v297 = unchecked_add v292, v296
+    v298 = mul v287, v290
+    enable_side_effects u1 1
+    v299 = not v297
+    enable_side_effects v299
+    v301 = array_get v9, index u32 22 -> u8
+    v302 = eq v301, u8 112
+    v303 = not v302
+    v304 = mul v299, v303
+    v305 = lt v301, u8 112
+    enable_side_effects v304
+    v306 = mul v305, v304
+    constrain v306 == v304
+    v307 = not v304
+    v308 = mul v307, v297
+    v309 = unchecked_add v304, v308
+    v310 = mul v299, v302
+    enable_side_effects u1 1
+    v311 = not v309
+    enable_side_effects v311
+    v313 = array_get v9, index u32 23 -> u8
+    v314 = eq v313, u8 145
+    v315 = not v314
+    v316 = mul v311, v315
+    v317 = lt v313, u8 145
+    enable_side_effects v316
+    v318 = mul v317, v316
+    constrain v318 == v316
+    v319 = not v316
+    v320 = mul v319, v309
+    v321 = unchecked_add v316, v320
+    v322 = mul v311, v314
+    enable_side_effects u1 1
+    v323 = not v321
+    enable_side_effects v323
+    v325 = array_get v9, index u32 24 -> u8
+    v326 = eq v325, u8 67
+    v327 = not v326
+    v328 = mul v323, v327
+    v329 = lt v325, u8 67
+    enable_side_effects v328
+    v330 = mul v329, v328
+    constrain v330 == v328
+    v331 = not v328
+    v332 = mul v331, v321
+    v333 = unchecked_add v328, v332
+    v334 = mul v323, v326
+    enable_side_effects u1 1
+    v335 = not v333
+    enable_side_effects v335
+    v337 = array_get v9, index u32 25 -> u8
+    v338 = eq v337, u8 225
+    v339 = not v338
+    v340 = mul v335, v339
+    v341 = lt v337, u8 225
+    enable_side_effects v340
+    v342 = mul v341, v340
+    constrain v342 == v340
+    v343 = not v340
+    v344 = mul v343, v333
+    v345 = unchecked_add v340, v344
+    v346 = mul v335, v338
+    enable_side_effects u1 1
+    v347 = not v345
+    enable_side_effects v347
+    v349 = array_get v9, index u32 26 -> u8
+    v350 = eq v349, u8 245
+    v351 = not v350
+    v352 = mul v347, v351
+    v353 = lt v349, u8 245
+    enable_side_effects v352
+    v354 = mul v353, v352
+    constrain v354 == v352
+    v355 = not v352
+    v356 = mul v355, v345
+    v357 = unchecked_add v352, v356
+    v358 = mul v347, v350
+    enable_side_effects u1 1
+    v359 = not v357
+    enable_side_effects v359
+    v361 = array_get v9, index u32 27 -> u8
+    v362 = eq v361, u8 147
+    v363 = not v362
+    v364 = mul v359, v363
+    v365 = lt v361, u8 147
+    enable_side_effects v364
+    v366 = mul v365, v364
+    constrain v366 == v364
+    v367 = not v364
+    v368 = mul v367, v357
+    v369 = unchecked_add v364, v368
+    v370 = mul v359, v362
+    enable_side_effects u1 1
+    v371 = not v369
+    enable_side_effects v371
+    v373 = array_get v9, index u32 28 -> u8
+    v374 = eq v373, u8 240
+    v375 = not v374
+    v376 = mul v371, v375
+    v377 = lt v373, u8 240
+    enable_side_effects v376
+    v378 = mul v377, v376
+    constrain v378 == v376
+    v379 = not v376
+    v380 = mul v379, v369
+    v381 = unchecked_add v376, v380
+    v382 = mul v371, v374
+    enable_side_effects u1 1
+    v383 = not v381
+    enable_side_effects v383
+    v385 = array_get v9, index u32 29 -> u8
+    v386 = eq v385, u8 0
+    v387 = not v386
+    v388 = mul v383, v387
+    constrain u1 0 == v388
+    v390 = not v388
+    enable_side_effects v388
+    v391 = mul v390, v381
+    v392 = unchecked_add v388, v391
+    v393 = mul v383, v386
+    enable_side_effects u1 1
+    v394 = not v392
+    enable_side_effects v394
+    v396 = array_get v9, index u32 30 -> u8
+    v397 = eq v396, u8 0
+    v398 = not v397
+    v399 = mul v394, v398
+    constrain u1 0 == v399
+    v400 = not v399
+    enable_side_effects v399
+    v401 = mul v400, v392
+    v402 = unchecked_add v399, v401
+    v403 = mul v394, v397
+    enable_side_effects u1 1
+    v404 = not v402
+    enable_side_effects v404
+    v406 = array_get v9, index u32 31 -> u8
+    v407 = eq v406, u8 1
+    v408 = not v407
+    v409 = mul v404, v408
+    v410 = eq v406, u8 0
+    v411 = cast v409 as u8
+    enable_side_effects v409
+    v412 = unchecked_mul v406, v411
+    constrain v412 == u8 0
+    v413 = not v409
+    v414 = mul v413, v402
+    v415 = unchecked_add v409, v414
+    v416 = mul v404, v407
+    enable_side_effects u1 1
+    constrain v415 == u1 1
+    v417 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v418 = allocate -> &mut u1
+    v419 = allocate -> &mut [u8; 32]
+    v420 = make_array [v42, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v421 = make_array [v42, v48, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v422 = make_array [v42, v48, v61, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v423 = make_array [v42, v48, v61, v73, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v424 = make_array [v42, v48, v61, v73, v85, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v425 = make_array [v42, v48, v61, v73, v85, v97, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v426 = make_array [v42, v48, v61, v73, v85, v97, v109, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v427 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v428 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v429 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v430 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v431 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v432 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v433 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v434 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v435 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v436 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v437 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v438 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v439 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v440 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v441 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v442 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v443 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v444 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v445 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v446 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v447 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v448 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, u8 0, u8 0, u8 0] : [u8; 32]
+    v449 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, u8 0, u8 0] : [u8; 32]
+    v450 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v396, u8 0] : [u8; 32]
+    v451 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v396, v406] : [u8; 32]
+    v452 = allocate -> &mut Field
+    v453 = allocate -> &mut Field
+    v454 = allocate -> &mut Field
+    v455 = cast v217 as Field
+    v456 = cast v406 as Field
+    v457 = cast v205 as Field
+    v459 = mul v457, Field 256
+    v460 = add v455, v459
+    v461 = cast v396 as Field
+    v462 = mul v461, Field 256
+    v463 = add v456, v462
+    v464 = cast v193 as Field
+    v466 = mul v464, Field 65536
+    v467 = add v460, v466
+    v468 = cast v385 as Field
+    v469 = mul v468, Field 65536
+    v470 = add v463, v469
+    v471 = cast v181 as Field
+    v473 = mul v471, Field 16777216
+    v474 = add v467, v473
+    v475 = cast v373 as Field
+    v476 = mul v475, Field 16777216
+    v477 = add v470, v476
+    v478 = cast v169 as Field
+    v480 = mul v478, Field 4294967296
+    v481 = add v474, v480
+    v482 = cast v361 as Field
+    v483 = mul v482, Field 4294967296
+    v484 = add v477, v483
+    v485 = cast v157 as Field
+    v487 = mul v485, Field 1099511627776
+    v488 = add v481, v487
+    v489 = cast v349 as Field
+    v490 = mul v489, Field 1099511627776
+    v491 = add v484, v490
+    v492 = cast v145 as Field
+    v494 = mul v492, Field 281474976710656
+    v495 = add v488, v494
+    v496 = cast v337 as Field
+    v497 = mul v496, Field 281474976710656
+    v498 = add v491, v497
+    v499 = cast v133 as Field
+    v501 = mul v499, Field 72057594037927936
+    v502 = add v495, v501
+    v503 = cast v325 as Field
+    v504 = mul v503, Field 72057594037927936
+    v505 = add v498, v504
+    v506 = cast v121 as Field
+    v508 = mul v506, Field 18446744073709551616
+    v509 = add v502, v508
+    v510 = cast v313 as Field
+    v511 = mul v510, Field 18446744073709551616
+    v512 = add v505, v511
+    v513 = cast v109 as Field
+    v515 = mul v513, Field 4722366482869645213696
+    v516 = add v509, v515
+    v517 = cast v301 as Field
+    v518 = mul v517, Field 4722366482869645213696
+    v519 = add v512, v518
+    v520 = cast v97 as Field
+    v522 = mul v520, Field 1208925819614629174706176
+    v523 = add v516, v522
+    v524 = cast v289 as Field
+    v525 = mul v524, Field 1208925819614629174706176
+    v526 = add v519, v525
+    v527 = cast v85 as Field
+    v529 = mul v527, Field 309485009821345068724781056
+    v530 = add v523, v529
+    v531 = cast v277 as Field
+    v532 = mul v531, Field 309485009821345068724781056
+    v533 = add v526, v532
+    v534 = cast v73 as Field
+    v536 = mul v534, Field 79228162514264337593543950336
+    v537 = add v530, v536
+    v538 = cast v265 as Field
+    v539 = mul v538, Field 79228162514264337593543950336
+    v540 = add v533, v539
+    v541 = cast v61 as Field
+    v543 = mul v541, Field 20282409603651670423947251286016
+    v544 = add v537, v543
+    v545 = cast v253 as Field
+    v546 = mul v545, Field 20282409603651670423947251286016
+    v547 = add v540, v546
+    v548 = cast v48 as Field
+    v550 = mul v548, Field 5192296858534827628530496329220096
+    v551 = add v544, v550
+    v552 = cast v241 as Field
+    v553 = mul v552, Field 5192296858534827628530496329220096
+    v554 = add v547, v553
+    v555 = cast v42 as Field
+    v557 = mul v555, Field 1329227995784915872903807060280344576
+    v558 = add v551, v557
+    v559 = cast v229 as Field
+    v560 = mul v559, Field 1329227995784915872903807060280344576
+    v561 = add v554, v560
+    v563 = mul v558, Field 340282366920938463463374607431768211456
+    v564 = add v561, v563
+    v565 = allocate -> &mut Field
+    v567 = eq v4, Field 0
+    v568 = not v567
+    enable_side_effects v568
+    v570 = call f1(v4, Field 0) -> u1
+    v571 = mul v568, v570
+    enable_side_effects v571
+    v573, v574 = call f3(Field 0) -> (Field, Field)
+    v575 = cast v571 as Field
+    v576 = mul v573, v575
+    range_check v576 to 128 bits
+    v577 = mul v574, v575
+    range_check v577 to 128 bits
+    v578 = mul Field 340282366920938463463374607431768211456, v574
+    v579 = add v573, v578
+    v580 = eq Field 0, v579
+    v581 = mul v579, v575
+    constrain Field 0 == v581
+    v584 = call f2(Field 53438638232309528389504892708671455233, v573) -> u1
+    v585 = sub Field 53438638232309528389504892708671455233, v573
+    v587 = sub v585, Field 1
+    v588 = cast v584 as Field
+    v589 = mul v588, Field 340282366920938463463374607431768211456
+    v590 = add v587, v589
+    v592 = sub Field 64323764613183177041862057485226039389, v574
+    v593 = sub v592, v588
+    v594 = mul v590, v575
+    range_check v594 to 128 bits
+    v595 = mul v593, v575
+    range_check v595 to 128 bits
+    v597, v598 = call f3(v4) -> (Field, Field)
+    v599 = mul v597, v575
+    range_check v599 to 128 bits
+    v600 = mul v598, v575
+    range_check v600 to 128 bits
+    v601 = mul Field 340282366920938463463374607431768211456, v598
+    v602 = add v597, v601
+    v603 = eq v4, v602
+    v604 = mul v4, v575
+    v605 = mul v602, v575
+    constrain v604 == v605
+    v607 = call f2(Field 53438638232309528389504892708671455233, v597) -> u1
+    v608 = sub Field 53438638232309528389504892708671455233, v597
+    v609 = sub v608, Field 1
+    v610 = cast v607 as Field
+    v611 = mul v610, Field 340282366920938463463374607431768211456
+    v612 = add v609, v611
+    v613 = sub Field 64323764613183177041862057485226039389, v598
+    v614 = sub v613, v610
+    v615 = mul v612, v575
+    range_check v615 to 128 bits
+    v616 = mul v614, v575
+    range_check v616 to 128 bits
+    v618 = call f2(v573, v597) -> u1
+    v619 = sub v573, v597
+    v620 = sub v619, Field 1
+    v621 = cast v618 as Field
+    v622 = mul v621, Field 340282366920938463463374607431768211456
+    v623 = add v620, v622
+    v624 = sub v574, v598
+    v625 = sub v624, v621
+    v626 = mul v623, v575
+    range_check v626 to 128 bits
+    v627 = mul v625, v575
+    range_check v627 to 128 bits
+    v628 = not v570
+    v629 = mul v568, v628
+    enable_side_effects v629
+    v631, v632 = call f3(v4) -> (Field, Field)
+    v633 = cast v629 as Field
+    v634 = mul v631, v633
+    range_check v634 to 128 bits
+    v635 = mul v632, v633
+    range_check v635 to 128 bits
+    v636 = mul Field 340282366920938463463374607431768211456, v632
+    v637 = add v631, v636
+    v638 = eq v4, v637
+    v639 = mul v4, v633
+    v640 = mul v637, v633
+    constrain v639 == v640
+    v642 = call f2(Field 53438638232309528389504892708671455233, v631) -> u1
+    v643 = sub Field 53438638232309528389504892708671455233, v631
+    v644 = sub v643, Field 1
+    v645 = cast v642 as Field
+    v646 = mul v645, Field 340282366920938463463374607431768211456
+    v647 = add v644, v646
+    v648 = sub Field 64323764613183177041862057485226039389, v632
+    v649 = sub v648, v645
+    v650 = mul v647, v633
+    range_check v650 to 128 bits
+    v651 = mul v649, v633
+    range_check v651 to 128 bits
+    v653, v654 = call f3(Field 0) -> (Field, Field)
+    v655 = mul v653, v633
+    range_check v655 to 128 bits
+    v656 = mul v654, v633
+    range_check v656 to 128 bits
+    v657 = mul Field 340282366920938463463374607431768211456, v654
+    v658 = add v653, v657
+    v659 = eq Field 0, v658
+    v660 = mul v658, v633
+    constrain Field 0 == v660
+    v662 = call f2(Field 53438638232309528389504892708671455233, v653) -> u1
+    v663 = sub Field 53438638232309528389504892708671455233, v653
+    v664 = sub v663, Field 1
+    v665 = cast v662 as Field
+    v666 = mul v665, Field 340282366920938463463374607431768211456
+    v667 = add v664, v666
+    v668 = sub Field 64323764613183177041862057485226039389, v654
+    v669 = sub v668, v665
+    v670 = mul v667, v633
+    range_check v670 to 128 bits
+    v671 = mul v669, v633
+    range_check v671 to 128 bits
+    v673 = call f2(v631, v653) -> u1
+    v674 = sub v631, v653
+    v675 = sub v674, Field 1
+    v676 = cast v673 as Field
+    v677 = mul v676, Field 340282366920938463463374607431768211456
+    v678 = add v675, v677
+    v679 = sub v632, v654
+    v680 = sub v679, v676
+    v681 = mul v678, v633
+    range_check v681 to 128 bits
+    v682 = mul v680, v633
+    range_check v682 to 128 bits
+    v683 = not v629
+    v684 = cast v683 as Field
+    enable_side_effects u1 1
+    v685 = sub v633, v564
+    return v685
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Constraint Folding:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = allocate -> &mut Field
+    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v40 = allocate -> &mut u1
+    v42 = array_get v9, index u32 0 -> u8
+    v43 = eq v42, u8 48
+    v44 = not v43
+    v45 = lt v42, u8 48
+    enable_side_effects v44
+    v46 = mul v45, v44
+    constrain v46 == v44
+    enable_side_effects v43
+    v48 = array_get v9, index u32 1 -> u8
+    v49 = eq v48, u8 100
+    v50 = not v49
+    v51 = mul v43, v50
+    v52 = lt v48, u8 100
+    enable_side_effects v51
+    v53 = mul v52, v51
+    constrain v53 == v51
+    v54 = not v51
+    v55 = mul v54, v44
+    v56 = unchecked_add v51, v55
+    v57 = mul v43, v49
+    enable_side_effects u1 1
+    v59 = not v56
+    enable_side_effects v59
+    v61 = array_get v9, index u32 2 -> u8
+    v62 = eq v61, u8 78
+    v63 = not v62
+    v64 = mul v59, v63
+    v65 = lt v61, u8 78
+    enable_side_effects v64
+    v66 = mul v65, v64
+    constrain v66 == v64
+    v67 = not v64
+    v68 = mul v67, v56
+    v69 = unchecked_add v64, v68
+    v70 = mul v59, v62
+    enable_side_effects u1 1
+    v71 = not v69
+    enable_side_effects v71
+    v73 = array_get v9, index u32 3 -> u8
+    v74 = eq v73, u8 114
+    v75 = not v74
+    v76 = mul v71, v75
+    v77 = lt v73, u8 114
+    enable_side_effects v76
+    v78 = mul v77, v76
+    constrain v78 == v76
+    v79 = not v76
+    v80 = mul v79, v69
+    v81 = unchecked_add v76, v80
+    v82 = mul v71, v74
+    enable_side_effects u1 1
+    v83 = not v81
+    enable_side_effects v83
+    v85 = array_get v9, index u32 4 -> u8
+    v86 = eq v85, u8 225
+    v87 = not v86
+    v88 = mul v83, v87
+    v89 = lt v85, u8 225
+    enable_side_effects v88
+    v90 = mul v89, v88
+    constrain v90 == v88
+    v91 = not v88
+    v92 = mul v91, v81
+    v93 = unchecked_add v88, v92
+    v94 = mul v83, v86
+    enable_side_effects u1 1
+    v95 = not v93
+    enable_side_effects v95
+    v97 = array_get v9, index u32 5 -> u8
+    v98 = eq v97, u8 49
+    v99 = not v98
+    v100 = mul v95, v99
+    v101 = lt v97, u8 49
+    enable_side_effects v100
+    v102 = mul v101, v100
+    constrain v102 == v100
+    v103 = not v100
+    v104 = mul v103, v93
+    v105 = unchecked_add v100, v104
+    v106 = mul v95, v98
+    enable_side_effects u1 1
+    v107 = not v105
+    enable_side_effects v107
+    v109 = array_get v9, index u32 6 -> u8
+    v110 = eq v109, u8 160
+    v111 = not v110
+    v112 = mul v107, v111
+    v113 = lt v109, u8 160
+    enable_side_effects v112
+    v114 = mul v113, v112
+    constrain v114 == v112
+    v115 = not v112
+    v116 = mul v115, v105
+    v117 = unchecked_add v112, v116
+    v118 = mul v107, v110
+    enable_side_effects u1 1
+    v119 = not v117
+    enable_side_effects v119
+    v121 = array_get v9, index u32 7 -> u8
+    v122 = eq v121, u8 41
+    v123 = not v122
+    v124 = mul v119, v123
+    v125 = lt v121, u8 41
+    enable_side_effects v124
+    v126 = mul v125, v124
+    constrain v126 == v124
+    v127 = not v124
+    v128 = mul v127, v117
+    v129 = unchecked_add v124, v128
+    v130 = mul v119, v122
+    enable_side_effects u1 1
+    v131 = not v129
+    enable_side_effects v131
+    v133 = array_get v9, index u32 8 -> u8
+    v134 = eq v133, u8 184
+    v135 = not v134
+    v136 = mul v131, v135
+    v137 = lt v133, u8 184
+    enable_side_effects v136
+    v138 = mul v137, v136
+    constrain v138 == v136
+    v139 = not v136
+    v140 = mul v139, v129
+    v141 = unchecked_add v136, v140
+    v142 = mul v131, v134
+    enable_side_effects u1 1
+    v143 = not v141
+    enable_side_effects v143
+    v145 = array_get v9, index u32 9 -> u8
+    v146 = eq v145, u8 80
+    v147 = not v146
+    v148 = mul v143, v147
+    v149 = lt v145, u8 80
+    enable_side_effects v148
+    v150 = mul v149, v148
+    constrain v150 == v148
+    v151 = not v148
+    v152 = mul v151, v141
+    v153 = unchecked_add v148, v152
+    v154 = mul v143, v146
+    enable_side_effects u1 1
+    v155 = not v153
+    enable_side_effects v155
+    v157 = array_get v9, index u32 10 -> u8
+    v158 = eq v157, u8 69
+    v159 = not v158
+    v160 = mul v155, v159
+    v161 = lt v157, u8 69
+    enable_side_effects v160
+    v162 = mul v161, v160
+    constrain v162 == v160
+    v163 = not v160
+    v164 = mul v163, v153
+    v165 = unchecked_add v160, v164
+    v166 = mul v155, v158
+    enable_side_effects u1 1
+    v167 = not v165
+    enable_side_effects v167
+    v169 = array_get v9, index u32 11 -> u8
+    v170 = eq v169, u8 182
+    v171 = not v170
+    v172 = mul v167, v171
+    v173 = lt v169, u8 182
+    enable_side_effects v172
+    v174 = mul v173, v172
+    constrain v174 == v172
+    v175 = not v172
+    v176 = mul v175, v165
+    v177 = unchecked_add v172, v176
+    v178 = mul v167, v170
+    enable_side_effects u1 1
+    v179 = not v177
+    enable_side_effects v179
+    v181 = array_get v9, index u32 12 -> u8
+    v182 = eq v181, u8 129
+    v183 = not v182
+    v184 = mul v179, v183
+    v185 = lt v181, u8 129
+    enable_side_effects v184
+    v186 = mul v185, v184
+    constrain v186 == v184
+    v187 = not v184
+    v188 = mul v187, v177
+    v189 = unchecked_add v184, v188
+    v190 = mul v179, v182
+    enable_side_effects u1 1
+    v191 = not v189
+    enable_side_effects v191
+    v193 = array_get v9, index u32 13 -> u8
+    v194 = eq v193, u8 129
+    v195 = not v194
+    v196 = mul v191, v195
+    v197 = lt v193, u8 129
+    enable_side_effects v196
+    v198 = mul v197, v196
+    constrain v198 == v196
+    v199 = not v196
+    v200 = mul v199, v189
+    v201 = unchecked_add v196, v200
+    v202 = mul v191, v194
+    enable_side_effects u1 1
+    v203 = not v201
+    enable_side_effects v203
+    v205 = array_get v9, index u32 14 -> u8
+    v206 = eq v205, u8 88
+    v207 = not v206
+    v208 = mul v203, v207
+    v209 = lt v205, u8 88
+    enable_side_effects v208
+    v210 = mul v209, v208
+    constrain v210 == v208
+    v211 = not v208
+    v212 = mul v211, v201
+    v213 = unchecked_add v208, v212
+    v214 = mul v203, v206
+    enable_side_effects u1 1
+    v215 = not v213
+    enable_side_effects v215
+    v217 = array_get v9, index u32 15 -> u8
+    v218 = eq v217, u8 93
+    v219 = not v218
+    v220 = mul v215, v219
+    v221 = lt v217, u8 93
+    enable_side_effects v220
+    v222 = mul v221, v220
+    constrain v222 == v220
+    v223 = not v220
+    v224 = mul v223, v213
+    v225 = unchecked_add v220, v224
+    v226 = mul v215, v218
+    enable_side_effects u1 1
+    v227 = not v225
+    enable_side_effects v227
+    v229 = array_get v9, index u32 16 -> u8
+    v230 = eq v229, u8 40
+    v231 = not v230
+    v232 = mul v227, v231
+    v233 = lt v229, u8 40
+    enable_side_effects v232
+    v234 = mul v233, v232
+    constrain v234 == v232
+    v235 = not v232
+    v236 = mul v235, v225
+    v237 = unchecked_add v232, v236
+    v238 = mul v227, v230
+    enable_side_effects u1 1
+    v239 = not v237
+    enable_side_effects v239
+    v241 = array_get v9, index u32 17 -> u8
+    v242 = eq v241, u8 51
+    v243 = not v242
+    v244 = mul v239, v243
+    v245 = lt v241, u8 51
+    enable_side_effects v244
+    v246 = mul v245, v244
+    constrain v246 == v244
+    v247 = not v244
+    v248 = mul v247, v237
+    v249 = unchecked_add v244, v248
+    v250 = mul v239, v242
+    enable_side_effects u1 1
+    v251 = not v249
+    enable_side_effects v251
+    v253 = array_get v9, index u32 18 -> u8
+    v254 = eq v253, u8 232
+    v255 = not v254
+    v256 = mul v251, v255
+    v257 = lt v253, u8 232
+    enable_side_effects v256
+    v258 = mul v257, v256
+    constrain v258 == v256
+    v259 = not v256
+    v260 = mul v259, v249
+    v261 = unchecked_add v256, v260
+    v262 = mul v251, v254
+    enable_side_effects u1 1
+    v263 = not v261
+    enable_side_effects v263
+    v265 = array_get v9, index u32 19 -> u8
+    v266 = eq v265, u8 72
+    v267 = not v266
+    v268 = mul v263, v267
+    v269 = lt v265, u8 72
+    enable_side_effects v268
+    v270 = mul v269, v268
+    constrain v270 == v268
+    v271 = not v268
+    v272 = mul v271, v261
+    v273 = unchecked_add v268, v272
+    v274 = mul v263, v266
+    enable_side_effects u1 1
+    v275 = not v273
+    enable_side_effects v275
+    v277 = array_get v9, index u32 20 -> u8
+    v278 = eq v277, u8 121
+    v279 = not v278
+    v280 = mul v275, v279
+    v281 = lt v277, u8 121
+    enable_side_effects v280
+    v282 = mul v281, v280
+    constrain v282 == v280
+    v283 = not v280
+    v284 = mul v283, v273
+    v285 = unchecked_add v280, v284
+    v286 = mul v275, v278
+    enable_side_effects u1 1
+    v287 = not v285
+    enable_side_effects v287
+    v289 = array_get v9, index u32 21 -> u8
+    v290 = eq v289, u8 185
+    v291 = not v290
+    v292 = mul v287, v291
+    v293 = lt v289, u8 185
+    enable_side_effects v292
+    v294 = mul v293, v292
+    constrain v294 == v292
+    v295 = not v292
+    v296 = mul v295, v285
+    v297 = unchecked_add v292, v296
+    v298 = mul v287, v290
+    enable_side_effects u1 1
+    v299 = not v297
+    enable_side_effects v299
+    v301 = array_get v9, index u32 22 -> u8
+    v302 = eq v301, u8 112
+    v303 = not v302
+    v304 = mul v299, v303
+    v305 = lt v301, u8 112
+    enable_side_effects v304
+    v306 = mul v305, v304
+    constrain v306 == v304
+    v307 = not v304
+    v308 = mul v307, v297
+    v309 = unchecked_add v304, v308
+    v310 = mul v299, v302
+    enable_side_effects u1 1
+    v311 = not v309
+    enable_side_effects v311
+    v313 = array_get v9, index u32 23 -> u8
+    v314 = eq v313, u8 145
+    v315 = not v314
+    v316 = mul v311, v315
+    v317 = lt v313, u8 145
+    enable_side_effects v316
+    v318 = mul v317, v316
+    constrain v318 == v316
+    v319 = not v316
+    v320 = mul v319, v309
+    v321 = unchecked_add v316, v320
+    v322 = mul v311, v314
+    enable_side_effects u1 1
+    v323 = not v321
+    enable_side_effects v323
+    v325 = array_get v9, index u32 24 -> u8
+    v326 = eq v325, u8 67
+    v327 = not v326
+    v328 = mul v323, v327
+    v329 = lt v325, u8 67
+    enable_side_effects v328
+    v330 = mul v329, v328
+    constrain v330 == v328
+    v331 = not v328
+    v332 = mul v331, v321
+    v333 = unchecked_add v328, v332
+    v334 = mul v323, v326
+    enable_side_effects u1 1
+    v335 = not v333
+    enable_side_effects v335
+    v337 = array_get v9, index u32 25 -> u8
+    v338 = eq v337, u8 225
+    v339 = not v338
+    v340 = mul v335, v339
+    v341 = lt v337, u8 225
+    enable_side_effects v340
+    v342 = mul v341, v340
+    constrain v342 == v340
+    v343 = not v340
+    v344 = mul v343, v333
+    v345 = unchecked_add v340, v344
+    v346 = mul v335, v338
+    enable_side_effects u1 1
+    v347 = not v345
+    enable_side_effects v347
+    v349 = array_get v9, index u32 26 -> u8
+    v350 = eq v349, u8 245
+    v351 = not v350
+    v352 = mul v347, v351
+    v353 = lt v349, u8 245
+    enable_side_effects v352
+    v354 = mul v353, v352
+    constrain v354 == v352
+    v355 = not v352
+    v356 = mul v355, v345
+    v357 = unchecked_add v352, v356
+    v358 = mul v347, v350
+    enable_side_effects u1 1
+    v359 = not v357
+    enable_side_effects v359
+    v361 = array_get v9, index u32 27 -> u8
+    v362 = eq v361, u8 147
+    v363 = not v362
+    v364 = mul v359, v363
+    v365 = lt v361, u8 147
+    enable_side_effects v364
+    v366 = mul v365, v364
+    constrain v366 == v364
+    v367 = not v364
+    v368 = mul v367, v357
+    v369 = unchecked_add v364, v368
+    v370 = mul v359, v362
+    enable_side_effects u1 1
+    v371 = not v369
+    enable_side_effects v371
+    v373 = array_get v9, index u32 28 -> u8
+    v374 = eq v373, u8 240
+    v375 = not v374
+    v376 = mul v371, v375
+    v377 = lt v373, u8 240
+    enable_side_effects v376
+    v378 = mul v377, v376
+    constrain v378 == v376
+    v379 = not v376
+    v380 = mul v379, v369
+    v381 = unchecked_add v376, v380
+    v382 = mul v371, v374
+    enable_side_effects u1 1
+    v383 = not v381
+    enable_side_effects v383
+    v385 = array_get v9, index u32 29 -> u8
+    v386 = eq v385, u8 0
+    v387 = not v386
+    v388 = mul v383, v387
+    constrain u1 0 == v388
+    enable_side_effects u1 0
+    v390 = unchecked_add v388, v381
+    v391 = mul v383, v386
+    enable_side_effects u1 1
+    v392 = not v390
+    enable_side_effects v392
+    v394 = array_get v9, index u32 30 -> u8
+    v395 = eq v394, u8 0
+    v396 = not v395
+    v397 = mul v392, v396
+    constrain u1 0 == v397
+    enable_side_effects u1 0
+    v398 = unchecked_add v397, v390
+    v399 = mul v392, v395
+    enable_side_effects u1 1
+    v400 = not v398
+    enable_side_effects v400
+    v402 = array_get v9, index u32 31 -> u8
+    v403 = eq v402, u8 1
+    v404 = not v403
+    v405 = mul v400, v404
+    v406 = eq v402, u8 0
+    v407 = cast v405 as u8
+    enable_side_effects v405
+    v408 = unchecked_mul v402, v407
+    constrain v408 == u8 0
+    v409 = not v405
+    v410 = mul v409, v398
+    v411 = unchecked_add v405, v410
+    v412 = mul v400, v403
+    enable_side_effects u1 1
+    constrain v411 == u1 1
+    v413 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v414 = allocate -> &mut u1
+    v415 = allocate -> &mut [u8; 32]
+    v416 = make_array [v42, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v417 = make_array [v42, v48, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v418 = make_array [v42, v48, v61, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v419 = make_array [v42, v48, v61, v73, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v420 = make_array [v42, v48, v61, v73, v85, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v421 = make_array [v42, v48, v61, v73, v85, v97, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v422 = make_array [v42, v48, v61, v73, v85, v97, v109, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v423 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v424 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v425 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v426 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v427 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v428 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v429 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v430 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v431 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v432 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v433 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v434 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v435 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v436 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v437 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v438 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v439 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v440 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v441 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v442 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v443 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v444 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, u8 0, u8 0, u8 0] : [u8; 32]
+    v445 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, u8 0, u8 0] : [u8; 32]
+    v446 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v394, u8 0] : [u8; 32]
+    v447 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v394, v402] : [u8; 32]
+    v448 = allocate -> &mut Field
+    v449 = allocate -> &mut Field
+    v450 = allocate -> &mut Field
+    v451 = cast v217 as Field
+    v452 = cast v402 as Field
+    v453 = cast v205 as Field
+    v455 = mul v453, Field 256
+    v456 = add v451, v455
+    v457 = cast v394 as Field
+    v458 = mul v457, Field 256
+    v459 = add v452, v458
+    v460 = cast v193 as Field
+    v462 = mul v460, Field 65536
+    v463 = add v456, v462
+    v464 = cast v385 as Field
+    v465 = mul v464, Field 65536
+    v466 = add v459, v465
+    v467 = cast v181 as Field
+    v469 = mul v467, Field 16777216
+    v470 = add v463, v469
+    v471 = cast v373 as Field
+    v472 = mul v471, Field 16777216
+    v473 = add v466, v472
+    v474 = cast v169 as Field
+    v476 = mul v474, Field 4294967296
+    v477 = add v470, v476
+    v478 = cast v361 as Field
+    v479 = mul v478, Field 4294967296
+    v480 = add v473, v479
+    v481 = cast v157 as Field
+    v483 = mul v481, Field 1099511627776
+    v484 = add v477, v483
+    v485 = cast v349 as Field
+    v486 = mul v485, Field 1099511627776
+    v487 = add v480, v486
+    v488 = cast v145 as Field
+    v490 = mul v488, Field 281474976710656
+    v491 = add v484, v490
+    v492 = cast v337 as Field
+    v493 = mul v492, Field 281474976710656
+    v494 = add v487, v493
+    v495 = cast v133 as Field
+    v497 = mul v495, Field 72057594037927936
+    v498 = add v491, v497
+    v499 = cast v325 as Field
+    v500 = mul v499, Field 72057594037927936
+    v501 = add v494, v500
+    v502 = cast v121 as Field
+    v504 = mul v502, Field 18446744073709551616
+    v505 = add v498, v504
+    v506 = cast v313 as Field
+    v507 = mul v506, Field 18446744073709551616
+    v508 = add v501, v507
+    v509 = cast v109 as Field
+    v511 = mul v509, Field 4722366482869645213696
+    v512 = add v505, v511
+    v513 = cast v301 as Field
+    v514 = mul v513, Field 4722366482869645213696
+    v515 = add v508, v514
+    v516 = cast v97 as Field
+    v518 = mul v516, Field 1208925819614629174706176
+    v519 = add v512, v518
+    v520 = cast v289 as Field
+    v521 = mul v520, Field 1208925819614629174706176
+    v522 = add v515, v521
+    v523 = cast v85 as Field
+    v525 = mul v523, Field 309485009821345068724781056
+    v526 = add v519, v525
+    v527 = cast v277 as Field
+    v528 = mul v527, Field 309485009821345068724781056
+    v529 = add v522, v528
+    v530 = cast v73 as Field
+    v532 = mul v530, Field 79228162514264337593543950336
+    v533 = add v526, v532
+    v534 = cast v265 as Field
+    v535 = mul v534, Field 79228162514264337593543950336
+    v536 = add v529, v535
+    v537 = cast v61 as Field
+    v539 = mul v537, Field 20282409603651670423947251286016
+    v540 = add v533, v539
+    v541 = cast v253 as Field
+    v542 = mul v541, Field 20282409603651670423947251286016
+    v543 = add v536, v542
+    v544 = cast v48 as Field
+    v546 = mul v544, Field 5192296858534827628530496329220096
+    v547 = add v540, v546
+    v548 = cast v241 as Field
+    v549 = mul v548, Field 5192296858534827628530496329220096
+    v550 = add v543, v549
+    v551 = cast v42 as Field
+    v553 = mul v551, Field 1329227995784915872903807060280344576
+    v554 = add v547, v553
+    v555 = cast v229 as Field
+    v556 = mul v555, Field 1329227995784915872903807060280344576
+    v557 = add v550, v556
+    v559 = mul v554, Field 340282366920938463463374607431768211456
+    v560 = add v557, v559
+    v561 = allocate -> &mut Field
+    v563 = eq v4, Field 0
+    v564 = not v563
+    enable_side_effects v564
+    v566 = call f1(v4, Field 0) -> u1
+    v567 = mul v564, v566
+    enable_side_effects v567
+    v569, v570 = call f3(Field 0) -> (Field, Field)
+    v571 = cast v567 as Field
+    v572 = mul v569, v571
+    range_check v572 to 128 bits
+    v573 = mul v570, v571
+    range_check v573 to 128 bits
+    v574 = mul Field 340282366920938463463374607431768211456, v570
+    v575 = add v569, v574
+    v576 = eq Field 0, v575
+    v577 = mul v575, v571
+    constrain Field 0 == v577
+    v580 = call f2(Field 53438638232309528389504892708671455233, v569) -> u1
+    v581 = sub Field 53438638232309528389504892708671455233, v569
+    v583 = sub v581, Field 1
+    v584 = cast v580 as Field
+    v585 = mul v584, Field 340282366920938463463374607431768211456
+    v586 = add v583, v585
+    v588 = sub Field 64323764613183177041862057485226039389, v570
+    v589 = sub v588, v584
+    v590 = mul v586, v571
+    range_check v590 to 128 bits
+    v591 = mul v589, v571
+    range_check v591 to 128 bits
+    v593, v594 = call f3(v4) -> (Field, Field)
+    v595 = mul v593, v571
+    range_check v595 to 128 bits
+    v596 = mul v594, v571
+    range_check v596 to 128 bits
+    v597 = mul Field 340282366920938463463374607431768211456, v594
+    v598 = add v593, v597
+    v599 = eq v4, v598
+    v600 = mul v4, v571
+    v601 = mul v598, v571
+    constrain v600 == v601
+    v603 = call f2(Field 53438638232309528389504892708671455233, v593) -> u1
+    v604 = sub Field 53438638232309528389504892708671455233, v593
+    v605 = sub v604, Field 1
+    v606 = cast v603 as Field
+    v607 = mul v606, Field 340282366920938463463374607431768211456
+    v608 = add v605, v607
+    v609 = sub Field 64323764613183177041862057485226039389, v594
+    v610 = sub v609, v606
+    v611 = mul v608, v571
+    range_check v611 to 128 bits
+    v612 = mul v610, v571
+    range_check v612 to 128 bits
+    v614 = call f2(v569, v593) -> u1
+    v615 = sub v569, v593
+    v616 = sub v615, Field 1
+    v617 = cast v614 as Field
+    v618 = mul v617, Field 340282366920938463463374607431768211456
+    v619 = add v616, v618
+    v620 = sub v570, v594
+    v621 = sub v620, v617
+    v622 = mul v619, v571
+    range_check v622 to 128 bits
+    v623 = mul v621, v571
+    range_check v623 to 128 bits
+    v624 = not v566
+    v625 = mul v564, v624
+    enable_side_effects v625
+    v627, v628 = call f3(v4) -> (Field, Field)
+    v629 = cast v625 as Field
+    v630 = mul v627, v629
+    range_check v630 to 128 bits
+    v631 = mul v628, v629
+    range_check v631 to 128 bits
+    v632 = mul Field 340282366920938463463374607431768211456, v628
+    v633 = add v627, v632
+    v634 = eq v4, v633
+    v635 = mul v4, v629
+    v636 = mul v633, v629
+    constrain v635 == v636
+    v638 = call f2(Field 53438638232309528389504892708671455233, v627) -> u1
+    v639 = sub Field 53438638232309528389504892708671455233, v627
+    v640 = sub v639, Field 1
+    v641 = cast v638 as Field
+    v642 = mul v641, Field 340282366920938463463374607431768211456
+    v643 = add v640, v642
+    v644 = sub Field 64323764613183177041862057485226039389, v628
+    v645 = sub v644, v641
+    v646 = mul v643, v629
+    range_check v646 to 128 bits
+    v647 = mul v645, v629
+    range_check v647 to 128 bits
+    v649, v650 = call f3(Field 0) -> (Field, Field)
+    v651 = mul v649, v629
+    range_check v651 to 128 bits
+    v652 = mul v650, v629
+    range_check v652 to 128 bits
+    v653 = mul Field 340282366920938463463374607431768211456, v650
+    v654 = add v649, v653
+    v655 = eq Field 0, v654
+    v656 = mul v654, v629
+    constrain Field 0 == v656
+    v658 = call f2(Field 53438638232309528389504892708671455233, v649) -> u1
+    v659 = sub Field 53438638232309528389504892708671455233, v649
+    v660 = sub v659, Field 1
+    v661 = cast v658 as Field
+    v662 = mul v661, Field 340282366920938463463374607431768211456
+    v663 = add v660, v662
+    v664 = sub Field 64323764613183177041862057485226039389, v650
+    v665 = sub v664, v661
+    v666 = mul v663, v629
+    range_check v666 to 128 bits
+    v667 = mul v665, v629
+    range_check v667 to 128 bits
+    v669 = call f2(v627, v649) -> u1
+    v670 = sub v627, v649
+    v671 = sub v670, Field 1
+    v672 = cast v669 as Field
+    v673 = mul v672, Field 340282366920938463463374607431768211456
+    v674 = add v671, v673
+    v675 = sub v628, v650
+    v676 = sub v675, v672
+    v677 = mul v674, v629
+    range_check v677 to 128 bits
+    v678 = mul v676, v629
+    range_check v678 to 128 bits
+    v679 = not v625
+    v680 = cast v679 as Field
+    enable_side_effects u1 1
+    v681 = sub v629, v560
+    return v681
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Adding constrain not equal:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = allocate -> &mut Field
+    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
+    v40 = allocate -> &mut u1
+    v42 = array_get v9, index u32 0 -> u8
+    v43 = eq v42, u8 48
+    v44 = not v43
+    v45 = lt v42, u8 48
+    enable_side_effects v44
+    v46 = mul v45, v44
+    constrain v46 == v44
+    enable_side_effects v43
+    v48 = array_get v9, index u32 1 -> u8
+    v49 = eq v48, u8 100
+    v50 = not v49
+    v51 = mul v43, v50
+    v52 = lt v48, u8 100
+    enable_side_effects v51
+    v53 = mul v52, v51
+    constrain v53 == v51
+    v54 = not v51
+    v55 = mul v54, v44
+    v56 = unchecked_add v51, v55
+    v57 = mul v43, v49
+    enable_side_effects u1 1
+    v59 = not v56
+    enable_side_effects v59
+    v61 = array_get v9, index u32 2 -> u8
+    v62 = eq v61, u8 78
+    v63 = not v62
+    v64 = mul v59, v63
+    v65 = lt v61, u8 78
+    enable_side_effects v64
+    v66 = mul v65, v64
+    constrain v66 == v64
+    v67 = not v64
+    v68 = mul v67, v56
+    v69 = unchecked_add v64, v68
+    v70 = mul v59, v62
+    enable_side_effects u1 1
+    v71 = not v69
+    enable_side_effects v71
+    v73 = array_get v9, index u32 3 -> u8
+    v74 = eq v73, u8 114
+    v75 = not v74
+    v76 = mul v71, v75
+    v77 = lt v73, u8 114
+    enable_side_effects v76
+    v78 = mul v77, v76
+    constrain v78 == v76
+    v79 = not v76
+    v80 = mul v79, v69
+    v81 = unchecked_add v76, v80
+    v82 = mul v71, v74
+    enable_side_effects u1 1
+    v83 = not v81
+    enable_side_effects v83
+    v85 = array_get v9, index u32 4 -> u8
+    v86 = eq v85, u8 225
+    v87 = not v86
+    v88 = mul v83, v87
+    v89 = lt v85, u8 225
+    enable_side_effects v88
+    v90 = mul v89, v88
+    constrain v90 == v88
+    v91 = not v88
+    v92 = mul v91, v81
+    v93 = unchecked_add v88, v92
+    v94 = mul v83, v86
+    enable_side_effects u1 1
+    v95 = not v93
+    enable_side_effects v95
+    v97 = array_get v9, index u32 5 -> u8
+    v98 = eq v97, u8 49
+    v99 = not v98
+    v100 = mul v95, v99
+    v101 = lt v97, u8 49
+    enable_side_effects v100
+    v102 = mul v101, v100
+    constrain v102 == v100
+    v103 = not v100
+    v104 = mul v103, v93
+    v105 = unchecked_add v100, v104
+    v106 = mul v95, v98
+    enable_side_effects u1 1
+    v107 = not v105
+    enable_side_effects v107
+    v109 = array_get v9, index u32 6 -> u8
+    v110 = eq v109, u8 160
+    v111 = not v110
+    v112 = mul v107, v111
+    v113 = lt v109, u8 160
+    enable_side_effects v112
+    v114 = mul v113, v112
+    constrain v114 == v112
+    v115 = not v112
+    v116 = mul v115, v105
+    v117 = unchecked_add v112, v116
+    v118 = mul v107, v110
+    enable_side_effects u1 1
+    v119 = not v117
+    enable_side_effects v119
+    v121 = array_get v9, index u32 7 -> u8
+    v122 = eq v121, u8 41
+    v123 = not v122
+    v124 = mul v119, v123
+    v125 = lt v121, u8 41
+    enable_side_effects v124
+    v126 = mul v125, v124
+    constrain v126 == v124
+    v127 = not v124
+    v128 = mul v127, v117
+    v129 = unchecked_add v124, v128
+    v130 = mul v119, v122
+    enable_side_effects u1 1
+    v131 = not v129
+    enable_side_effects v131
+    v133 = array_get v9, index u32 8 -> u8
+    v134 = eq v133, u8 184
+    v135 = not v134
+    v136 = mul v131, v135
+    v137 = lt v133, u8 184
+    enable_side_effects v136
+    v138 = mul v137, v136
+    constrain v138 == v136
+    v139 = not v136
+    v140 = mul v139, v129
+    v141 = unchecked_add v136, v140
+    v142 = mul v131, v134
+    enable_side_effects u1 1
+    v143 = not v141
+    enable_side_effects v143
+    v145 = array_get v9, index u32 9 -> u8
+    v146 = eq v145, u8 80
+    v147 = not v146
+    v148 = mul v143, v147
+    v149 = lt v145, u8 80
+    enable_side_effects v148
+    v150 = mul v149, v148
+    constrain v150 == v148
+    v151 = not v148
+    v152 = mul v151, v141
+    v153 = unchecked_add v148, v152
+    v154 = mul v143, v146
+    enable_side_effects u1 1
+    v155 = not v153
+    enable_side_effects v155
+    v157 = array_get v9, index u32 10 -> u8
+    v158 = eq v157, u8 69
+    v159 = not v158
+    v160 = mul v155, v159
+    v161 = lt v157, u8 69
+    enable_side_effects v160
+    v162 = mul v161, v160
+    constrain v162 == v160
+    v163 = not v160
+    v164 = mul v163, v153
+    v165 = unchecked_add v160, v164
+    v166 = mul v155, v158
+    enable_side_effects u1 1
+    v167 = not v165
+    enable_side_effects v167
+    v169 = array_get v9, index u32 11 -> u8
+    v170 = eq v169, u8 182
+    v171 = not v170
+    v172 = mul v167, v171
+    v173 = lt v169, u8 182
+    enable_side_effects v172
+    v174 = mul v173, v172
+    constrain v174 == v172
+    v175 = not v172
+    v176 = mul v175, v165
+    v177 = unchecked_add v172, v176
+    v178 = mul v167, v170
+    enable_side_effects u1 1
+    v179 = not v177
+    enable_side_effects v179
+    v181 = array_get v9, index u32 12 -> u8
+    v182 = eq v181, u8 129
+    v183 = not v182
+    v184 = mul v179, v183
+    v185 = lt v181, u8 129
+    enable_side_effects v184
+    v186 = mul v185, v184
+    constrain v186 == v184
+    v187 = not v184
+    v188 = mul v187, v177
+    v189 = unchecked_add v184, v188
+    v190 = mul v179, v182
+    enable_side_effects u1 1
+    v191 = not v189
+    enable_side_effects v191
+    v193 = array_get v9, index u32 13 -> u8
+    v194 = eq v193, u8 129
+    v195 = not v194
+    v196 = mul v191, v195
+    v197 = lt v193, u8 129
+    enable_side_effects v196
+    v198 = mul v197, v196
+    constrain v198 == v196
+    v199 = not v196
+    v200 = mul v199, v189
+    v201 = unchecked_add v196, v200
+    v202 = mul v191, v194
+    enable_side_effects u1 1
+    v203 = not v201
+    enable_side_effects v203
+    v205 = array_get v9, index u32 14 -> u8
+    v206 = eq v205, u8 88
+    v207 = not v206
+    v208 = mul v203, v207
+    v209 = lt v205, u8 88
+    enable_side_effects v208
+    v210 = mul v209, v208
+    constrain v210 == v208
+    v211 = not v208
+    v212 = mul v211, v201
+    v213 = unchecked_add v208, v212
+    v214 = mul v203, v206
+    enable_side_effects u1 1
+    v215 = not v213
+    enable_side_effects v215
+    v217 = array_get v9, index u32 15 -> u8
+    v218 = eq v217, u8 93
+    v219 = not v218
+    v220 = mul v215, v219
+    v221 = lt v217, u8 93
+    enable_side_effects v220
+    v222 = mul v221, v220
+    constrain v222 == v220
+    v223 = not v220
+    v224 = mul v223, v213
+    v225 = unchecked_add v220, v224
+    v226 = mul v215, v218
+    enable_side_effects u1 1
+    v227 = not v225
+    enable_side_effects v227
+    v229 = array_get v9, index u32 16 -> u8
+    v230 = eq v229, u8 40
+    v231 = not v230
+    v232 = mul v227, v231
+    v233 = lt v229, u8 40
+    enable_side_effects v232
+    v234 = mul v233, v232
+    constrain v234 == v232
+    v235 = not v232
+    v236 = mul v235, v225
+    v237 = unchecked_add v232, v236
+    v238 = mul v227, v230
+    enable_side_effects u1 1
+    v239 = not v237
+    enable_side_effects v239
+    v241 = array_get v9, index u32 17 -> u8
+    v242 = eq v241, u8 51
+    v243 = not v242
+    v244 = mul v239, v243
+    v245 = lt v241, u8 51
+    enable_side_effects v244
+    v246 = mul v245, v244
+    constrain v246 == v244
+    v247 = not v244
+    v248 = mul v247, v237
+    v249 = unchecked_add v244, v248
+    v250 = mul v239, v242
+    enable_side_effects u1 1
+    v251 = not v249
+    enable_side_effects v251
+    v253 = array_get v9, index u32 18 -> u8
+    v254 = eq v253, u8 232
+    v255 = not v254
+    v256 = mul v251, v255
+    v257 = lt v253, u8 232
+    enable_side_effects v256
+    v258 = mul v257, v256
+    constrain v258 == v256
+    v259 = not v256
+    v260 = mul v259, v249
+    v261 = unchecked_add v256, v260
+    v262 = mul v251, v254
+    enable_side_effects u1 1
+    v263 = not v261
+    enable_side_effects v263
+    v265 = array_get v9, index u32 19 -> u8
+    v266 = eq v265, u8 72
+    v267 = not v266
+    v268 = mul v263, v267
+    v269 = lt v265, u8 72
+    enable_side_effects v268
+    v270 = mul v269, v268
+    constrain v270 == v268
+    v271 = not v268
+    v272 = mul v271, v261
+    v273 = unchecked_add v268, v272
+    v274 = mul v263, v266
+    enable_side_effects u1 1
+    v275 = not v273
+    enable_side_effects v275
+    v277 = array_get v9, index u32 20 -> u8
+    v278 = eq v277, u8 121
+    v279 = not v278
+    v280 = mul v275, v279
+    v281 = lt v277, u8 121
+    enable_side_effects v280
+    v282 = mul v281, v280
+    constrain v282 == v280
+    v283 = not v280
+    v284 = mul v283, v273
+    v285 = unchecked_add v280, v284
+    v286 = mul v275, v278
+    enable_side_effects u1 1
+    v287 = not v285
+    enable_side_effects v287
+    v289 = array_get v9, index u32 21 -> u8
+    v290 = eq v289, u8 185
+    v291 = not v290
+    v292 = mul v287, v291
+    v293 = lt v289, u8 185
+    enable_side_effects v292
+    v294 = mul v293, v292
+    constrain v294 == v292
+    v295 = not v292
+    v296 = mul v295, v285
+    v297 = unchecked_add v292, v296
+    v298 = mul v287, v290
+    enable_side_effects u1 1
+    v299 = not v297
+    enable_side_effects v299
+    v301 = array_get v9, index u32 22 -> u8
+    v302 = eq v301, u8 112
+    v303 = not v302
+    v304 = mul v299, v303
+    v305 = lt v301, u8 112
+    enable_side_effects v304
+    v306 = mul v305, v304
+    constrain v306 == v304
+    v307 = not v304
+    v308 = mul v307, v297
+    v309 = unchecked_add v304, v308
+    v310 = mul v299, v302
+    enable_side_effects u1 1
+    v311 = not v309
+    enable_side_effects v311
+    v313 = array_get v9, index u32 23 -> u8
+    v314 = eq v313, u8 145
+    v315 = not v314
+    v316 = mul v311, v315
+    v317 = lt v313, u8 145
+    enable_side_effects v316
+    v318 = mul v317, v316
+    constrain v318 == v316
+    v319 = not v316
+    v320 = mul v319, v309
+    v321 = unchecked_add v316, v320
+    v322 = mul v311, v314
+    enable_side_effects u1 1
+    v323 = not v321
+    enable_side_effects v323
+    v325 = array_get v9, index u32 24 -> u8
+    v326 = eq v325, u8 67
+    v327 = not v326
+    v328 = mul v323, v327
+    v329 = lt v325, u8 67
+    enable_side_effects v328
+    v330 = mul v329, v328
+    constrain v330 == v328
+    v331 = not v328
+    v332 = mul v331, v321
+    v333 = unchecked_add v328, v332
+    v334 = mul v323, v326
+    enable_side_effects u1 1
+    v335 = not v333
+    enable_side_effects v335
+    v337 = array_get v9, index u32 25 -> u8
+    v338 = eq v337, u8 225
+    v339 = not v338
+    v340 = mul v335, v339
+    v341 = lt v337, u8 225
+    enable_side_effects v340
+    v342 = mul v341, v340
+    constrain v342 == v340
+    v343 = not v340
+    v344 = mul v343, v333
+    v345 = unchecked_add v340, v344
+    v346 = mul v335, v338
+    enable_side_effects u1 1
+    v347 = not v345
+    enable_side_effects v347
+    v349 = array_get v9, index u32 26 -> u8
+    v350 = eq v349, u8 245
+    v351 = not v350
+    v352 = mul v347, v351
+    v353 = lt v349, u8 245
+    enable_side_effects v352
+    v354 = mul v353, v352
+    constrain v354 == v352
+    v355 = not v352
+    v356 = mul v355, v345
+    v357 = unchecked_add v352, v356
+    v358 = mul v347, v350
+    enable_side_effects u1 1
+    v359 = not v357
+    enable_side_effects v359
+    v361 = array_get v9, index u32 27 -> u8
+    v362 = eq v361, u8 147
+    v363 = not v362
+    v364 = mul v359, v363
+    v365 = lt v361, u8 147
+    enable_side_effects v364
+    v366 = mul v365, v364
+    constrain v366 == v364
+    v367 = not v364
+    v368 = mul v367, v357
+    v369 = unchecked_add v364, v368
+    v370 = mul v359, v362
+    enable_side_effects u1 1
+    v371 = not v369
+    enable_side_effects v371
+    v373 = array_get v9, index u32 28 -> u8
+    v374 = eq v373, u8 240
+    v375 = not v374
+    v376 = mul v371, v375
+    v377 = lt v373, u8 240
+    enable_side_effects v376
+    v378 = mul v377, v376
+    constrain v378 == v376
+    v379 = not v376
+    v380 = mul v379, v369
+    v381 = unchecked_add v376, v380
+    v382 = mul v371, v374
+    enable_side_effects u1 1
+    v383 = not v381
+    enable_side_effects v383
+    v385 = array_get v9, index u32 29 -> u8
+    v386 = eq v385, u8 0
+    v387 = not v386
+    v388 = mul v383, v387
+    constrain u1 0 == v388
+    enable_side_effects u1 0
+    v390 = unchecked_add v388, v381
+    v391 = mul v383, v386
+    enable_side_effects u1 1
+    v392 = not v390
+    enable_side_effects v392
+    v394 = array_get v9, index u32 30 -> u8
+    v395 = eq v394, u8 0
+    v396 = not v395
+    v397 = mul v392, v396
+    constrain u1 0 == v397
+    enable_side_effects u1 0
+    v398 = unchecked_add v397, v390
+    v399 = mul v392, v395
+    enable_side_effects u1 1
+    v400 = not v398
+    enable_side_effects v400
+    v402 = array_get v9, index u32 31 -> u8
+    v403 = eq v402, u8 1
+    v404 = not v403
+    v405 = mul v400, v404
+    v406 = eq v402, u8 0
+    v407 = cast v405 as u8
+    enable_side_effects v405
+    v408 = unchecked_mul v402, v407
+    constrain v408 == u8 0
+    v409 = not v405
+    v410 = mul v409, v398
+    v411 = unchecked_add v405, v410
+    v412 = mul v400, v403
+    enable_side_effects u1 1
+    constrain v411 == u1 1
+    v413 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v414 = allocate -> &mut u1
+    v415 = allocate -> &mut [u8; 32]
+    v416 = make_array [v42, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v417 = make_array [v42, v48, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v418 = make_array [v42, v48, v61, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v419 = make_array [v42, v48, v61, v73, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v420 = make_array [v42, v48, v61, v73, v85, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v421 = make_array [v42, v48, v61, v73, v85, v97, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v422 = make_array [v42, v48, v61, v73, v85, v97, v109, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v423 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v424 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v425 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v426 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v427 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v428 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v429 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v430 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v431 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v432 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v433 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v434 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v435 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v436 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v437 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v438 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v439 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v440 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v441 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v442 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v443 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
+    v444 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, u8 0, u8 0, u8 0] : [u8; 32]
+    v445 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, u8 0, u8 0] : [u8; 32]
+    v446 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v394, u8 0] : [u8; 32]
+    v447 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v394, v402] : [u8; 32]
+    v448 = allocate -> &mut Field
+    v449 = allocate -> &mut Field
+    v450 = allocate -> &mut Field
+    v451 = cast v217 as Field
+    v452 = cast v402 as Field
+    v453 = cast v205 as Field
+    v455 = mul v453, Field 256
+    v456 = add v451, v455
+    v457 = cast v394 as Field
+    v458 = mul v457, Field 256
+    v459 = add v452, v458
+    v460 = cast v193 as Field
+    v462 = mul v460, Field 65536
+    v463 = add v456, v462
+    v464 = cast v385 as Field
+    v465 = mul v464, Field 65536
+    v466 = add v459, v465
+    v467 = cast v181 as Field
+    v469 = mul v467, Field 16777216
+    v470 = add v463, v469
+    v471 = cast v373 as Field
+    v472 = mul v471, Field 16777216
+    v473 = add v466, v472
+    v474 = cast v169 as Field
+    v476 = mul v474, Field 4294967296
+    v477 = add v470, v476
+    v478 = cast v361 as Field
+    v479 = mul v478, Field 4294967296
+    v480 = add v473, v479
+    v481 = cast v157 as Field
+    v483 = mul v481, Field 1099511627776
+    v484 = add v477, v483
+    v485 = cast v349 as Field
+    v486 = mul v485, Field 1099511627776
+    v487 = add v480, v486
+    v488 = cast v145 as Field
+    v490 = mul v488, Field 281474976710656
+    v491 = add v484, v490
+    v492 = cast v337 as Field
+    v493 = mul v492, Field 281474976710656
+    v494 = add v487, v493
+    v495 = cast v133 as Field
+    v497 = mul v495, Field 72057594037927936
+    v498 = add v491, v497
+    v499 = cast v325 as Field
+    v500 = mul v499, Field 72057594037927936
+    v501 = add v494, v500
+    v502 = cast v121 as Field
+    v504 = mul v502, Field 18446744073709551616
+    v505 = add v498, v504
+    v506 = cast v313 as Field
+    v507 = mul v506, Field 18446744073709551616
+    v508 = add v501, v507
+    v509 = cast v109 as Field
+    v511 = mul v509, Field 4722366482869645213696
+    v512 = add v505, v511
+    v513 = cast v301 as Field
+    v514 = mul v513, Field 4722366482869645213696
+    v515 = add v508, v514
+    v516 = cast v97 as Field
+    v518 = mul v516, Field 1208925819614629174706176
+    v519 = add v512, v518
+    v520 = cast v289 as Field
+    v521 = mul v520, Field 1208925819614629174706176
+    v522 = add v515, v521
+    v523 = cast v85 as Field
+    v525 = mul v523, Field 309485009821345068724781056
+    v526 = add v519, v525
+    v527 = cast v277 as Field
+    v528 = mul v527, Field 309485009821345068724781056
+    v529 = add v522, v528
+    v530 = cast v73 as Field
+    v532 = mul v530, Field 79228162514264337593543950336
+    v533 = add v526, v532
+    v534 = cast v265 as Field
+    v535 = mul v534, Field 79228162514264337593543950336
+    v536 = add v529, v535
+    v537 = cast v61 as Field
+    v539 = mul v537, Field 20282409603651670423947251286016
+    v540 = add v533, v539
+    v541 = cast v253 as Field
+    v542 = mul v541, Field 20282409603651670423947251286016
+    v543 = add v536, v542
+    v544 = cast v48 as Field
+    v546 = mul v544, Field 5192296858534827628530496329220096
+    v547 = add v540, v546
+    v548 = cast v241 as Field
+    v549 = mul v548, Field 5192296858534827628530496329220096
+    v550 = add v543, v549
+    v551 = cast v42 as Field
+    v553 = mul v551, Field 1329227995784915872903807060280344576
+    v554 = add v547, v553
+    v555 = cast v229 as Field
+    v556 = mul v555, Field 1329227995784915872903807060280344576
+    v557 = add v550, v556
+    v559 = mul v554, Field 340282366920938463463374607431768211456
+    v560 = add v557, v559
+    v561 = allocate -> &mut Field
+    v563 = eq v4, Field 0
+    v564 = not v563
+    enable_side_effects v564
+    v566 = call f1(v4, Field 0) -> u1
+    v567 = mul v564, v566
+    enable_side_effects v567
+    v569, v570 = call f3(Field 0) -> (Field, Field)
+    v571 = cast v567 as Field
+    v572 = mul v569, v571
+    range_check v572 to 128 bits
+    v573 = mul v570, v571
+    range_check v573 to 128 bits
+    v574 = mul Field 340282366920938463463374607431768211456, v570
+    v575 = add v569, v574
+    v576 = eq Field 0, v575
+    v577 = mul v575, v571
+    constrain Field 0 == v577
+    v580 = call f2(Field 53438638232309528389504892708671455233, v569) -> u1
+    v581 = sub Field 53438638232309528389504892708671455233, v569
+    v583 = sub v581, Field 1
+    v584 = cast v580 as Field
+    v585 = mul v584, Field 340282366920938463463374607431768211456
+    v586 = add v583, v585
+    v588 = sub Field 64323764613183177041862057485226039389, v570
+    v589 = sub v588, v584
+    v590 = mul v586, v571
+    range_check v590 to 128 bits
+    v591 = mul v589, v571
+    range_check v591 to 128 bits
+    v593, v594 = call f3(v4) -> (Field, Field)
+    v595 = mul v593, v571
+    range_check v595 to 128 bits
+    v596 = mul v594, v571
+    range_check v596 to 128 bits
+    v597 = mul Field 340282366920938463463374607431768211456, v594
+    v598 = add v593, v597
+    v599 = eq v4, v598
+    v600 = mul v4, v571
+    v601 = mul v598, v571
+    constrain v600 == v601
+    v603 = call f2(Field 53438638232309528389504892708671455233, v593) -> u1
+    v604 = sub Field 53438638232309528389504892708671455233, v593
+    v605 = sub v604, Field 1
+    v606 = cast v603 as Field
+    v607 = mul v606, Field 340282366920938463463374607431768211456
+    v608 = add v605, v607
+    v609 = sub Field 64323764613183177041862057485226039389, v594
+    v610 = sub v609, v606
+    v611 = mul v608, v571
+    range_check v611 to 128 bits
+    v612 = mul v610, v571
+    range_check v612 to 128 bits
+    v614 = call f2(v569, v593) -> u1
+    v615 = sub v569, v593
+    v616 = sub v615, Field 1
+    v617 = cast v614 as Field
+    v618 = mul v617, Field 340282366920938463463374607431768211456
+    v619 = add v616, v618
+    v620 = sub v570, v594
+    v621 = sub v620, v617
+    v622 = mul v619, v571
+    range_check v622 to 128 bits
+    v623 = mul v621, v571
+    range_check v623 to 128 bits
+    v624 = not v566
+    v625 = mul v564, v624
+    enable_side_effects v625
+    v627, v628 = call f3(v4) -> (Field, Field)
+    v629 = cast v625 as Field
+    v630 = mul v627, v629
+    range_check v630 to 128 bits
+    v631 = mul v628, v629
+    range_check v631 to 128 bits
+    v632 = mul Field 340282366920938463463374607431768211456, v628
+    v633 = add v627, v632
+    v634 = eq v4, v633
+    v635 = mul v4, v629
+    v636 = mul v633, v629
+    constrain v635 == v636
+    v638 = call f2(Field 53438638232309528389504892708671455233, v627) -> u1
+    v639 = sub Field 53438638232309528389504892708671455233, v627
+    v640 = sub v639, Field 1
+    v641 = cast v638 as Field
+    v642 = mul v641, Field 340282366920938463463374607431768211456
+    v643 = add v640, v642
+    v644 = sub Field 64323764613183177041862057485226039389, v628
+    v645 = sub v644, v641
+    v646 = mul v643, v629
+    range_check v646 to 128 bits
+    v647 = mul v645, v629
+    range_check v647 to 128 bits
+    v649, v650 = call f3(Field 0) -> (Field, Field)
+    v651 = mul v649, v629
+    range_check v651 to 128 bits
+    v652 = mul v650, v629
+    range_check v652 to 128 bits
+    v653 = mul Field 340282366920938463463374607431768211456, v650
+    v654 = add v649, v653
+    v655 = eq Field 0, v654
+    v656 = mul v654, v629
+    constrain Field 0 == v656
+    v658 = call f2(Field 53438638232309528389504892708671455233, v649) -> u1
+    v659 = sub Field 53438638232309528389504892708671455233, v649
+    v660 = sub v659, Field 1
+    v661 = cast v658 as Field
+    v662 = mul v661, Field 340282366920938463463374607431768211456
+    v663 = add v660, v662
+    v664 = sub Field 64323764613183177041862057485226039389, v650
+    v665 = sub v664, v661
+    v666 = mul v663, v629
+    range_check v666 to 128 bits
+    v667 = mul v665, v629
+    range_check v667 to 128 bits
+    v669 = call f2(v627, v649) -> u1
+    v670 = sub v627, v649
+    v671 = sub v670, Field 1
+    v672 = cast v669 as Field
+    v673 = mul v672, Field 340282366920938463463374607431768211456
+    v674 = add v671, v673
+    v675 = sub v628, v650
+    v676 = sub v675, v672
+    v677 = mul v674, v629
+    range_check v677 to 128 bits
+    v678 = mul v676, v629
+    range_check v678 to 128 bits
+    v679 = not v625
+    v680 = cast v679 as Field
+    enable_side_effects u1 1
+    v681 = sub v629, v560
+    return v681
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = allocate -> &mut Field
+    v6 = truncate v4 to 64 bits, max_bit_size: 254
+    v7 = cast v6 as u64
+    v8 = sub v4, v6
+    v9 = div v8, Field 18446744073709551616
+    v10 = truncate v9 to 64 bits, max_bit_size: 254
+    v11 = cast v10 as u64
+    v12 = sub v9, v10
+    v13 = div v12, Field 18446744073709551616
+    v14 = mul v10, Field 18446744073709551616
+    v15 = add v14, v6
+    return v15, v13
+}
+
+After Dead Instruction Elimination (1st):
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v7 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v9 = array_get v7, index u32 0 -> u8
+    v11 = eq v9, u8 48
+    v12 = not v11
+    v13 = lt v9, u8 48
+    enable_side_effects v12
+    v14 = mul v13, v12
+    constrain v14 == v12
+    enable_side_effects v11
+    v16 = array_get v7, index u32 1 -> u8
+    v18 = eq v16, u8 100
+    v19 = not v18
+    v20 = mul v11, v19
+    v21 = lt v16, u8 100
+    enable_side_effects v20
+    v22 = mul v21, v20
+    constrain v22 == v20
+    v23 = not v20
+    v24 = mul v23, v12
+    v25 = unchecked_add v20, v24
+    enable_side_effects u1 1
+    v27 = not v25
+    enable_side_effects v27
+    v29 = array_get v7, index u32 2 -> u8
+    v31 = eq v29, u8 78
+    v32 = not v31
+    v33 = mul v27, v32
+    v34 = lt v29, u8 78
+    enable_side_effects v33
+    v35 = mul v34, v33
+    constrain v35 == v33
+    v36 = not v33
+    v37 = mul v36, v25
+    v38 = unchecked_add v33, v37
+    enable_side_effects u1 1
+    v39 = not v38
+    enable_side_effects v39
+    v41 = array_get v7, index u32 3 -> u8
+    v43 = eq v41, u8 114
+    v44 = not v43
+    v45 = mul v39, v44
+    v46 = lt v41, u8 114
+    enable_side_effects v45
+    v47 = mul v46, v45
+    constrain v47 == v45
+    v48 = not v45
+    v49 = mul v48, v38
+    v50 = unchecked_add v45, v49
+    enable_side_effects u1 1
+    v51 = not v50
+    enable_side_effects v51
+    v53 = array_get v7, index u32 4 -> u8
+    v55 = eq v53, u8 225
+    v56 = not v55
+    v57 = mul v51, v56
+    v58 = lt v53, u8 225
+    enable_side_effects v57
+    v59 = mul v58, v57
+    constrain v59 == v57
+    v60 = not v57
+    v61 = mul v60, v50
+    v62 = unchecked_add v57, v61
+    enable_side_effects u1 1
+    v63 = not v62
+    enable_side_effects v63
+    v65 = array_get v7, index u32 5 -> u8
+    v67 = eq v65, u8 49
+    v68 = not v67
+    v69 = mul v63, v68
+    v70 = lt v65, u8 49
+    enable_side_effects v69
+    v71 = mul v70, v69
+    constrain v71 == v69
+    v72 = not v69
+    v73 = mul v72, v62
+    v74 = unchecked_add v69, v73
+    enable_side_effects u1 1
+    v75 = not v74
+    enable_side_effects v75
+    v77 = array_get v7, index u32 6 -> u8
+    v79 = eq v77, u8 160
+    v80 = not v79
+    v81 = mul v75, v80
+    v82 = lt v77, u8 160
+    enable_side_effects v81
+    v83 = mul v82, v81
+    constrain v83 == v81
+    v84 = not v81
+    v85 = mul v84, v74
+    v86 = unchecked_add v81, v85
+    enable_side_effects u1 1
+    v87 = not v86
+    enable_side_effects v87
+    v89 = array_get v7, index u32 7 -> u8
+    v91 = eq v89, u8 41
+    v92 = not v91
+    v93 = mul v87, v92
+    v94 = lt v89, u8 41
+    enable_side_effects v93
+    v95 = mul v94, v93
+    constrain v95 == v93
+    v96 = not v93
+    v97 = mul v96, v86
+    v98 = unchecked_add v93, v97
+    enable_side_effects u1 1
+    v99 = not v98
+    enable_side_effects v99
+    v101 = array_get v7, index u32 8 -> u8
+    v103 = eq v101, u8 184
+    v104 = not v103
+    v105 = mul v99, v104
+    v106 = lt v101, u8 184
+    enable_side_effects v105
+    v107 = mul v106, v105
+    constrain v107 == v105
+    v108 = not v105
+    v109 = mul v108, v98
+    v110 = unchecked_add v105, v109
+    enable_side_effects u1 1
+    v111 = not v110
+    enable_side_effects v111
+    v113 = array_get v7, index u32 9 -> u8
+    v115 = eq v113, u8 80
+    v116 = not v115
+    v117 = mul v111, v116
+    v118 = lt v113, u8 80
+    enable_side_effects v117
+    v119 = mul v118, v117
+    constrain v119 == v117
+    v120 = not v117
+    v121 = mul v120, v110
+    v122 = unchecked_add v117, v121
+    enable_side_effects u1 1
+    v123 = not v122
+    enable_side_effects v123
+    v125 = array_get v7, index u32 10 -> u8
+    v127 = eq v125, u8 69
+    v128 = not v127
+    v129 = mul v123, v128
+    v130 = lt v125, u8 69
+    enable_side_effects v129
+    v131 = mul v130, v129
+    constrain v131 == v129
+    v132 = not v129
+    v133 = mul v132, v122
+    v134 = unchecked_add v129, v133
+    enable_side_effects u1 1
+    v135 = not v134
+    enable_side_effects v135
+    v137 = array_get v7, index u32 11 -> u8
+    v139 = eq v137, u8 182
+    v140 = not v139
+    v141 = mul v135, v140
+    v142 = lt v137, u8 182
+    enable_side_effects v141
+    v143 = mul v142, v141
+    constrain v143 == v141
+    v144 = not v141
+    v145 = mul v144, v134
+    v146 = unchecked_add v141, v145
+    enable_side_effects u1 1
+    v147 = not v146
+    enable_side_effects v147
+    v149 = array_get v7, index u32 12 -> u8
+    v151 = eq v149, u8 129
+    v152 = not v151
+    v153 = mul v147, v152
+    v154 = lt v149, u8 129
+    enable_side_effects v153
+    v155 = mul v154, v153
+    constrain v155 == v153
+    v156 = not v153
+    v157 = mul v156, v146
+    v158 = unchecked_add v153, v157
+    enable_side_effects u1 1
+    v159 = not v158
+    enable_side_effects v159
+    v161 = array_get v7, index u32 13 -> u8
+    v162 = eq v161, u8 129
+    v163 = not v162
+    v164 = mul v159, v163
+    v165 = lt v161, u8 129
+    enable_side_effects v164
+    v166 = mul v165, v164
+    constrain v166 == v164
+    v167 = not v164
+    v168 = mul v167, v158
+    v169 = unchecked_add v164, v168
+    enable_side_effects u1 1
+    v170 = not v169
+    enable_side_effects v170
+    v172 = array_get v7, index u32 14 -> u8
+    v174 = eq v172, u8 88
+    v175 = not v174
+    v176 = mul v170, v175
+    v177 = lt v172, u8 88
+    enable_side_effects v176
+    v178 = mul v177, v176
+    constrain v178 == v176
+    v179 = not v176
+    v180 = mul v179, v169
+    v181 = unchecked_add v176, v180
+    enable_side_effects u1 1
+    v182 = not v181
+    enable_side_effects v182
+    v184 = array_get v7, index u32 15 -> u8
+    v186 = eq v184, u8 93
+    v187 = not v186
+    v188 = mul v182, v187
+    v189 = lt v184, u8 93
+    enable_side_effects v188
+    v190 = mul v189, v188
+    constrain v190 == v188
+    v191 = not v188
+    v192 = mul v191, v181
+    v193 = unchecked_add v188, v192
+    enable_side_effects u1 1
+    v194 = not v193
+    enable_side_effects v194
+    v196 = array_get v7, index u32 16 -> u8
+    v198 = eq v196, u8 40
+    v199 = not v198
+    v200 = mul v194, v199
+    v201 = lt v196, u8 40
+    enable_side_effects v200
+    v202 = mul v201, v200
+    constrain v202 == v200
+    v203 = not v200
+    v204 = mul v203, v193
+    v205 = unchecked_add v200, v204
+    enable_side_effects u1 1
+    v206 = not v205
+    enable_side_effects v206
+    v208 = array_get v7, index u32 17 -> u8
+    v210 = eq v208, u8 51
+    v211 = not v210
+    v212 = mul v206, v211
+    v213 = lt v208, u8 51
+    enable_side_effects v212
+    v214 = mul v213, v212
+    constrain v214 == v212
+    v215 = not v212
+    v216 = mul v215, v205
+    v217 = unchecked_add v212, v216
+    enable_side_effects u1 1
+    v218 = not v217
+    enable_side_effects v218
+    v220 = array_get v7, index u32 18 -> u8
+    v222 = eq v220, u8 232
+    v223 = not v222
+    v224 = mul v218, v223
+    v225 = lt v220, u8 232
+    enable_side_effects v224
+    v226 = mul v225, v224
+    constrain v226 == v224
+    v227 = not v224
+    v228 = mul v227, v217
+    v229 = unchecked_add v224, v228
+    enable_side_effects u1 1
+    v230 = not v229
+    enable_side_effects v230
+    v232 = array_get v7, index u32 19 -> u8
+    v234 = eq v232, u8 72
+    v235 = not v234
+    v236 = mul v230, v235
+    v237 = lt v232, u8 72
+    enable_side_effects v236
+    v238 = mul v237, v236
+    constrain v238 == v236
+    v239 = not v236
+    v240 = mul v239, v229
+    v241 = unchecked_add v236, v240
+    enable_side_effects u1 1
+    v242 = not v241
+    enable_side_effects v242
+    v244 = array_get v7, index u32 20 -> u8
+    v246 = eq v244, u8 121
+    v247 = not v246
+    v248 = mul v242, v247
+    v249 = lt v244, u8 121
+    enable_side_effects v248
+    v250 = mul v249, v248
+    constrain v250 == v248
+    v251 = not v248
+    v252 = mul v251, v241
+    v253 = unchecked_add v248, v252
+    enable_side_effects u1 1
+    v254 = not v253
+    enable_side_effects v254
+    v256 = array_get v7, index u32 21 -> u8
+    v258 = eq v256, u8 185
+    v259 = not v258
+    v260 = mul v254, v259
+    v261 = lt v256, u8 185
+    enable_side_effects v260
+    v262 = mul v261, v260
+    constrain v262 == v260
+    v263 = not v260
+    v264 = mul v263, v253
+    v265 = unchecked_add v260, v264
+    enable_side_effects u1 1
+    v266 = not v265
+    enable_side_effects v266
+    v268 = array_get v7, index u32 22 -> u8
+    v270 = eq v268, u8 112
+    v271 = not v270
+    v272 = mul v266, v271
+    v273 = lt v268, u8 112
+    enable_side_effects v272
+    v274 = mul v273, v272
+    constrain v274 == v272
+    v275 = not v272
+    v276 = mul v275, v265
+    v277 = unchecked_add v272, v276
+    enable_side_effects u1 1
+    v278 = not v277
+    enable_side_effects v278
+    v280 = array_get v7, index u32 23 -> u8
+    v282 = eq v280, u8 145
+    v283 = not v282
+    v284 = mul v278, v283
+    v285 = lt v280, u8 145
+    enable_side_effects v284
+    v286 = mul v285, v284
+    constrain v286 == v284
+    v287 = not v284
+    v288 = mul v287, v277
+    v289 = unchecked_add v284, v288
+    enable_side_effects u1 1
+    v290 = not v289
+    enable_side_effects v290
+    v292 = array_get v7, index u32 24 -> u8
+    v294 = eq v292, u8 67
+    v295 = not v294
+    v296 = mul v290, v295
+    v297 = lt v292, u8 67
+    enable_side_effects v296
+    v298 = mul v297, v296
+    constrain v298 == v296
+    v299 = not v296
+    v300 = mul v299, v289
+    v301 = unchecked_add v296, v300
+    enable_side_effects u1 1
+    v302 = not v301
+    enable_side_effects v302
+    v304 = array_get v7, index u32 25 -> u8
+    v305 = eq v304, u8 225
+    v306 = not v305
+    v307 = mul v302, v306
+    v308 = lt v304, u8 225
+    enable_side_effects v307
+    v309 = mul v308, v307
+    constrain v309 == v307
+    v310 = not v307
+    v311 = mul v310, v301
+    v312 = unchecked_add v307, v311
+    enable_side_effects u1 1
+    v313 = not v312
+    enable_side_effects v313
+    v315 = array_get v7, index u32 26 -> u8
+    v317 = eq v315, u8 245
+    v318 = not v317
+    v319 = mul v313, v318
+    v320 = lt v315, u8 245
+    enable_side_effects v319
+    v321 = mul v320, v319
+    constrain v321 == v319
+    v322 = not v319
+    v323 = mul v322, v312
+    v324 = unchecked_add v319, v323
+    enable_side_effects u1 1
+    v325 = not v324
+    enable_side_effects v325
+    v327 = array_get v7, index u32 27 -> u8
+    v329 = eq v327, u8 147
+    v330 = not v329
+    v331 = mul v325, v330
+    v332 = lt v327, u8 147
+    enable_side_effects v331
+    v333 = mul v332, v331
+    constrain v333 == v331
+    v334 = not v331
+    v335 = mul v334, v324
+    v336 = unchecked_add v331, v335
+    enable_side_effects u1 1
+    v337 = not v336
+    enable_side_effects v337
+    v339 = array_get v7, index u32 28 -> u8
+    v341 = eq v339, u8 240
+    v342 = not v341
+    v343 = mul v337, v342
+    v344 = lt v339, u8 240
+    enable_side_effects v343
+    v345 = mul v344, v343
+    constrain v345 == v343
+    v346 = not v343
+    v347 = mul v346, v336
+    v348 = unchecked_add v343, v347
+    enable_side_effects u1 1
+    v349 = not v348
+    enable_side_effects v349
+    v351 = array_get v7, index u32 29 -> u8
+    v353 = eq v351, u8 0
+    v354 = not v353
+    v355 = mul v349, v354
+    constrain u1 0 == v355
+    enable_side_effects u1 0
+    v357 = unchecked_add v355, v348
+    enable_side_effects u1 1
+    v358 = not v357
+    enable_side_effects v358
+    v360 = array_get v7, index u32 30 -> u8
+    v361 = eq v360, u8 0
+    v362 = not v361
+    v363 = mul v358, v362
+    constrain u1 0 == v363
+    enable_side_effects u1 0
+    v364 = unchecked_add v363, v357
+    enable_side_effects u1 1
+    v365 = not v364
+    enable_side_effects v365
+    v367 = array_get v7, index u32 31 -> u8
+    v369 = eq v367, u8 1
+    v370 = not v369
+    v371 = mul v365, v370
+    v372 = cast v371 as u8
+    enable_side_effects v371
+    v373 = unchecked_mul v367, v372
+    constrain v373 == u8 0
+    v374 = not v371
+    v375 = mul v374, v364
+    v376 = unchecked_add v371, v375
+    enable_side_effects u1 1
+    constrain v376 == u1 1
+    v377 = cast v184 as Field
+    v378 = cast v367 as Field
+    v379 = cast v172 as Field
+    v381 = mul v379, Field 256
+    v382 = add v377, v381
+    v383 = cast v360 as Field
+    v384 = mul v383, Field 256
+    v385 = add v378, v384
+    v386 = cast v161 as Field
+    v388 = mul v386, Field 65536
+    v389 = add v382, v388
+    v390 = cast v351 as Field
+    v391 = mul v390, Field 65536
+    v392 = add v385, v391
+    v393 = cast v149 as Field
+    v395 = mul v393, Field 16777216
+    v396 = add v389, v395
+    v397 = cast v339 as Field
+    v398 = mul v397, Field 16777216
+    v399 = add v392, v398
+    v400 = cast v137 as Field
+    v402 = mul v400, Field 4294967296
+    v403 = add v396, v402
+    v404 = cast v327 as Field
+    v405 = mul v404, Field 4294967296
+    v406 = add v399, v405
+    v407 = cast v125 as Field
+    v409 = mul v407, Field 1099511627776
+    v410 = add v403, v409
+    v411 = cast v315 as Field
+    v412 = mul v411, Field 1099511627776
+    v413 = add v406, v412
+    v414 = cast v113 as Field
+    v416 = mul v414, Field 281474976710656
+    v417 = add v410, v416
+    v418 = cast v304 as Field
+    v419 = mul v418, Field 281474976710656
+    v420 = add v413, v419
+    v421 = cast v101 as Field
+    v423 = mul v421, Field 72057594037927936
+    v424 = add v417, v423
+    v425 = cast v292 as Field
+    v426 = mul v425, Field 72057594037927936
+    v427 = add v420, v426
+    v428 = cast v89 as Field
+    v430 = mul v428, Field 18446744073709551616
+    v431 = add v424, v430
+    v432 = cast v280 as Field
+    v433 = mul v432, Field 18446744073709551616
+    v434 = add v427, v433
+    v435 = cast v77 as Field
+    v437 = mul v435, Field 4722366482869645213696
+    v438 = add v431, v437
+    v439 = cast v268 as Field
+    v440 = mul v439, Field 4722366482869645213696
+    v441 = add v434, v440
+    v442 = cast v65 as Field
+    v444 = mul v442, Field 1208925819614629174706176
+    v445 = add v438, v444
+    v446 = cast v256 as Field
+    v447 = mul v446, Field 1208925819614629174706176
+    v448 = add v441, v447
+    v449 = cast v53 as Field
+    v451 = mul v449, Field 309485009821345068724781056
+    v452 = add v445, v451
+    v453 = cast v244 as Field
+    v454 = mul v453, Field 309485009821345068724781056
+    v455 = add v448, v454
+    v456 = cast v41 as Field
+    v458 = mul v456, Field 79228162514264337593543950336
+    v459 = add v452, v458
+    v460 = cast v232 as Field
+    v461 = mul v460, Field 79228162514264337593543950336
+    v462 = add v455, v461
+    v463 = cast v29 as Field
+    v465 = mul v463, Field 20282409603651670423947251286016
+    v466 = add v459, v465
+    v467 = cast v220 as Field
+    v468 = mul v467, Field 20282409603651670423947251286016
+    v469 = add v462, v468
+    v470 = cast v16 as Field
+    v472 = mul v470, Field 5192296858534827628530496329220096
+    v473 = add v466, v472
+    v474 = cast v208 as Field
+    v475 = mul v474, Field 5192296858534827628530496329220096
+    v476 = add v469, v475
+    v477 = cast v9 as Field
+    v479 = mul v477, Field 1329227995784915872903807060280344576
+    v480 = add v473, v479
+    v481 = cast v196 as Field
+    v482 = mul v481, Field 1329227995784915872903807060280344576
+    v483 = add v476, v482
+    v485 = mul v480, Field 340282366920938463463374607431768211456
+    v486 = add v483, v485
+    v488 = eq v4, Field 0
+    v489 = not v488
+    enable_side_effects v489
+    v491 = call f1(v4, Field 0) -> u1
+    v492 = mul v489, v491
+    enable_side_effects v492
+    v494, v495 = call f3(Field 0) -> (Field, Field)
+    v496 = cast v492 as Field
+    v497 = mul v494, v496
+    range_check v497 to 128 bits
+    v498 = mul v495, v496
+    range_check v498 to 128 bits
+    v499 = mul Field 340282366920938463463374607431768211456, v495
+    v500 = add v494, v499
+    v501 = mul v500, v496
+    constrain Field 0 == v501
+    v504 = call f2(Field 53438638232309528389504892708671455233, v494) -> u1
+    v505 = sub Field 53438638232309528389504892708671455233, v494
+    v507 = sub v505, Field 1
+    v508 = cast v504 as Field
+    v509 = mul v508, Field 340282366920938463463374607431768211456
+    v510 = add v507, v509
+    v512 = sub Field 64323764613183177041862057485226039389, v495
+    v513 = sub v512, v508
+    v514 = mul v510, v496
+    range_check v514 to 128 bits
+    v515 = mul v513, v496
+    range_check v515 to 128 bits
+    v517, v518 = call f3(v4) -> (Field, Field)
+    v519 = mul v517, v496
+    range_check v519 to 128 bits
+    v520 = mul v518, v496
+    range_check v520 to 128 bits
+    v521 = mul Field 340282366920938463463374607431768211456, v518
+    v522 = add v517, v521
+    v523 = mul v4, v496
+    v524 = mul v522, v496
+    constrain v523 == v524
+    v526 = call f2(Field 53438638232309528389504892708671455233, v517) -> u1
+    v527 = sub Field 53438638232309528389504892708671455233, v517
+    v528 = sub v527, Field 1
+    v529 = cast v526 as Field
+    v530 = mul v529, Field 340282366920938463463374607431768211456
+    v531 = add v528, v530
+    v532 = sub Field 64323764613183177041862057485226039389, v518
+    v533 = sub v532, v529
+    v534 = mul v531, v496
+    range_check v534 to 128 bits
+    v535 = mul v533, v496
+    range_check v535 to 128 bits
+    v537 = call f2(v494, v517) -> u1
+    v538 = sub v494, v517
+    v539 = sub v538, Field 1
+    v540 = cast v537 as Field
+    v541 = mul v540, Field 340282366920938463463374607431768211456
+    v542 = add v539, v541
+    v543 = sub v495, v518
+    v544 = sub v543, v540
+    v545 = mul v542, v496
+    range_check v545 to 128 bits
+    v546 = mul v544, v496
+    range_check v546 to 128 bits
+    v547 = not v491
+    v548 = mul v489, v547
+    enable_side_effects v548
+    v550, v551 = call f3(v4) -> (Field, Field)
+    v552 = cast v548 as Field
+    v553 = mul v550, v552
+    range_check v553 to 128 bits
+    v554 = mul v551, v552
+    range_check v554 to 128 bits
+    v555 = mul Field 340282366920938463463374607431768211456, v551
+    v556 = add v550, v555
+    v557 = mul v4, v552
+    v558 = mul v556, v552
+    constrain v557 == v558
+    v560 = call f2(Field 53438638232309528389504892708671455233, v550) -> u1
+    v561 = sub Field 53438638232309528389504892708671455233, v550
+    v562 = sub v561, Field 1
+    v563 = cast v560 as Field
+    v564 = mul v563, Field 340282366920938463463374607431768211456
+    v565 = add v562, v564
+    v566 = sub Field 64323764613183177041862057485226039389, v551
+    v567 = sub v566, v563
+    v568 = mul v565, v552
+    range_check v568 to 128 bits
+    v569 = mul v567, v552
+    range_check v569 to 128 bits
+    v571, v572 = call f3(Field 0) -> (Field, Field)
+    v573 = mul v571, v552
+    range_check v573 to 128 bits
+    v574 = mul v572, v552
+    range_check v574 to 128 bits
+    v575 = mul Field 340282366920938463463374607431768211456, v572
+    v576 = add v571, v575
+    v577 = mul v576, v552
+    constrain Field 0 == v577
+    v579 = call f2(Field 53438638232309528389504892708671455233, v571) -> u1
+    v580 = sub Field 53438638232309528389504892708671455233, v571
+    v581 = sub v580, Field 1
+    v582 = cast v579 as Field
+    v583 = mul v582, Field 340282366920938463463374607431768211456
+    v584 = add v581, v583
+    v585 = sub Field 64323764613183177041862057485226039389, v572
+    v586 = sub v585, v582
+    v587 = mul v584, v552
+    range_check v587 to 128 bits
+    v588 = mul v586, v552
+    range_check v588 to 128 bits
+    v590 = call f2(v550, v571) -> u1
+    v591 = sub v550, v571
+    v592 = sub v591, Field 1
+    v593 = cast v590 as Field
+    v594 = mul v593, Field 340282366920938463463374607431768211456
+    v595 = add v592, v594
+    v596 = sub v551, v572
+    v597 = sub v596, v593
+    v598 = mul v595, v552
+    range_check v598 to 128 bits
+    v599 = mul v597, v552
+    range_check v599 to 128 bits
+    enable_side_effects u1 1
+    v600 = sub v552, v486
+    return v600
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = truncate v4 to 64 bits, max_bit_size: 254
+    v6 = sub v4, v5
+    v7 = div v6, Field 18446744073709551616
+    v8 = truncate v7 to 64 bits, max_bit_size: 254
+    v9 = sub v7, v8
+    v10 = div v9, Field 18446744073709551616
+    v11 = mul v8, Field 18446744073709551616
+    v12 = add v11, v5
+    return v12, v10
+}
+
+After Simplifying::
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v7 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v9 = array_get v7, index u32 0 -> u8
+    v11 = eq v9, u8 48
+    v12 = not v11
+    v13 = lt v9, u8 48
+    enable_side_effects v12
+    v14 = mul v13, v12
+    constrain v14 == v12
+    enable_side_effects v11
+    v16 = array_get v7, index u32 1 -> u8
+    v18 = eq v16, u8 100
+    v19 = not v18
+    v20 = mul v11, v19
+    v21 = lt v16, u8 100
+    enable_side_effects v20
+    v22 = mul v21, v20
+    constrain v22 == v20
+    v23 = not v20
+    v24 = mul v23, v12
+    v25 = unchecked_add v20, v24
+    enable_side_effects u1 1
+    v27 = not v25
+    enable_side_effects v27
+    v29 = array_get v7, index u32 2 -> u8
+    v31 = eq v29, u8 78
+    v32 = not v31
+    v33 = mul v27, v32
+    v34 = lt v29, u8 78
+    enable_side_effects v33
+    v35 = mul v34, v33
+    constrain v35 == v33
+    v36 = not v33
+    v37 = mul v36, v25
+    v38 = unchecked_add v33, v37
+    enable_side_effects u1 1
+    v39 = not v38
+    enable_side_effects v39
+    v41 = array_get v7, index u32 3 -> u8
+    v43 = eq v41, u8 114
+    v44 = not v43
+    v45 = mul v39, v44
+    v46 = lt v41, u8 114
+    enable_side_effects v45
+    v47 = mul v46, v45
+    constrain v47 == v45
+    v48 = not v45
+    v49 = mul v48, v38
+    v50 = unchecked_add v45, v49
+    enable_side_effects u1 1
+    v51 = not v50
+    enable_side_effects v51
+    v53 = array_get v7, index u32 4 -> u8
+    v55 = eq v53, u8 225
+    v56 = not v55
+    v57 = mul v51, v56
+    v58 = lt v53, u8 225
+    enable_side_effects v57
+    v59 = mul v58, v57
+    constrain v59 == v57
+    v60 = not v57
+    v61 = mul v60, v50
+    v62 = unchecked_add v57, v61
+    enable_side_effects u1 1
+    v63 = not v62
+    enable_side_effects v63
+    v65 = array_get v7, index u32 5 -> u8
+    v67 = eq v65, u8 49
+    v68 = not v67
+    v69 = mul v63, v68
+    v70 = lt v65, u8 49
+    enable_side_effects v69
+    v71 = mul v70, v69
+    constrain v71 == v69
+    v72 = not v69
+    v73 = mul v72, v62
+    v74 = unchecked_add v69, v73
+    enable_side_effects u1 1
+    v75 = not v74
+    enable_side_effects v75
+    v77 = array_get v7, index u32 6 -> u8
+    v79 = eq v77, u8 160
+    v80 = not v79
+    v81 = mul v75, v80
+    v82 = lt v77, u8 160
+    enable_side_effects v81
+    v83 = mul v82, v81
+    constrain v83 == v81
+    v84 = not v81
+    v85 = mul v84, v74
+    v86 = unchecked_add v81, v85
+    enable_side_effects u1 1
+    v87 = not v86
+    enable_side_effects v87
+    v89 = array_get v7, index u32 7 -> u8
+    v91 = eq v89, u8 41
+    v92 = not v91
+    v93 = mul v87, v92
+    v94 = lt v89, u8 41
+    enable_side_effects v93
+    v95 = mul v94, v93
+    constrain v95 == v93
+    v96 = not v93
+    v97 = mul v96, v86
+    v98 = unchecked_add v93, v97
+    enable_side_effects u1 1
+    v99 = not v98
+    enable_side_effects v99
+    v101 = array_get v7, index u32 8 -> u8
+    v103 = eq v101, u8 184
+    v104 = not v103
+    v105 = mul v99, v104
+    v106 = lt v101, u8 184
+    enable_side_effects v105
+    v107 = mul v106, v105
+    constrain v107 == v105
+    v108 = not v105
+    v109 = mul v108, v98
+    v110 = unchecked_add v105, v109
+    enable_side_effects u1 1
+    v111 = not v110
+    enable_side_effects v111
+    v113 = array_get v7, index u32 9 -> u8
+    v115 = eq v113, u8 80
+    v116 = not v115
+    v117 = mul v111, v116
+    v118 = lt v113, u8 80
+    enable_side_effects v117
+    v119 = mul v118, v117
+    constrain v119 == v117
+    v120 = not v117
+    v121 = mul v120, v110
+    v122 = unchecked_add v117, v121
+    enable_side_effects u1 1
+    v123 = not v122
+    enable_side_effects v123
+    v125 = array_get v7, index u32 10 -> u8
+    v127 = eq v125, u8 69
+    v128 = not v127
+    v129 = mul v123, v128
+    v130 = lt v125, u8 69
+    enable_side_effects v129
+    v131 = mul v130, v129
+    constrain v131 == v129
+    v132 = not v129
+    v133 = mul v132, v122
+    v134 = unchecked_add v129, v133
+    enable_side_effects u1 1
+    v135 = not v134
+    enable_side_effects v135
+    v137 = array_get v7, index u32 11 -> u8
+    v139 = eq v137, u8 182
+    v140 = not v139
+    v141 = mul v135, v140
+    v142 = lt v137, u8 182
+    enable_side_effects v141
+    v143 = mul v142, v141
+    constrain v143 == v141
+    v144 = not v141
+    v145 = mul v144, v134
+    v146 = unchecked_add v141, v145
+    enable_side_effects u1 1
+    v147 = not v146
+    enable_side_effects v147
+    v149 = array_get v7, index u32 12 -> u8
+    v151 = eq v149, u8 129
+    v152 = not v151
+    v153 = mul v147, v152
+    v154 = lt v149, u8 129
+    enable_side_effects v153
+    v155 = mul v154, v153
+    constrain v155 == v153
+    v156 = not v153
+    v157 = mul v156, v146
+    v158 = unchecked_add v153, v157
+    enable_side_effects u1 1
+    v159 = not v158
+    enable_side_effects v159
+    v161 = array_get v7, index u32 13 -> u8
+    v162 = eq v161, u8 129
+    v163 = not v162
+    v164 = mul v159, v163
+    v165 = lt v161, u8 129
+    enable_side_effects v164
+    v166 = mul v165, v164
+    constrain v166 == v164
+    v167 = not v164
+    v168 = mul v167, v158
+    v169 = unchecked_add v164, v168
+    enable_side_effects u1 1
+    v170 = not v169
+    enable_side_effects v170
+    v172 = array_get v7, index u32 14 -> u8
+    v174 = eq v172, u8 88
+    v175 = not v174
+    v176 = mul v170, v175
+    v177 = lt v172, u8 88
+    enable_side_effects v176
+    v178 = mul v177, v176
+    constrain v178 == v176
+    v179 = not v176
+    v180 = mul v179, v169
+    v181 = unchecked_add v176, v180
+    enable_side_effects u1 1
+    v182 = not v181
+    enable_side_effects v182
+    v184 = array_get v7, index u32 15 -> u8
+    v186 = eq v184, u8 93
+    v187 = not v186
+    v188 = mul v182, v187
+    v189 = lt v184, u8 93
+    enable_side_effects v188
+    v190 = mul v189, v188
+    constrain v190 == v188
+    v191 = not v188
+    v192 = mul v191, v181
+    v193 = unchecked_add v188, v192
+    enable_side_effects u1 1
+    v194 = not v193
+    enable_side_effects v194
+    v196 = array_get v7, index u32 16 -> u8
+    v198 = eq v196, u8 40
+    v199 = not v198
+    v200 = mul v194, v199
+    v201 = lt v196, u8 40
+    enable_side_effects v200
+    v202 = mul v201, v200
+    constrain v202 == v200
+    v203 = not v200
+    v204 = mul v203, v193
+    v205 = unchecked_add v200, v204
+    enable_side_effects u1 1
+    v206 = not v205
+    enable_side_effects v206
+    v208 = array_get v7, index u32 17 -> u8
+    v210 = eq v208, u8 51
+    v211 = not v210
+    v212 = mul v206, v211
+    v213 = lt v208, u8 51
+    enable_side_effects v212
+    v214 = mul v213, v212
+    constrain v214 == v212
+    v215 = not v212
+    v216 = mul v215, v205
+    v217 = unchecked_add v212, v216
+    enable_side_effects u1 1
+    v218 = not v217
+    enable_side_effects v218
+    v220 = array_get v7, index u32 18 -> u8
+    v222 = eq v220, u8 232
+    v223 = not v222
+    v224 = mul v218, v223
+    v225 = lt v220, u8 232
+    enable_side_effects v224
+    v226 = mul v225, v224
+    constrain v226 == v224
+    v227 = not v224
+    v228 = mul v227, v217
+    v229 = unchecked_add v224, v228
+    enable_side_effects u1 1
+    v230 = not v229
+    enable_side_effects v230
+    v232 = array_get v7, index u32 19 -> u8
+    v234 = eq v232, u8 72
+    v235 = not v234
+    v236 = mul v230, v235
+    v237 = lt v232, u8 72
+    enable_side_effects v236
+    v238 = mul v237, v236
+    constrain v238 == v236
+    v239 = not v236
+    v240 = mul v239, v229
+    v241 = unchecked_add v236, v240
+    enable_side_effects u1 1
+    v242 = not v241
+    enable_side_effects v242
+    v244 = array_get v7, index u32 20 -> u8
+    v246 = eq v244, u8 121
+    v247 = not v246
+    v248 = mul v242, v247
+    v249 = lt v244, u8 121
+    enable_side_effects v248
+    v250 = mul v249, v248
+    constrain v250 == v248
+    v251 = not v248
+    v252 = mul v251, v241
+    v253 = unchecked_add v248, v252
+    enable_side_effects u1 1
+    v254 = not v253
+    enable_side_effects v254
+    v256 = array_get v7, index u32 21 -> u8
+    v258 = eq v256, u8 185
+    v259 = not v258
+    v260 = mul v254, v259
+    v261 = lt v256, u8 185
+    enable_side_effects v260
+    v262 = mul v261, v260
+    constrain v262 == v260
+    v263 = not v260
+    v264 = mul v263, v253
+    v265 = unchecked_add v260, v264
+    enable_side_effects u1 1
+    v266 = not v265
+    enable_side_effects v266
+    v268 = array_get v7, index u32 22 -> u8
+    v270 = eq v268, u8 112
+    v271 = not v270
+    v272 = mul v266, v271
+    v273 = lt v268, u8 112
+    enable_side_effects v272
+    v274 = mul v273, v272
+    constrain v274 == v272
+    v275 = not v272
+    v276 = mul v275, v265
+    v277 = unchecked_add v272, v276
+    enable_side_effects u1 1
+    v278 = not v277
+    enable_side_effects v278
+    v280 = array_get v7, index u32 23 -> u8
+    v282 = eq v280, u8 145
+    v283 = not v282
+    v284 = mul v278, v283
+    v285 = lt v280, u8 145
+    enable_side_effects v284
+    v286 = mul v285, v284
+    constrain v286 == v284
+    v287 = not v284
+    v288 = mul v287, v277
+    v289 = unchecked_add v284, v288
+    enable_side_effects u1 1
+    v290 = not v289
+    enable_side_effects v290
+    v292 = array_get v7, index u32 24 -> u8
+    v294 = eq v292, u8 67
+    v295 = not v294
+    v296 = mul v290, v295
+    v297 = lt v292, u8 67
+    enable_side_effects v296
+    v298 = mul v297, v296
+    constrain v298 == v296
+    v299 = not v296
+    v300 = mul v299, v289
+    v301 = unchecked_add v296, v300
+    enable_side_effects u1 1
+    v302 = not v301
+    enable_side_effects v302
+    v304 = array_get v7, index u32 25 -> u8
+    v305 = eq v304, u8 225
+    v306 = not v305
+    v307 = mul v302, v306
+    v308 = lt v304, u8 225
+    enable_side_effects v307
+    v309 = mul v308, v307
+    constrain v309 == v307
+    v310 = not v307
+    v311 = mul v310, v301
+    v312 = unchecked_add v307, v311
+    enable_side_effects u1 1
+    v313 = not v312
+    enable_side_effects v313
+    v315 = array_get v7, index u32 26 -> u8
+    v317 = eq v315, u8 245
+    v318 = not v317
+    v319 = mul v313, v318
+    v320 = lt v315, u8 245
+    enable_side_effects v319
+    v321 = mul v320, v319
+    constrain v321 == v319
+    v322 = not v319
+    v323 = mul v322, v312
+    v324 = unchecked_add v319, v323
+    enable_side_effects u1 1
+    v325 = not v324
+    enable_side_effects v325
+    v327 = array_get v7, index u32 27 -> u8
+    v329 = eq v327, u8 147
+    v330 = not v329
+    v331 = mul v325, v330
+    v332 = lt v327, u8 147
+    enable_side_effects v331
+    v333 = mul v332, v331
+    constrain v333 == v331
+    v334 = not v331
+    v335 = mul v334, v324
+    v336 = unchecked_add v331, v335
+    enable_side_effects u1 1
+    v337 = not v336
+    enable_side_effects v337
+    v339 = array_get v7, index u32 28 -> u8
+    v341 = eq v339, u8 240
+    v342 = not v341
+    v343 = mul v337, v342
+    v344 = lt v339, u8 240
+    enable_side_effects v343
+    v345 = mul v344, v343
+    constrain v345 == v343
+    v346 = not v343
+    v347 = mul v346, v336
+    v348 = unchecked_add v343, v347
+    enable_side_effects u1 1
+    v349 = not v348
+    enable_side_effects v349
+    v351 = array_get v7, index u32 29 -> u8
+    v353 = eq v351, u8 0
+    v354 = not v353
+    v355 = mul v349, v354
+    constrain u1 0 == v355
+    enable_side_effects u1 0
+    v357 = unchecked_add v355, v348
+    enable_side_effects u1 1
+    v358 = not v357
+    enable_side_effects v358
+    v360 = array_get v7, index u32 30 -> u8
+    v361 = eq v360, u8 0
+    v362 = not v361
+    v363 = mul v358, v362
+    constrain u1 0 == v363
+    enable_side_effects u1 0
+    v364 = unchecked_add v363, v357
+    enable_side_effects u1 1
+    v365 = not v364
+    enable_side_effects v365
+    v367 = array_get v7, index u32 31 -> u8
+    v369 = eq v367, u8 1
+    v370 = not v369
+    v371 = mul v365, v370
+    v372 = cast v371 as u8
+    enable_side_effects v371
+    v373 = unchecked_mul v367, v372
+    constrain v373 == u8 0
+    v374 = not v371
+    v375 = mul v374, v364
+    v376 = unchecked_add v371, v375
+    enable_side_effects u1 1
+    constrain v376 == u1 1
+    v377 = cast v184 as Field
+    v378 = cast v367 as Field
+    v379 = cast v172 as Field
+    v381 = mul v379, Field 256
+    v382 = add v377, v381
+    v383 = cast v360 as Field
+    v384 = mul v383, Field 256
+    v385 = add v378, v384
+    v386 = cast v161 as Field
+    v388 = mul v386, Field 65536
+    v389 = add v382, v388
+    v390 = cast v351 as Field
+    v391 = mul v390, Field 65536
+    v392 = add v385, v391
+    v393 = cast v149 as Field
+    v395 = mul v393, Field 16777216
+    v396 = add v389, v395
+    v397 = cast v339 as Field
+    v398 = mul v397, Field 16777216
+    v399 = add v392, v398
+    v400 = cast v137 as Field
+    v402 = mul v400, Field 4294967296
+    v403 = add v396, v402
+    v404 = cast v327 as Field
+    v405 = mul v404, Field 4294967296
+    v406 = add v399, v405
+    v407 = cast v125 as Field
+    v409 = mul v407, Field 1099511627776
+    v410 = add v403, v409
+    v411 = cast v315 as Field
+    v412 = mul v411, Field 1099511627776
+    v413 = add v406, v412
+    v414 = cast v113 as Field
+    v416 = mul v414, Field 281474976710656
+    v417 = add v410, v416
+    v418 = cast v304 as Field
+    v419 = mul v418, Field 281474976710656
+    v420 = add v413, v419
+    v421 = cast v101 as Field
+    v423 = mul v421, Field 72057594037927936
+    v424 = add v417, v423
+    v425 = cast v292 as Field
+    v426 = mul v425, Field 72057594037927936
+    v427 = add v420, v426
+    v428 = cast v89 as Field
+    v430 = mul v428, Field 18446744073709551616
+    v431 = add v424, v430
+    v432 = cast v280 as Field
+    v433 = mul v432, Field 18446744073709551616
+    v434 = add v427, v433
+    v435 = cast v77 as Field
+    v437 = mul v435, Field 4722366482869645213696
+    v438 = add v431, v437
+    v439 = cast v268 as Field
+    v440 = mul v439, Field 4722366482869645213696
+    v441 = add v434, v440
+    v442 = cast v65 as Field
+    v444 = mul v442, Field 1208925819614629174706176
+    v445 = add v438, v444
+    v446 = cast v256 as Field
+    v447 = mul v446, Field 1208925819614629174706176
+    v448 = add v441, v447
+    v449 = cast v53 as Field
+    v451 = mul v449, Field 309485009821345068724781056
+    v452 = add v445, v451
+    v453 = cast v244 as Field
+    v454 = mul v453, Field 309485009821345068724781056
+    v455 = add v448, v454
+    v456 = cast v41 as Field
+    v458 = mul v456, Field 79228162514264337593543950336
+    v459 = add v452, v458
+    v460 = cast v232 as Field
+    v461 = mul v460, Field 79228162514264337593543950336
+    v462 = add v455, v461
+    v463 = cast v29 as Field
+    v465 = mul v463, Field 20282409603651670423947251286016
+    v466 = add v459, v465
+    v467 = cast v220 as Field
+    v468 = mul v467, Field 20282409603651670423947251286016
+    v469 = add v462, v468
+    v470 = cast v16 as Field
+    v472 = mul v470, Field 5192296858534827628530496329220096
+    v473 = add v466, v472
+    v474 = cast v208 as Field
+    v475 = mul v474, Field 5192296858534827628530496329220096
+    v476 = add v469, v475
+    v477 = cast v9 as Field
+    v479 = mul v477, Field 1329227995784915872903807060280344576
+    v480 = add v473, v479
+    v481 = cast v196 as Field
+    v482 = mul v481, Field 1329227995784915872903807060280344576
+    v483 = add v476, v482
+    v485 = mul v480, Field 340282366920938463463374607431768211456
+    v486 = add v483, v485
+    v488 = eq v4, Field 0
+    v489 = not v488
+    enable_side_effects v489
+    v491 = call f1(v4, Field 0) -> u1
+    v492 = mul v489, v491
+    enable_side_effects v492
+    v494, v495 = call f3(Field 0) -> (Field, Field)
+    v496 = cast v492 as Field
+    v497 = mul v494, v496
+    range_check v497 to 128 bits
+    v498 = mul v495, v496
+    range_check v498 to 128 bits
+    v499 = mul Field 340282366920938463463374607431768211456, v495
+    v500 = add v494, v499
+    v501 = mul v500, v496
+    constrain Field 0 == v501
+    v504 = call f2(Field 53438638232309528389504892708671455233, v494) -> u1
+    v505 = sub Field 53438638232309528389504892708671455233, v494
+    v507 = sub v505, Field 1
+    v508 = cast v504 as Field
+    v509 = mul v508, Field 340282366920938463463374607431768211456
+    v510 = add v507, v509
+    v512 = sub Field 64323764613183177041862057485226039389, v495
+    v513 = sub v512, v508
+    v514 = mul v510, v496
+    range_check v514 to 128 bits
+    v515 = mul v513, v496
+    range_check v515 to 128 bits
+    v517, v518 = call f3(v4) -> (Field, Field)
+    v519 = mul v517, v496
+    range_check v519 to 128 bits
+    v520 = mul v518, v496
+    range_check v520 to 128 bits
+    v521 = mul Field 340282366920938463463374607431768211456, v518
+    v522 = add v517, v521
+    v523 = mul v4, v496
+    v524 = mul v522, v496
+    constrain v523 == v524
+    v526 = call f2(Field 53438638232309528389504892708671455233, v517) -> u1
+    v527 = sub Field 53438638232309528389504892708671455233, v517
+    v528 = sub v527, Field 1
+    v529 = cast v526 as Field
+    v530 = mul v529, Field 340282366920938463463374607431768211456
+    v531 = add v528, v530
+    v532 = sub Field 64323764613183177041862057485226039389, v518
+    v533 = sub v532, v529
+    v534 = mul v531, v496
+    range_check v534 to 128 bits
+    v535 = mul v533, v496
+    range_check v535 to 128 bits
+    v537 = call f2(v494, v517) -> u1
+    v538 = sub v494, v517
+    v539 = sub v538, Field 1
+    v540 = cast v537 as Field
+    v541 = mul v540, Field 340282366920938463463374607431768211456
+    v542 = add v539, v541
+    v543 = sub v495, v518
+    v544 = sub v543, v540
+    v545 = mul v542, v496
+    range_check v545 to 128 bits
+    v546 = mul v544, v496
+    range_check v546 to 128 bits
+    v547 = not v491
+    v548 = mul v489, v547
+    enable_side_effects v548
+    v550, v551 = call f3(v4) -> (Field, Field)
+    v552 = cast v548 as Field
+    v553 = mul v550, v552
+    range_check v553 to 128 bits
+    v554 = mul v551, v552
+    range_check v554 to 128 bits
+    v555 = mul Field 340282366920938463463374607431768211456, v551
+    v556 = add v550, v555
+    v557 = mul v4, v552
+    v558 = mul v556, v552
+    constrain v557 == v558
+    v560 = call f2(Field 53438638232309528389504892708671455233, v550) -> u1
+    v561 = sub Field 53438638232309528389504892708671455233, v550
+    v562 = sub v561, Field 1
+    v563 = cast v560 as Field
+    v564 = mul v563, Field 340282366920938463463374607431768211456
+    v565 = add v562, v564
+    v566 = sub Field 64323764613183177041862057485226039389, v551
+    v567 = sub v566, v563
+    v568 = mul v565, v552
+    range_check v568 to 128 bits
+    v569 = mul v567, v552
+    range_check v569 to 128 bits
+    v571, v572 = call f3(Field 0) -> (Field, Field)
+    v573 = mul v571, v552
+    range_check v573 to 128 bits
+    v574 = mul v572, v552
+    range_check v574 to 128 bits
+    v575 = mul Field 340282366920938463463374607431768211456, v572
+    v576 = add v571, v575
+    v577 = mul v576, v552
+    constrain Field 0 == v577
+    v579 = call f2(Field 53438638232309528389504892708671455233, v571) -> u1
+    v580 = sub Field 53438638232309528389504892708671455233, v571
+    v581 = sub v580, Field 1
+    v582 = cast v579 as Field
+    v583 = mul v582, Field 340282366920938463463374607431768211456
+    v584 = add v581, v583
+    v585 = sub Field 64323764613183177041862057485226039389, v572
+    v586 = sub v585, v582
+    v587 = mul v584, v552
+    range_check v587 to 128 bits
+    v588 = mul v586, v552
+    range_check v588 to 128 bits
+    v590 = call f2(v550, v571) -> u1
+    v591 = sub v550, v571
+    v592 = sub v591, Field 1
+    v593 = cast v590 as Field
+    v594 = mul v593, Field 340282366920938463463374607431768211456
+    v595 = add v592, v594
+    v596 = sub v551, v572
+    v597 = sub v596, v593
+    v598 = mul v595, v552
+    range_check v598 to 128 bits
+    v599 = mul v597, v552
+    range_check v599 to 128 bits
+    enable_side_effects u1 1
+    v600 = sub v552, v486
+    return v600
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = truncate v4 to 64 bits, max_bit_size: 254
+    v6 = sub v4, v5
+    v7 = div v6, Field 18446744073709551616
+    v8 = truncate v7 to 64 bits, max_bit_size: 254
+    v9 = sub v7, v8
+    v10 = div v9, Field 18446744073709551616
+    v11 = mul v8, Field 18446744073709551616
+    v12 = add v11, v5
+    return v12, v10
+}
+
+After Array Set Optimizations:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v7 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v9 = array_get v7, index u32 0 -> u8
+    v11 = eq v9, u8 48
+    v12 = not v11
+    v13 = lt v9, u8 48
+    enable_side_effects v12
+    v14 = mul v13, v12
+    constrain v14 == v12
+    enable_side_effects v11
+    v16 = array_get v7, index u32 1 -> u8
+    v18 = eq v16, u8 100
+    v19 = not v18
+    v20 = mul v11, v19
+    v21 = lt v16, u8 100
+    enable_side_effects v20
+    v22 = mul v21, v20
+    constrain v22 == v20
+    v23 = not v20
+    v24 = mul v23, v12
+    v25 = unchecked_add v20, v24
+    enable_side_effects u1 1
+    v27 = not v25
+    enable_side_effects v27
+    v29 = array_get v7, index u32 2 -> u8
+    v31 = eq v29, u8 78
+    v32 = not v31
+    v33 = mul v27, v32
+    v34 = lt v29, u8 78
+    enable_side_effects v33
+    v35 = mul v34, v33
+    constrain v35 == v33
+    v36 = not v33
+    v37 = mul v36, v25
+    v38 = unchecked_add v33, v37
+    enable_side_effects u1 1
+    v39 = not v38
+    enable_side_effects v39
+    v41 = array_get v7, index u32 3 -> u8
+    v43 = eq v41, u8 114
+    v44 = not v43
+    v45 = mul v39, v44
+    v46 = lt v41, u8 114
+    enable_side_effects v45
+    v47 = mul v46, v45
+    constrain v47 == v45
+    v48 = not v45
+    v49 = mul v48, v38
+    v50 = unchecked_add v45, v49
+    enable_side_effects u1 1
+    v51 = not v50
+    enable_side_effects v51
+    v53 = array_get v7, index u32 4 -> u8
+    v55 = eq v53, u8 225
+    v56 = not v55
+    v57 = mul v51, v56
+    v58 = lt v53, u8 225
+    enable_side_effects v57
+    v59 = mul v58, v57
+    constrain v59 == v57
+    v60 = not v57
+    v61 = mul v60, v50
+    v62 = unchecked_add v57, v61
+    enable_side_effects u1 1
+    v63 = not v62
+    enable_side_effects v63
+    v65 = array_get v7, index u32 5 -> u8
+    v67 = eq v65, u8 49
+    v68 = not v67
+    v69 = mul v63, v68
+    v70 = lt v65, u8 49
+    enable_side_effects v69
+    v71 = mul v70, v69
+    constrain v71 == v69
+    v72 = not v69
+    v73 = mul v72, v62
+    v74 = unchecked_add v69, v73
+    enable_side_effects u1 1
+    v75 = not v74
+    enable_side_effects v75
+    v77 = array_get v7, index u32 6 -> u8
+    v79 = eq v77, u8 160
+    v80 = not v79
+    v81 = mul v75, v80
+    v82 = lt v77, u8 160
+    enable_side_effects v81
+    v83 = mul v82, v81
+    constrain v83 == v81
+    v84 = not v81
+    v85 = mul v84, v74
+    v86 = unchecked_add v81, v85
+    enable_side_effects u1 1
+    v87 = not v86
+    enable_side_effects v87
+    v89 = array_get v7, index u32 7 -> u8
+    v91 = eq v89, u8 41
+    v92 = not v91
+    v93 = mul v87, v92
+    v94 = lt v89, u8 41
+    enable_side_effects v93
+    v95 = mul v94, v93
+    constrain v95 == v93
+    v96 = not v93
+    v97 = mul v96, v86
+    v98 = unchecked_add v93, v97
+    enable_side_effects u1 1
+    v99 = not v98
+    enable_side_effects v99
+    v101 = array_get v7, index u32 8 -> u8
+    v103 = eq v101, u8 184
+    v104 = not v103
+    v105 = mul v99, v104
+    v106 = lt v101, u8 184
+    enable_side_effects v105
+    v107 = mul v106, v105
+    constrain v107 == v105
+    v108 = not v105
+    v109 = mul v108, v98
+    v110 = unchecked_add v105, v109
+    enable_side_effects u1 1
+    v111 = not v110
+    enable_side_effects v111
+    v113 = array_get v7, index u32 9 -> u8
+    v115 = eq v113, u8 80
+    v116 = not v115
+    v117 = mul v111, v116
+    v118 = lt v113, u8 80
+    enable_side_effects v117
+    v119 = mul v118, v117
+    constrain v119 == v117
+    v120 = not v117
+    v121 = mul v120, v110
+    v122 = unchecked_add v117, v121
+    enable_side_effects u1 1
+    v123 = not v122
+    enable_side_effects v123
+    v125 = array_get v7, index u32 10 -> u8
+    v127 = eq v125, u8 69
+    v128 = not v127
+    v129 = mul v123, v128
+    v130 = lt v125, u8 69
+    enable_side_effects v129
+    v131 = mul v130, v129
+    constrain v131 == v129
+    v132 = not v129
+    v133 = mul v132, v122
+    v134 = unchecked_add v129, v133
+    enable_side_effects u1 1
+    v135 = not v134
+    enable_side_effects v135
+    v137 = array_get v7, index u32 11 -> u8
+    v139 = eq v137, u8 182
+    v140 = not v139
+    v141 = mul v135, v140
+    v142 = lt v137, u8 182
+    enable_side_effects v141
+    v143 = mul v142, v141
+    constrain v143 == v141
+    v144 = not v141
+    v145 = mul v144, v134
+    v146 = unchecked_add v141, v145
+    enable_side_effects u1 1
+    v147 = not v146
+    enable_side_effects v147
+    v149 = array_get v7, index u32 12 -> u8
+    v151 = eq v149, u8 129
+    v152 = not v151
+    v153 = mul v147, v152
+    v154 = lt v149, u8 129
+    enable_side_effects v153
+    v155 = mul v154, v153
+    constrain v155 == v153
+    v156 = not v153
+    v157 = mul v156, v146
+    v158 = unchecked_add v153, v157
+    enable_side_effects u1 1
+    v159 = not v158
+    enable_side_effects v159
+    v161 = array_get v7, index u32 13 -> u8
+    v162 = eq v161, u8 129
+    v163 = not v162
+    v164 = mul v159, v163
+    v165 = lt v161, u8 129
+    enable_side_effects v164
+    v166 = mul v165, v164
+    constrain v166 == v164
+    v167 = not v164
+    v168 = mul v167, v158
+    v169 = unchecked_add v164, v168
+    enable_side_effects u1 1
+    v170 = not v169
+    enable_side_effects v170
+    v172 = array_get v7, index u32 14 -> u8
+    v174 = eq v172, u8 88
+    v175 = not v174
+    v176 = mul v170, v175
+    v177 = lt v172, u8 88
+    enable_side_effects v176
+    v178 = mul v177, v176
+    constrain v178 == v176
+    v179 = not v176
+    v180 = mul v179, v169
+    v181 = unchecked_add v176, v180
+    enable_side_effects u1 1
+    v182 = not v181
+    enable_side_effects v182
+    v184 = array_get v7, index u32 15 -> u8
+    v186 = eq v184, u8 93
+    v187 = not v186
+    v188 = mul v182, v187
+    v189 = lt v184, u8 93
+    enable_side_effects v188
+    v190 = mul v189, v188
+    constrain v190 == v188
+    v191 = not v188
+    v192 = mul v191, v181
+    v193 = unchecked_add v188, v192
+    enable_side_effects u1 1
+    v194 = not v193
+    enable_side_effects v194
+    v196 = array_get v7, index u32 16 -> u8
+    v198 = eq v196, u8 40
+    v199 = not v198
+    v200 = mul v194, v199
+    v201 = lt v196, u8 40
+    enable_side_effects v200
+    v202 = mul v201, v200
+    constrain v202 == v200
+    v203 = not v200
+    v204 = mul v203, v193
+    v205 = unchecked_add v200, v204
+    enable_side_effects u1 1
+    v206 = not v205
+    enable_side_effects v206
+    v208 = array_get v7, index u32 17 -> u8
+    v210 = eq v208, u8 51
+    v211 = not v210
+    v212 = mul v206, v211
+    v213 = lt v208, u8 51
+    enable_side_effects v212
+    v214 = mul v213, v212
+    constrain v214 == v212
+    v215 = not v212
+    v216 = mul v215, v205
+    v217 = unchecked_add v212, v216
+    enable_side_effects u1 1
+    v218 = not v217
+    enable_side_effects v218
+    v220 = array_get v7, index u32 18 -> u8
+    v222 = eq v220, u8 232
+    v223 = not v222
+    v224 = mul v218, v223
+    v225 = lt v220, u8 232
+    enable_side_effects v224
+    v226 = mul v225, v224
+    constrain v226 == v224
+    v227 = not v224
+    v228 = mul v227, v217
+    v229 = unchecked_add v224, v228
+    enable_side_effects u1 1
+    v230 = not v229
+    enable_side_effects v230
+    v232 = array_get v7, index u32 19 -> u8
+    v234 = eq v232, u8 72
+    v235 = not v234
+    v236 = mul v230, v235
+    v237 = lt v232, u8 72
+    enable_side_effects v236
+    v238 = mul v237, v236
+    constrain v238 == v236
+    v239 = not v236
+    v240 = mul v239, v229
+    v241 = unchecked_add v236, v240
+    enable_side_effects u1 1
+    v242 = not v241
+    enable_side_effects v242
+    v244 = array_get v7, index u32 20 -> u8
+    v246 = eq v244, u8 121
+    v247 = not v246
+    v248 = mul v242, v247
+    v249 = lt v244, u8 121
+    enable_side_effects v248
+    v250 = mul v249, v248
+    constrain v250 == v248
+    v251 = not v248
+    v252 = mul v251, v241
+    v253 = unchecked_add v248, v252
+    enable_side_effects u1 1
+    v254 = not v253
+    enable_side_effects v254
+    v256 = array_get v7, index u32 21 -> u8
+    v258 = eq v256, u8 185
+    v259 = not v258
+    v260 = mul v254, v259
+    v261 = lt v256, u8 185
+    enable_side_effects v260
+    v262 = mul v261, v260
+    constrain v262 == v260
+    v263 = not v260
+    v264 = mul v263, v253
+    v265 = unchecked_add v260, v264
+    enable_side_effects u1 1
+    v266 = not v265
+    enable_side_effects v266
+    v268 = array_get v7, index u32 22 -> u8
+    v270 = eq v268, u8 112
+    v271 = not v270
+    v272 = mul v266, v271
+    v273 = lt v268, u8 112
+    enable_side_effects v272
+    v274 = mul v273, v272
+    constrain v274 == v272
+    v275 = not v272
+    v276 = mul v275, v265
+    v277 = unchecked_add v272, v276
+    enable_side_effects u1 1
+    v278 = not v277
+    enable_side_effects v278
+    v280 = array_get v7, index u32 23 -> u8
+    v282 = eq v280, u8 145
+    v283 = not v282
+    v284 = mul v278, v283
+    v285 = lt v280, u8 145
+    enable_side_effects v284
+    v286 = mul v285, v284
+    constrain v286 == v284
+    v287 = not v284
+    v288 = mul v287, v277
+    v289 = unchecked_add v284, v288
+    enable_side_effects u1 1
+    v290 = not v289
+    enable_side_effects v290
+    v292 = array_get v7, index u32 24 -> u8
+    v294 = eq v292, u8 67
+    v295 = not v294
+    v296 = mul v290, v295
+    v297 = lt v292, u8 67
+    enable_side_effects v296
+    v298 = mul v297, v296
+    constrain v298 == v296
+    v299 = not v296
+    v300 = mul v299, v289
+    v301 = unchecked_add v296, v300
+    enable_side_effects u1 1
+    v302 = not v301
+    enable_side_effects v302
+    v304 = array_get v7, index u32 25 -> u8
+    v305 = eq v304, u8 225
+    v306 = not v305
+    v307 = mul v302, v306
+    v308 = lt v304, u8 225
+    enable_side_effects v307
+    v309 = mul v308, v307
+    constrain v309 == v307
+    v310 = not v307
+    v311 = mul v310, v301
+    v312 = unchecked_add v307, v311
+    enable_side_effects u1 1
+    v313 = not v312
+    enable_side_effects v313
+    v315 = array_get v7, index u32 26 -> u8
+    v317 = eq v315, u8 245
+    v318 = not v317
+    v319 = mul v313, v318
+    v320 = lt v315, u8 245
+    enable_side_effects v319
+    v321 = mul v320, v319
+    constrain v321 == v319
+    v322 = not v319
+    v323 = mul v322, v312
+    v324 = unchecked_add v319, v323
+    enable_side_effects u1 1
+    v325 = not v324
+    enable_side_effects v325
+    v327 = array_get v7, index u32 27 -> u8
+    v329 = eq v327, u8 147
+    v330 = not v329
+    v331 = mul v325, v330
+    v332 = lt v327, u8 147
+    enable_side_effects v331
+    v333 = mul v332, v331
+    constrain v333 == v331
+    v334 = not v331
+    v335 = mul v334, v324
+    v336 = unchecked_add v331, v335
+    enable_side_effects u1 1
+    v337 = not v336
+    enable_side_effects v337
+    v339 = array_get v7, index u32 28 -> u8
+    v341 = eq v339, u8 240
+    v342 = not v341
+    v343 = mul v337, v342
+    v344 = lt v339, u8 240
+    enable_side_effects v343
+    v345 = mul v344, v343
+    constrain v345 == v343
+    v346 = not v343
+    v347 = mul v346, v336
+    v348 = unchecked_add v343, v347
+    enable_side_effects u1 1
+    v349 = not v348
+    enable_side_effects v349
+    v351 = array_get v7, index u32 29 -> u8
+    v353 = eq v351, u8 0
+    v354 = not v353
+    v355 = mul v349, v354
+    constrain u1 0 == v355
+    enable_side_effects u1 0
+    v357 = unchecked_add v355, v348
+    enable_side_effects u1 1
+    v358 = not v357
+    enable_side_effects v358
+    v360 = array_get v7, index u32 30 -> u8
+    v361 = eq v360, u8 0
+    v362 = not v361
+    v363 = mul v358, v362
+    constrain u1 0 == v363
+    enable_side_effects u1 0
+    v364 = unchecked_add v363, v357
+    enable_side_effects u1 1
+    v365 = not v364
+    enable_side_effects v365
+    v367 = array_get v7, index u32 31 -> u8
+    v369 = eq v367, u8 1
+    v370 = not v369
+    v371 = mul v365, v370
+    v372 = cast v371 as u8
+    enable_side_effects v371
+    v373 = unchecked_mul v367, v372
+    constrain v373 == u8 0
+    v374 = not v371
+    v375 = mul v374, v364
+    v376 = unchecked_add v371, v375
+    enable_side_effects u1 1
+    constrain v376 == u1 1
+    v377 = cast v184 as Field
+    v378 = cast v367 as Field
+    v379 = cast v172 as Field
+    v381 = mul v379, Field 256
+    v382 = add v377, v381
+    v383 = cast v360 as Field
+    v384 = mul v383, Field 256
+    v385 = add v378, v384
+    v386 = cast v161 as Field
+    v388 = mul v386, Field 65536
+    v389 = add v382, v388
+    v390 = cast v351 as Field
+    v391 = mul v390, Field 65536
+    v392 = add v385, v391
+    v393 = cast v149 as Field
+    v395 = mul v393, Field 16777216
+    v396 = add v389, v395
+    v397 = cast v339 as Field
+    v398 = mul v397, Field 16777216
+    v399 = add v392, v398
+    v400 = cast v137 as Field
+    v402 = mul v400, Field 4294967296
+    v403 = add v396, v402
+    v404 = cast v327 as Field
+    v405 = mul v404, Field 4294967296
+    v406 = add v399, v405
+    v407 = cast v125 as Field
+    v409 = mul v407, Field 1099511627776
+    v410 = add v403, v409
+    v411 = cast v315 as Field
+    v412 = mul v411, Field 1099511627776
+    v413 = add v406, v412
+    v414 = cast v113 as Field
+    v416 = mul v414, Field 281474976710656
+    v417 = add v410, v416
+    v418 = cast v304 as Field
+    v419 = mul v418, Field 281474976710656
+    v420 = add v413, v419
+    v421 = cast v101 as Field
+    v423 = mul v421, Field 72057594037927936
+    v424 = add v417, v423
+    v425 = cast v292 as Field
+    v426 = mul v425, Field 72057594037927936
+    v427 = add v420, v426
+    v428 = cast v89 as Field
+    v430 = mul v428, Field 18446744073709551616
+    v431 = add v424, v430
+    v432 = cast v280 as Field
+    v433 = mul v432, Field 18446744073709551616
+    v434 = add v427, v433
+    v435 = cast v77 as Field
+    v437 = mul v435, Field 4722366482869645213696
+    v438 = add v431, v437
+    v439 = cast v268 as Field
+    v440 = mul v439, Field 4722366482869645213696
+    v441 = add v434, v440
+    v442 = cast v65 as Field
+    v444 = mul v442, Field 1208925819614629174706176
+    v445 = add v438, v444
+    v446 = cast v256 as Field
+    v447 = mul v446, Field 1208925819614629174706176
+    v448 = add v441, v447
+    v449 = cast v53 as Field
+    v451 = mul v449, Field 309485009821345068724781056
+    v452 = add v445, v451
+    v453 = cast v244 as Field
+    v454 = mul v453, Field 309485009821345068724781056
+    v455 = add v448, v454
+    v456 = cast v41 as Field
+    v458 = mul v456, Field 79228162514264337593543950336
+    v459 = add v452, v458
+    v460 = cast v232 as Field
+    v461 = mul v460, Field 79228162514264337593543950336
+    v462 = add v455, v461
+    v463 = cast v29 as Field
+    v465 = mul v463, Field 20282409603651670423947251286016
+    v466 = add v459, v465
+    v467 = cast v220 as Field
+    v468 = mul v467, Field 20282409603651670423947251286016
+    v469 = add v462, v468
+    v470 = cast v16 as Field
+    v472 = mul v470, Field 5192296858534827628530496329220096
+    v473 = add v466, v472
+    v474 = cast v208 as Field
+    v475 = mul v474, Field 5192296858534827628530496329220096
+    v476 = add v469, v475
+    v477 = cast v9 as Field
+    v479 = mul v477, Field 1329227995784915872903807060280344576
+    v480 = add v473, v479
+    v481 = cast v196 as Field
+    v482 = mul v481, Field 1329227995784915872903807060280344576
+    v483 = add v476, v482
+    v485 = mul v480, Field 340282366920938463463374607431768211456
+    v486 = add v483, v485
+    v488 = eq v4, Field 0
+    v489 = not v488
+    enable_side_effects v489
+    v491 = call f1(v4, Field 0) -> u1
+    v492 = mul v489, v491
+    enable_side_effects v492
+    v494, v495 = call f3(Field 0) -> (Field, Field)
+    v496 = cast v492 as Field
+    v497 = mul v494, v496
+    range_check v497 to 128 bits
+    v498 = mul v495, v496
+    range_check v498 to 128 bits
+    v499 = mul Field 340282366920938463463374607431768211456, v495
+    v500 = add v494, v499
+    v501 = mul v500, v496
+    constrain Field 0 == v501
+    v504 = call f2(Field 53438638232309528389504892708671455233, v494) -> u1
+    v505 = sub Field 53438638232309528389504892708671455233, v494
+    v507 = sub v505, Field 1
+    v508 = cast v504 as Field
+    v509 = mul v508, Field 340282366920938463463374607431768211456
+    v510 = add v507, v509
+    v512 = sub Field 64323764613183177041862057485226039389, v495
+    v513 = sub v512, v508
+    v514 = mul v510, v496
+    range_check v514 to 128 bits
+    v515 = mul v513, v496
+    range_check v515 to 128 bits
+    v517, v518 = call f3(v4) -> (Field, Field)
+    v519 = mul v517, v496
+    range_check v519 to 128 bits
+    v520 = mul v518, v496
+    range_check v520 to 128 bits
+    v521 = mul Field 340282366920938463463374607431768211456, v518
+    v522 = add v517, v521
+    v523 = mul v4, v496
+    v524 = mul v522, v496
+    constrain v523 == v524
+    v526 = call f2(Field 53438638232309528389504892708671455233, v517) -> u1
+    v527 = sub Field 53438638232309528389504892708671455233, v517
+    v528 = sub v527, Field 1
+    v529 = cast v526 as Field
+    v530 = mul v529, Field 340282366920938463463374607431768211456
+    v531 = add v528, v530
+    v532 = sub Field 64323764613183177041862057485226039389, v518
+    v533 = sub v532, v529
+    v534 = mul v531, v496
+    range_check v534 to 128 bits
+    v535 = mul v533, v496
+    range_check v535 to 128 bits
+    v537 = call f2(v494, v517) -> u1
+    v538 = sub v494, v517
+    v539 = sub v538, Field 1
+    v540 = cast v537 as Field
+    v541 = mul v540, Field 340282366920938463463374607431768211456
+    v542 = add v539, v541
+    v543 = sub v495, v518
+    v544 = sub v543, v540
+    v545 = mul v542, v496
+    range_check v545 to 128 bits
+    v546 = mul v544, v496
+    range_check v546 to 128 bits
+    v547 = not v491
+    v548 = mul v489, v547
+    enable_side_effects v548
+    v550, v551 = call f3(v4) -> (Field, Field)
+    v552 = cast v548 as Field
+    v553 = mul v550, v552
+    range_check v553 to 128 bits
+    v554 = mul v551, v552
+    range_check v554 to 128 bits
+    v555 = mul Field 340282366920938463463374607431768211456, v551
+    v556 = add v550, v555
+    v557 = mul v4, v552
+    v558 = mul v556, v552
+    constrain v557 == v558
+    v560 = call f2(Field 53438638232309528389504892708671455233, v550) -> u1
+    v561 = sub Field 53438638232309528389504892708671455233, v550
+    v562 = sub v561, Field 1
+    v563 = cast v560 as Field
+    v564 = mul v563, Field 340282366920938463463374607431768211456
+    v565 = add v562, v564
+    v566 = sub Field 64323764613183177041862057485226039389, v551
+    v567 = sub v566, v563
+    v568 = mul v565, v552
+    range_check v568 to 128 bits
+    v569 = mul v567, v552
+    range_check v569 to 128 bits
+    v571, v572 = call f3(Field 0) -> (Field, Field)
+    v573 = mul v571, v552
+    range_check v573 to 128 bits
+    v574 = mul v572, v552
+    range_check v574 to 128 bits
+    v575 = mul Field 340282366920938463463374607431768211456, v572
+    v576 = add v571, v575
+    v577 = mul v576, v552
+    constrain Field 0 == v577
+    v579 = call f2(Field 53438638232309528389504892708671455233, v571) -> u1
+    v580 = sub Field 53438638232309528389504892708671455233, v571
+    v581 = sub v580, Field 1
+    v582 = cast v579 as Field
+    v583 = mul v582, Field 340282366920938463463374607431768211456
+    v584 = add v581, v583
+    v585 = sub Field 64323764613183177041862057485226039389, v572
+    v586 = sub v585, v582
+    v587 = mul v584, v552
+    range_check v587 to 128 bits
+    v588 = mul v586, v552
+    range_check v588 to 128 bits
+    v590 = call f2(v550, v571) -> u1
+    v591 = sub v550, v571
+    v592 = sub v591, Field 1
+    v593 = cast v590 as Field
+    v594 = mul v593, Field 340282366920938463463374607431768211456
+    v595 = add v592, v594
+    v596 = sub v551, v572
+    v597 = sub v596, v593
+    v598 = mul v595, v552
+    range_check v598 to 128 bits
+    v599 = mul v597, v552
+    range_check v599 to 128 bits
+    enable_side_effects u1 1
+    v600 = sub v552, v486
+    return v600
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = truncate v4 to 64 bits, max_bit_size: 254
+    v6 = sub v4, v5
+    v7 = div v6, Field 18446744073709551616
+    v8 = truncate v7 to 64 bits, max_bit_size: 254
+    v9 = sub v7, v8
+    v10 = div v9, Field 18446744073709551616
+    v11 = mul v8, Field 18446744073709551616
+    v12 = add v11, v5
+    return v12, v10
+}
+
+After Inlining Brillig Calls Inlining:
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v7 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v9 = array_get v7, index u32 0 -> u8
+    v11 = eq v9, u8 48
+    v12 = not v11
+    v13 = lt v9, u8 48
+    enable_side_effects v12
+    v14 = mul v13, v12
+    constrain v14 == v12
+    enable_side_effects v11
+    v16 = array_get v7, index u32 1 -> u8
+    v18 = eq v16, u8 100
+    v19 = not v18
+    v20 = mul v11, v19
+    v21 = lt v16, u8 100
+    enable_side_effects v20
+    v22 = mul v21, v20
+    constrain v22 == v20
+    v23 = not v20
+    v24 = mul v23, v12
+    v25 = unchecked_add v20, v24
+    enable_side_effects u1 1
+    v27 = not v25
+    enable_side_effects v27
+    v29 = array_get v7, index u32 2 -> u8
+    v31 = eq v29, u8 78
+    v32 = not v31
+    v33 = mul v27, v32
+    v34 = lt v29, u8 78
+    enable_side_effects v33
+    v35 = mul v34, v33
+    constrain v35 == v33
+    v36 = not v33
+    v37 = mul v36, v25
+    v38 = unchecked_add v33, v37
+    enable_side_effects u1 1
+    v39 = not v38
+    enable_side_effects v39
+    v41 = array_get v7, index u32 3 -> u8
+    v43 = eq v41, u8 114
+    v44 = not v43
+    v45 = mul v39, v44
+    v46 = lt v41, u8 114
+    enable_side_effects v45
+    v47 = mul v46, v45
+    constrain v47 == v45
+    v48 = not v45
+    v49 = mul v48, v38
+    v50 = unchecked_add v45, v49
+    enable_side_effects u1 1
+    v51 = not v50
+    enable_side_effects v51
+    v53 = array_get v7, index u32 4 -> u8
+    v55 = eq v53, u8 225
+    v56 = not v55
+    v57 = mul v51, v56
+    v58 = lt v53, u8 225
+    enable_side_effects v57
+    v59 = mul v58, v57
+    constrain v59 == v57
+    v60 = not v57
+    v61 = mul v60, v50
+    v62 = unchecked_add v57, v61
+    enable_side_effects u1 1
+    v63 = not v62
+    enable_side_effects v63
+    v65 = array_get v7, index u32 5 -> u8
+    v67 = eq v65, u8 49
+    v68 = not v67
+    v69 = mul v63, v68
+    v70 = lt v65, u8 49
+    enable_side_effects v69
+    v71 = mul v70, v69
+    constrain v71 == v69
+    v72 = not v69
+    v73 = mul v72, v62
+    v74 = unchecked_add v69, v73
+    enable_side_effects u1 1
+    v75 = not v74
+    enable_side_effects v75
+    v77 = array_get v7, index u32 6 -> u8
+    v79 = eq v77, u8 160
+    v80 = not v79
+    v81 = mul v75, v80
+    v82 = lt v77, u8 160
+    enable_side_effects v81
+    v83 = mul v82, v81
+    constrain v83 == v81
+    v84 = not v81
+    v85 = mul v84, v74
+    v86 = unchecked_add v81, v85
+    enable_side_effects u1 1
+    v87 = not v86
+    enable_side_effects v87
+    v89 = array_get v7, index u32 7 -> u8
+    v91 = eq v89, u8 41
+    v92 = not v91
+    v93 = mul v87, v92
+    v94 = lt v89, u8 41
+    enable_side_effects v93
+    v95 = mul v94, v93
+    constrain v95 == v93
+    v96 = not v93
+    v97 = mul v96, v86
+    v98 = unchecked_add v93, v97
+    enable_side_effects u1 1
+    v99 = not v98
+    enable_side_effects v99
+    v101 = array_get v7, index u32 8 -> u8
+    v103 = eq v101, u8 184
+    v104 = not v103
+    v105 = mul v99, v104
+    v106 = lt v101, u8 184
+    enable_side_effects v105
+    v107 = mul v106, v105
+    constrain v107 == v105
+    v108 = not v105
+    v109 = mul v108, v98
+    v110 = unchecked_add v105, v109
+    enable_side_effects u1 1
+    v111 = not v110
+    enable_side_effects v111
+    v113 = array_get v7, index u32 9 -> u8
+    v115 = eq v113, u8 80
+    v116 = not v115
+    v117 = mul v111, v116
+    v118 = lt v113, u8 80
+    enable_side_effects v117
+    v119 = mul v118, v117
+    constrain v119 == v117
+    v120 = not v117
+    v121 = mul v120, v110
+    v122 = unchecked_add v117, v121
+    enable_side_effects u1 1
+    v123 = not v122
+    enable_side_effects v123
+    v125 = array_get v7, index u32 10 -> u8
+    v127 = eq v125, u8 69
+    v128 = not v127
+    v129 = mul v123, v128
+    v130 = lt v125, u8 69
+    enable_side_effects v129
+    v131 = mul v130, v129
+    constrain v131 == v129
+    v132 = not v129
+    v133 = mul v132, v122
+    v134 = unchecked_add v129, v133
+    enable_side_effects u1 1
+    v135 = not v134
+    enable_side_effects v135
+    v137 = array_get v7, index u32 11 -> u8
+    v139 = eq v137, u8 182
+    v140 = not v139
+    v141 = mul v135, v140
+    v142 = lt v137, u8 182
+    enable_side_effects v141
+    v143 = mul v142, v141
+    constrain v143 == v141
+    v144 = not v141
+    v145 = mul v144, v134
+    v146 = unchecked_add v141, v145
+    enable_side_effects u1 1
+    v147 = not v146
+    enable_side_effects v147
+    v149 = array_get v7, index u32 12 -> u8
+    v151 = eq v149, u8 129
+    v152 = not v151
+    v153 = mul v147, v152
+    v154 = lt v149, u8 129
+    enable_side_effects v153
+    v155 = mul v154, v153
+    constrain v155 == v153
+    v156 = not v153
+    v157 = mul v156, v146
+    v158 = unchecked_add v153, v157
+    enable_side_effects u1 1
+    v159 = not v158
+    enable_side_effects v159
+    v161 = array_get v7, index u32 13 -> u8
+    v162 = eq v161, u8 129
+    v163 = not v162
+    v164 = mul v159, v163
+    v165 = lt v161, u8 129
+    enable_side_effects v164
+    v166 = mul v165, v164
+    constrain v166 == v164
+    v167 = not v164
+    v168 = mul v167, v158
+    v169 = unchecked_add v164, v168
+    enable_side_effects u1 1
+    v170 = not v169
+    enable_side_effects v170
+    v172 = array_get v7, index u32 14 -> u8
+    v174 = eq v172, u8 88
+    v175 = not v174
+    v176 = mul v170, v175
+    v177 = lt v172, u8 88
+    enable_side_effects v176
+    v178 = mul v177, v176
+    constrain v178 == v176
+    v179 = not v176
+    v180 = mul v179, v169
+    v181 = unchecked_add v176, v180
+    enable_side_effects u1 1
+    v182 = not v181
+    enable_side_effects v182
+    v184 = array_get v7, index u32 15 -> u8
+    v186 = eq v184, u8 93
+    v187 = not v186
+    v188 = mul v182, v187
+    v189 = lt v184, u8 93
+    enable_side_effects v188
+    v190 = mul v189, v188
+    constrain v190 == v188
+    v191 = not v188
+    v192 = mul v191, v181
+    v193 = unchecked_add v188, v192
+    enable_side_effects u1 1
+    v194 = not v193
+    enable_side_effects v194
+    v196 = array_get v7, index u32 16 -> u8
+    v198 = eq v196, u8 40
+    v199 = not v198
+    v200 = mul v194, v199
+    v201 = lt v196, u8 40
+    enable_side_effects v200
+    v202 = mul v201, v200
+    constrain v202 == v200
+    v203 = not v200
+    v204 = mul v203, v193
+    v205 = unchecked_add v200, v204
+    enable_side_effects u1 1
+    v206 = not v205
+    enable_side_effects v206
+    v208 = array_get v7, index u32 17 -> u8
+    v210 = eq v208, u8 51
+    v211 = not v210
+    v212 = mul v206, v211
+    v213 = lt v208, u8 51
+    enable_side_effects v212
+    v214 = mul v213, v212
+    constrain v214 == v212
+    v215 = not v212
+    v216 = mul v215, v205
+    v217 = unchecked_add v212, v216
+    enable_side_effects u1 1
+    v218 = not v217
+    enable_side_effects v218
+    v220 = array_get v7, index u32 18 -> u8
+    v222 = eq v220, u8 232
+    v223 = not v222
+    v224 = mul v218, v223
+    v225 = lt v220, u8 232
+    enable_side_effects v224
+    v226 = mul v225, v224
+    constrain v226 == v224
+    v227 = not v224
+    v228 = mul v227, v217
+    v229 = unchecked_add v224, v228
+    enable_side_effects u1 1
+    v230 = not v229
+    enable_side_effects v230
+    v232 = array_get v7, index u32 19 -> u8
+    v234 = eq v232, u8 72
+    v235 = not v234
+    v236 = mul v230, v235
+    v237 = lt v232, u8 72
+    enable_side_effects v236
+    v238 = mul v237, v236
+    constrain v238 == v236
+    v239 = not v236
+    v240 = mul v239, v229
+    v241 = unchecked_add v236, v240
+    enable_side_effects u1 1
+    v242 = not v241
+    enable_side_effects v242
+    v244 = array_get v7, index u32 20 -> u8
+    v246 = eq v244, u8 121
+    v247 = not v246
+    v248 = mul v242, v247
+    v249 = lt v244, u8 121
+    enable_side_effects v248
+    v250 = mul v249, v248
+    constrain v250 == v248
+    v251 = not v248
+    v252 = mul v251, v241
+    v253 = unchecked_add v248, v252
+    enable_side_effects u1 1
+    v254 = not v253
+    enable_side_effects v254
+    v256 = array_get v7, index u32 21 -> u8
+    v258 = eq v256, u8 185
+    v259 = not v258
+    v260 = mul v254, v259
+    v261 = lt v256, u8 185
+    enable_side_effects v260
+    v262 = mul v261, v260
+    constrain v262 == v260
+    v263 = not v260
+    v264 = mul v263, v253
+    v265 = unchecked_add v260, v264
+    enable_side_effects u1 1
+    v266 = not v265
+    enable_side_effects v266
+    v268 = array_get v7, index u32 22 -> u8
+    v270 = eq v268, u8 112
+    v271 = not v270
+    v272 = mul v266, v271
+    v273 = lt v268, u8 112
+    enable_side_effects v272
+    v274 = mul v273, v272
+    constrain v274 == v272
+    v275 = not v272
+    v276 = mul v275, v265
+    v277 = unchecked_add v272, v276
+    enable_side_effects u1 1
+    v278 = not v277
+    enable_side_effects v278
+    v280 = array_get v7, index u32 23 -> u8
+    v282 = eq v280, u8 145
+    v283 = not v282
+    v284 = mul v278, v283
+    v285 = lt v280, u8 145
+    enable_side_effects v284
+    v286 = mul v285, v284
+    constrain v286 == v284
+    v287 = not v284
+    v288 = mul v287, v277
+    v289 = unchecked_add v284, v288
+    enable_side_effects u1 1
+    v290 = not v289
+    enable_side_effects v290
+    v292 = array_get v7, index u32 24 -> u8
+    v294 = eq v292, u8 67
+    v295 = not v294
+    v296 = mul v290, v295
+    v297 = lt v292, u8 67
+    enable_side_effects v296
+    v298 = mul v297, v296
+    constrain v298 == v296
+    v299 = not v296
+    v300 = mul v299, v289
+    v301 = unchecked_add v296, v300
+    enable_side_effects u1 1
+    v302 = not v301
+    enable_side_effects v302
+    v304 = array_get v7, index u32 25 -> u8
+    v305 = eq v304, u8 225
+    v306 = not v305
+    v307 = mul v302, v306
+    v308 = lt v304, u8 225
+    enable_side_effects v307
+    v309 = mul v308, v307
+    constrain v309 == v307
+    v310 = not v307
+    v311 = mul v310, v301
+    v312 = unchecked_add v307, v311
+    enable_side_effects u1 1
+    v313 = not v312
+    enable_side_effects v313
+    v315 = array_get v7, index u32 26 -> u8
+    v317 = eq v315, u8 245
+    v318 = not v317
+    v319 = mul v313, v318
+    v320 = lt v315, u8 245
+    enable_side_effects v319
+    v321 = mul v320, v319
+    constrain v321 == v319
+    v322 = not v319
+    v323 = mul v322, v312
+    v324 = unchecked_add v319, v323
+    enable_side_effects u1 1
+    v325 = not v324
+    enable_side_effects v325
+    v327 = array_get v7, index u32 27 -> u8
+    v329 = eq v327, u8 147
+    v330 = not v329
+    v331 = mul v325, v330
+    v332 = lt v327, u8 147
+    enable_side_effects v331
+    v333 = mul v332, v331
+    constrain v333 == v331
+    v334 = not v331
+    v335 = mul v334, v324
+    v336 = unchecked_add v331, v335
+    enable_side_effects u1 1
+    v337 = not v336
+    enable_side_effects v337
+    v339 = array_get v7, index u32 28 -> u8
+    v341 = eq v339, u8 240
+    v342 = not v341
+    v343 = mul v337, v342
+    v344 = lt v339, u8 240
+    enable_side_effects v343
+    v345 = mul v344, v343
+    constrain v345 == v343
+    v346 = not v343
+    v347 = mul v346, v336
+    v348 = unchecked_add v343, v347
+    enable_side_effects u1 1
+    v349 = not v348
+    enable_side_effects v349
+    v351 = array_get v7, index u32 29 -> u8
+    v353 = eq v351, u8 0
+    v354 = not v353
+    v355 = mul v349, v354
+    constrain u1 0 == v355
+    enable_side_effects u1 0
+    v357 = unchecked_add v355, v348
+    enable_side_effects u1 1
+    v358 = not v357
+    enable_side_effects v358
+    v360 = array_get v7, index u32 30 -> u8
+    v361 = eq v360, u8 0
+    v362 = not v361
+    v363 = mul v358, v362
+    constrain u1 0 == v363
+    enable_side_effects u1 0
+    v364 = unchecked_add v363, v357
+    enable_side_effects u1 1
+    v365 = not v364
+    enable_side_effects v365
+    v367 = array_get v7, index u32 31 -> u8
+    v369 = eq v367, u8 1
+    v370 = not v369
+    v371 = mul v365, v370
+    v372 = cast v371 as u8
+    enable_side_effects v371
+    v373 = unchecked_mul v367, v372
+    constrain v373 == u8 0
+    v374 = not v371
+    v375 = mul v374, v364
+    v376 = unchecked_add v371, v375
+    enable_side_effects u1 1
+    constrain v376 == u1 1
+    v377 = cast v184 as Field
+    v378 = cast v367 as Field
+    v379 = cast v172 as Field
+    v381 = mul v379, Field 256
+    v382 = add v377, v381
+    v383 = cast v360 as Field
+    v384 = mul v383, Field 256
+    v385 = add v378, v384
+    v386 = cast v161 as Field
+    v388 = mul v386, Field 65536
+    v389 = add v382, v388
+    v390 = cast v351 as Field
+    v391 = mul v390, Field 65536
+    v392 = add v385, v391
+    v393 = cast v149 as Field
+    v395 = mul v393, Field 16777216
+    v396 = add v389, v395
+    v397 = cast v339 as Field
+    v398 = mul v397, Field 16777216
+    v399 = add v392, v398
+    v400 = cast v137 as Field
+    v402 = mul v400, Field 4294967296
+    v403 = add v396, v402
+    v404 = cast v327 as Field
+    v405 = mul v404, Field 4294967296
+    v406 = add v399, v405
+    v407 = cast v125 as Field
+    v409 = mul v407, Field 1099511627776
+    v410 = add v403, v409
+    v411 = cast v315 as Field
+    v412 = mul v411, Field 1099511627776
+    v413 = add v406, v412
+    v414 = cast v113 as Field
+    v416 = mul v414, Field 281474976710656
+    v417 = add v410, v416
+    v418 = cast v304 as Field
+    v419 = mul v418, Field 281474976710656
+    v420 = add v413, v419
+    v421 = cast v101 as Field
+    v423 = mul v421, Field 72057594037927936
+    v424 = add v417, v423
+    v425 = cast v292 as Field
+    v426 = mul v425, Field 72057594037927936
+    v427 = add v420, v426
+    v428 = cast v89 as Field
+    v430 = mul v428, Field 18446744073709551616
+    v431 = add v424, v430
+    v432 = cast v280 as Field
+    v433 = mul v432, Field 18446744073709551616
+    v434 = add v427, v433
+    v435 = cast v77 as Field
+    v437 = mul v435, Field 4722366482869645213696
+    v438 = add v431, v437
+    v439 = cast v268 as Field
+    v440 = mul v439, Field 4722366482869645213696
+    v441 = add v434, v440
+    v442 = cast v65 as Field
+    v444 = mul v442, Field 1208925819614629174706176
+    v445 = add v438, v444
+    v446 = cast v256 as Field
+    v447 = mul v446, Field 1208925819614629174706176
+    v448 = add v441, v447
+    v449 = cast v53 as Field
+    v451 = mul v449, Field 309485009821345068724781056
+    v452 = add v445, v451
+    v453 = cast v244 as Field
+    v454 = mul v453, Field 309485009821345068724781056
+    v455 = add v448, v454
+    v456 = cast v41 as Field
+    v458 = mul v456, Field 79228162514264337593543950336
+    v459 = add v452, v458
+    v460 = cast v232 as Field
+    v461 = mul v460, Field 79228162514264337593543950336
+    v462 = add v455, v461
+    v463 = cast v29 as Field
+    v465 = mul v463, Field 20282409603651670423947251286016
+    v466 = add v459, v465
+    v467 = cast v220 as Field
+    v468 = mul v467, Field 20282409603651670423947251286016
+    v469 = add v462, v468
+    v470 = cast v16 as Field
+    v472 = mul v470, Field 5192296858534827628530496329220096
+    v473 = add v466, v472
+    v474 = cast v208 as Field
+    v475 = mul v474, Field 5192296858534827628530496329220096
+    v476 = add v469, v475
+    v477 = cast v9 as Field
+    v479 = mul v477, Field 1329227995784915872903807060280344576
+    v480 = add v473, v479
+    v481 = cast v196 as Field
+    v482 = mul v481, Field 1329227995784915872903807060280344576
+    v483 = add v476, v482
+    v485 = mul v480, Field 340282366920938463463374607431768211456
+    v486 = add v483, v485
+    v488 = eq v4, Field 0
+    v489 = not v488
+    enable_side_effects v489
+    v491 = call f1(v4, Field 0) -> u1
+    v492 = mul v489, v491
+    enable_side_effects v492
+    v493 = cast v492 as Field
+    v495 = mul Field 53438638232309528389504892708671455232, v493
+    range_check v495 to 128 bits
+    v497 = mul Field 64323764613183177041862057485226039389, v493
+    range_check v497 to 128 bits
+    v499, v500 = call f3(v4) -> (Field, Field)
+    v501 = mul v499, v493
+    range_check v501 to 128 bits
+    v502 = mul v500, v493
+    range_check v502 to 128 bits
+    v503 = mul Field 340282366920938463463374607431768211456, v500
+    v504 = add v499, v503
+    v505 = mul v4, v493
+    v506 = mul v504, v493
+    constrain v505 == v506
+    v509 = call f2(Field 53438638232309528389504892708671455233, v499) -> u1
+    v510 = sub Field 53438638232309528389504892708671455233, v499
+    v512 = sub v510, Field 1
+    v513 = cast v509 as Field
+    v514 = mul v513, Field 340282366920938463463374607431768211456
+    v515 = add v512, v514
+    v516 = sub Field 64323764613183177041862057485226039389, v500
+    v517 = sub v516, v513
+    v518 = mul v515, v493
+    range_check v518 to 128 bits
+    v519 = mul v517, v493
+    range_check v519 to 128 bits
+    v521 = call f2(Field 0, v499) -> u1
+    v522 = sub Field 0, v499
+    v523 = sub v522, Field 1
+    v524 = cast v521 as Field
+    v525 = mul v524, Field 340282366920938463463374607431768211456
+    v526 = add v523, v525
+    v527 = sub Field 0, v500
+    v528 = sub v527, v524
+    v529 = mul v526, v493
+    range_check v529 to 128 bits
+    v530 = mul v528, v493
+    range_check v530 to 128 bits
+    v531 = not v491
+    v532 = mul v489, v531
+    enable_side_effects v532
+    v534, v535 = call f3(v4) -> (Field, Field)
+    v536 = cast v532 as Field
+    v537 = mul v534, v536
+    range_check v537 to 128 bits
+    v538 = mul v535, v536
+    range_check v538 to 128 bits
+    v539 = mul Field 340282366920938463463374607431768211456, v535
+    v540 = add v534, v539
+    v541 = mul v4, v536
+    v542 = mul v540, v536
+    constrain v541 == v542
+    v544 = call f2(Field 53438638232309528389504892708671455233, v534) -> u1
+    v545 = sub Field 53438638232309528389504892708671455233, v534
+    v546 = sub v545, Field 1
+    v547 = cast v544 as Field
+    v548 = mul v547, Field 340282366920938463463374607431768211456
+    v549 = add v546, v548
+    v550 = sub Field 64323764613183177041862057485226039389, v535
+    v551 = sub v550, v547
+    v552 = mul v549, v536
+    range_check v552 to 128 bits
+    v553 = mul v551, v536
+    range_check v553 to 128 bits
+    v554 = mul Field 53438638232309528389504892708671455232, v536
+    range_check v554 to 128 bits
+    v555 = mul Field 64323764613183177041862057485226039389, v536
+    range_check v555 to 128 bits
+    v557 = call f2(v534, Field 0) -> u1
+    v558 = sub v534, Field 1
+    v559 = cast v557 as Field
+    v560 = mul v559, Field 340282366920938463463374607431768211456
+    v561 = add v558, v560
+    v562 = sub v535, v559
+    v563 = mul v561, v536
+    range_check v563 to 128 bits
+    v564 = mul v562, v536
+    range_check v564 to 128 bits
+    enable_side_effects u1 1
+    v565 = sub v536, v486
+    return v565
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = truncate v4 to 64 bits, max_bit_size: 254
+    v6 = sub v4, v5
+    v7 = div v6, Field 18446744073709551616
+    v8 = truncate v7 to 64 bits, max_bit_size: 254
+    v9 = sub v7, v8
+    v10 = div v9, Field 18446744073709551616
+    v11 = mul v8, Field 18446744073709551616
+    v12 = add v11, v5
+    return v12, v10
+}
+
+After Dead Instruction Elimination (2nd):
+g0 = Field 340282366920938463463374607431768211456
+g1 = Field 53438638232309528389504892708671455233
+g2 = Field 64323764613183177041862057485226039389
+g3 = Field 18446744073709551616
+
+acir(inline) fn main f0 {
+  b0(v4: Field):
+    v7 = call to_be_radix(v4, u32 256) -> [u8; 32]
+    v9 = array_get v7, index u32 0 -> u8
+    v11 = eq v9, u8 48
+    v12 = not v11
+    v13 = lt v9, u8 48
+    enable_side_effects v12
+    v14 = mul v13, v12
+    constrain v14 == v12
+    enable_side_effects v11
+    v16 = array_get v7, index u32 1 -> u8
+    v18 = eq v16, u8 100
+    v19 = not v18
+    v20 = mul v11, v19
+    v21 = lt v16, u8 100
+    enable_side_effects v20
+    v22 = mul v21, v20
+    constrain v22 == v20
+    v23 = not v20
+    v24 = mul v23, v12
+    v25 = unchecked_add v20, v24
+    enable_side_effects u1 1
+    v27 = not v25
+    enable_side_effects v27
+    v29 = array_get v7, index u32 2 -> u8
+    v31 = eq v29, u8 78
+    v32 = not v31
+    v33 = mul v27, v32
+    v34 = lt v29, u8 78
+    enable_side_effects v33
+    v35 = mul v34, v33
+    constrain v35 == v33
+    v36 = not v33
+    v37 = mul v36, v25
+    v38 = unchecked_add v33, v37
+    enable_side_effects u1 1
+    v39 = not v38
+    enable_side_effects v39
+    v41 = array_get v7, index u32 3 -> u8
+    v43 = eq v41, u8 114
+    v44 = not v43
+    v45 = mul v39, v44
+    v46 = lt v41, u8 114
+    enable_side_effects v45
+    v47 = mul v46, v45
+    constrain v47 == v45
+    v48 = not v45
+    v49 = mul v48, v38
+    v50 = unchecked_add v45, v49
+    enable_side_effects u1 1
+    v51 = not v50
+    enable_side_effects v51
+    v53 = array_get v7, index u32 4 -> u8
+    v55 = eq v53, u8 225
+    v56 = not v55
+    v57 = mul v51, v56
+    v58 = lt v53, u8 225
+    enable_side_effects v57
+    v59 = mul v58, v57
+    constrain v59 == v57
+    v60 = not v57
+    v61 = mul v60, v50
+    v62 = unchecked_add v57, v61
+    enable_side_effects u1 1
+    v63 = not v62
+    enable_side_effects v63
+    v65 = array_get v7, index u32 5 -> u8
+    v67 = eq v65, u8 49
+    v68 = not v67
+    v69 = mul v63, v68
+    v70 = lt v65, u8 49
+    enable_side_effects v69
+    v71 = mul v70, v69
+    constrain v71 == v69
+    v72 = not v69
+    v73 = mul v72, v62
+    v74 = unchecked_add v69, v73
+    enable_side_effects u1 1
+    v75 = not v74
+    enable_side_effects v75
+    v77 = array_get v7, index u32 6 -> u8
+    v79 = eq v77, u8 160
+    v80 = not v79
+    v81 = mul v75, v80
+    v82 = lt v77, u8 160
+    enable_side_effects v81
+    v83 = mul v82, v81
+    constrain v83 == v81
+    v84 = not v81
+    v85 = mul v84, v74
+    v86 = unchecked_add v81, v85
+    enable_side_effects u1 1
+    v87 = not v86
+    enable_side_effects v87
+    v89 = array_get v7, index u32 7 -> u8
+    v91 = eq v89, u8 41
+    v92 = not v91
+    v93 = mul v87, v92
+    v94 = lt v89, u8 41
+    enable_side_effects v93
+    v95 = mul v94, v93
+    constrain v95 == v93
+    v96 = not v93
+    v97 = mul v96, v86
+    v98 = unchecked_add v93, v97
+    enable_side_effects u1 1
+    v99 = not v98
+    enable_side_effects v99
+    v101 = array_get v7, index u32 8 -> u8
+    v103 = eq v101, u8 184
+    v104 = not v103
+    v105 = mul v99, v104
+    v106 = lt v101, u8 184
+    enable_side_effects v105
+    v107 = mul v106, v105
+    constrain v107 == v105
+    v108 = not v105
+    v109 = mul v108, v98
+    v110 = unchecked_add v105, v109
+    enable_side_effects u1 1
+    v111 = not v110
+    enable_side_effects v111
+    v113 = array_get v7, index u32 9 -> u8
+    v115 = eq v113, u8 80
+    v116 = not v115
+    v117 = mul v111, v116
+    v118 = lt v113, u8 80
+    enable_side_effects v117
+    v119 = mul v118, v117
+    constrain v119 == v117
+    v120 = not v117
+    v121 = mul v120, v110
+    v122 = unchecked_add v117, v121
+    enable_side_effects u1 1
+    v123 = not v122
+    enable_side_effects v123
+    v125 = array_get v7, index u32 10 -> u8
+    v127 = eq v125, u8 69
+    v128 = not v127
+    v129 = mul v123, v128
+    v130 = lt v125, u8 69
+    enable_side_effects v129
+    v131 = mul v130, v129
+    constrain v131 == v129
+    v132 = not v129
+    v133 = mul v132, v122
+    v134 = unchecked_add v129, v133
+    enable_side_effects u1 1
+    v135 = not v134
+    enable_side_effects v135
+    v137 = array_get v7, index u32 11 -> u8
+    v139 = eq v137, u8 182
+    v140 = not v139
+    v141 = mul v135, v140
+    v142 = lt v137, u8 182
+    enable_side_effects v141
+    v143 = mul v142, v141
+    constrain v143 == v141
+    v144 = not v141
+    v145 = mul v144, v134
+    v146 = unchecked_add v141, v145
+    enable_side_effects u1 1
+    v147 = not v146
+    enable_side_effects v147
+    v149 = array_get v7, index u32 12 -> u8
+    v151 = eq v149, u8 129
+    v152 = not v151
+    v153 = mul v147, v152
+    v154 = lt v149, u8 129
+    enable_side_effects v153
+    v155 = mul v154, v153
+    constrain v155 == v153
+    v156 = not v153
+    v157 = mul v156, v146
+    v158 = unchecked_add v153, v157
+    enable_side_effects u1 1
+    v159 = not v158
+    enable_side_effects v159
+    v161 = array_get v7, index u32 13 -> u8
+    v162 = eq v161, u8 129
+    v163 = not v162
+    v164 = mul v159, v163
+    v165 = lt v161, u8 129
+    enable_side_effects v164
+    v166 = mul v165, v164
+    constrain v166 == v164
+    v167 = not v164
+    v168 = mul v167, v158
+    v169 = unchecked_add v164, v168
+    enable_side_effects u1 1
+    v170 = not v169
+    enable_side_effects v170
+    v172 = array_get v7, index u32 14 -> u8
+    v174 = eq v172, u8 88
+    v175 = not v174
+    v176 = mul v170, v175
+    v177 = lt v172, u8 88
+    enable_side_effects v176
+    v178 = mul v177, v176
+    constrain v178 == v176
+    v179 = not v176
+    v180 = mul v179, v169
+    v181 = unchecked_add v176, v180
+    enable_side_effects u1 1
+    v182 = not v181
+    enable_side_effects v182
+    v184 = array_get v7, index u32 15 -> u8
+    v186 = eq v184, u8 93
+    v187 = not v186
+    v188 = mul v182, v187
+    v189 = lt v184, u8 93
+    enable_side_effects v188
+    v190 = mul v189, v188
+    constrain v190 == v188
+    v191 = not v188
+    v192 = mul v191, v181
+    v193 = unchecked_add v188, v192
+    enable_side_effects u1 1
+    v194 = not v193
+    enable_side_effects v194
+    v196 = array_get v7, index u32 16 -> u8
+    v198 = eq v196, u8 40
+    v199 = not v198
+    v200 = mul v194, v199
+    v201 = lt v196, u8 40
+    enable_side_effects v200
+    v202 = mul v201, v200
+    constrain v202 == v200
+    v203 = not v200
+    v204 = mul v203, v193
+    v205 = unchecked_add v200, v204
+    enable_side_effects u1 1
+    v206 = not v205
+    enable_side_effects v206
+    v208 = array_get v7, index u32 17 -> u8
+    v210 = eq v208, u8 51
+    v211 = not v210
+    v212 = mul v206, v211
+    v213 = lt v208, u8 51
+    enable_side_effects v212
+    v214 = mul v213, v212
+    constrain v214 == v212
+    v215 = not v212
+    v216 = mul v215, v205
+    v217 = unchecked_add v212, v216
+    enable_side_effects u1 1
+    v218 = not v217
+    enable_side_effects v218
+    v220 = array_get v7, index u32 18 -> u8
+    v222 = eq v220, u8 232
+    v223 = not v222
+    v224 = mul v218, v223
+    v225 = lt v220, u8 232
+    enable_side_effects v224
+    v226 = mul v225, v224
+    constrain v226 == v224
+    v227 = not v224
+    v228 = mul v227, v217
+    v229 = unchecked_add v224, v228
+    enable_side_effects u1 1
+    v230 = not v229
+    enable_side_effects v230
+    v232 = array_get v7, index u32 19 -> u8
+    v234 = eq v232, u8 72
+    v235 = not v234
+    v236 = mul v230, v235
+    v237 = lt v232, u8 72
+    enable_side_effects v236
+    v238 = mul v237, v236
+    constrain v238 == v236
+    v239 = not v236
+    v240 = mul v239, v229
+    v241 = unchecked_add v236, v240
+    enable_side_effects u1 1
+    v242 = not v241
+    enable_side_effects v242
+    v244 = array_get v7, index u32 20 -> u8
+    v246 = eq v244, u8 121
+    v247 = not v246
+    v248 = mul v242, v247
+    v249 = lt v244, u8 121
+    enable_side_effects v248
+    v250 = mul v249, v248
+    constrain v250 == v248
+    v251 = not v248
+    v252 = mul v251, v241
+    v253 = unchecked_add v248, v252
+    enable_side_effects u1 1
+    v254 = not v253
+    enable_side_effects v254
+    v256 = array_get v7, index u32 21 -> u8
+    v258 = eq v256, u8 185
+    v259 = not v258
+    v260 = mul v254, v259
+    v261 = lt v256, u8 185
+    enable_side_effects v260
+    v262 = mul v261, v260
+    constrain v262 == v260
+    v263 = not v260
+    v264 = mul v263, v253
+    v265 = unchecked_add v260, v264
+    enable_side_effects u1 1
+    v266 = not v265
+    enable_side_effects v266
+    v268 = array_get v7, index u32 22 -> u8
+    v270 = eq v268, u8 112
+    v271 = not v270
+    v272 = mul v266, v271
+    v273 = lt v268, u8 112
+    enable_side_effects v272
+    v274 = mul v273, v272
+    constrain v274 == v272
+    v275 = not v272
+    v276 = mul v275, v265
+    v277 = unchecked_add v272, v276
+    enable_side_effects u1 1
+    v278 = not v277
+    enable_side_effects v278
+    v280 = array_get v7, index u32 23 -> u8
+    v282 = eq v280, u8 145
+    v283 = not v282
+    v284 = mul v278, v283
+    v285 = lt v280, u8 145
+    enable_side_effects v284
+    v286 = mul v285, v284
+    constrain v286 == v284
+    v287 = not v284
+    v288 = mul v287, v277
+    v289 = unchecked_add v284, v288
+    enable_side_effects u1 1
+    v290 = not v289
+    enable_side_effects v290
+    v292 = array_get v7, index u32 24 -> u8
+    v294 = eq v292, u8 67
+    v295 = not v294
+    v296 = mul v290, v295
+    v297 = lt v292, u8 67
+    enable_side_effects v296
+    v298 = mul v297, v296
+    constrain v298 == v296
+    v299 = not v296
+    v300 = mul v299, v289
+    v301 = unchecked_add v296, v300
+    enable_side_effects u1 1
+    v302 = not v301
+    enable_side_effects v302
+    v304 = array_get v7, index u32 25 -> u8
+    v305 = eq v304, u8 225
+    v306 = not v305
+    v307 = mul v302, v306
+    v308 = lt v304, u8 225
+    enable_side_effects v307
+    v309 = mul v308, v307
+    constrain v309 == v307
+    v310 = not v307
+    v311 = mul v310, v301
+    v312 = unchecked_add v307, v311
+    enable_side_effects u1 1
+    v313 = not v312
+    enable_side_effects v313
+    v315 = array_get v7, index u32 26 -> u8
+    v317 = eq v315, u8 245
+    v318 = not v317
+    v319 = mul v313, v318
+    v320 = lt v315, u8 245
+    enable_side_effects v319
+    v321 = mul v320, v319
+    constrain v321 == v319
+    v322 = not v319
+    v323 = mul v322, v312
+    v324 = unchecked_add v319, v323
+    enable_side_effects u1 1
+    v325 = not v324
+    enable_side_effects v325
+    v327 = array_get v7, index u32 27 -> u8
+    v329 = eq v327, u8 147
+    v330 = not v329
+    v331 = mul v325, v330
+    v332 = lt v327, u8 147
+    enable_side_effects v331
+    v333 = mul v332, v331
+    constrain v333 == v331
+    v334 = not v331
+    v335 = mul v334, v324
+    v336 = unchecked_add v331, v335
+    enable_side_effects u1 1
+    v337 = not v336
+    enable_side_effects v337
+    v339 = array_get v7, index u32 28 -> u8
+    v341 = eq v339, u8 240
+    v342 = not v341
+    v343 = mul v337, v342
+    v344 = lt v339, u8 240
+    enable_side_effects v343
+    v345 = mul v344, v343
+    constrain v345 == v343
+    v346 = not v343
+    v347 = mul v346, v336
+    v348 = unchecked_add v343, v347
+    enable_side_effects u1 1
+    v349 = not v348
+    enable_side_effects v349
+    v351 = array_get v7, index u32 29 -> u8
+    v353 = eq v351, u8 0
+    v354 = not v353
+    v355 = mul v349, v354
+    constrain u1 0 == v355
+    enable_side_effects u1 0
+    v357 = unchecked_add v355, v348
+    enable_side_effects u1 1
+    v358 = not v357
+    enable_side_effects v358
+    v360 = array_get v7, index u32 30 -> u8
+    v361 = eq v360, u8 0
+    v362 = not v361
+    v363 = mul v358, v362
+    constrain u1 0 == v363
+    enable_side_effects u1 0
+    v364 = unchecked_add v363, v357
+    enable_side_effects u1 1
+    v365 = not v364
+    enable_side_effects v365
+    v367 = array_get v7, index u32 31 -> u8
+    v369 = eq v367, u8 1
+    v370 = not v369
+    v371 = mul v365, v370
+    v372 = cast v371 as u8
+    enable_side_effects v371
+    v373 = unchecked_mul v367, v372
+    constrain v373 == u8 0
+    v374 = not v371
+    v375 = mul v374, v364
+    v376 = unchecked_add v371, v375
+    enable_side_effects u1 1
+    constrain v376 == u1 1
+    v377 = cast v184 as Field
+    v378 = cast v367 as Field
+    v379 = cast v172 as Field
+    v381 = mul v379, Field 256
+    v382 = add v377, v381
+    v383 = cast v360 as Field
+    v384 = mul v383, Field 256
+    v385 = add v378, v384
+    v386 = cast v161 as Field
+    v388 = mul v386, Field 65536
+    v389 = add v382, v388
+    v390 = cast v351 as Field
+    v391 = mul v390, Field 65536
+    v392 = add v385, v391
+    v393 = cast v149 as Field
+    v395 = mul v393, Field 16777216
+    v396 = add v389, v395
+    v397 = cast v339 as Field
+    v398 = mul v397, Field 16777216
+    v399 = add v392, v398
+    v400 = cast v137 as Field
+    v402 = mul v400, Field 4294967296
+    v403 = add v396, v402
+    v404 = cast v327 as Field
+    v405 = mul v404, Field 4294967296
+    v406 = add v399, v405
+    v407 = cast v125 as Field
+    v409 = mul v407, Field 1099511627776
+    v410 = add v403, v409
+    v411 = cast v315 as Field
+    v412 = mul v411, Field 1099511627776
+    v413 = add v406, v412
+    v414 = cast v113 as Field
+    v416 = mul v414, Field 281474976710656
+    v417 = add v410, v416
+    v418 = cast v304 as Field
+    v419 = mul v418, Field 281474976710656
+    v420 = add v413, v419
+    v421 = cast v101 as Field
+    v423 = mul v421, Field 72057594037927936
+    v424 = add v417, v423
+    v425 = cast v292 as Field
+    v426 = mul v425, Field 72057594037927936
+    v427 = add v420, v426
+    v428 = cast v89 as Field
+    v430 = mul v428, Field 18446744073709551616
+    v431 = add v424, v430
+    v432 = cast v280 as Field
+    v433 = mul v432, Field 18446744073709551616
+    v434 = add v427, v433
+    v435 = cast v77 as Field
+    v437 = mul v435, Field 4722366482869645213696
+    v438 = add v431, v437
+    v439 = cast v268 as Field
+    v440 = mul v439, Field 4722366482869645213696
+    v441 = add v434, v440
+    v442 = cast v65 as Field
+    v444 = mul v442, Field 1208925819614629174706176
+    v445 = add v438, v444
+    v446 = cast v256 as Field
+    v447 = mul v446, Field 1208925819614629174706176
+    v448 = add v441, v447
+    v449 = cast v53 as Field
+    v451 = mul v449, Field 309485009821345068724781056
+    v452 = add v445, v451
+    v453 = cast v244 as Field
+    v454 = mul v453, Field 309485009821345068724781056
+    v455 = add v448, v454
+    v456 = cast v41 as Field
+    v458 = mul v456, Field 79228162514264337593543950336
+    v459 = add v452, v458
+    v460 = cast v232 as Field
+    v461 = mul v460, Field 79228162514264337593543950336
+    v462 = add v455, v461
+    v463 = cast v29 as Field
+    v465 = mul v463, Field 20282409603651670423947251286016
+    v466 = add v459, v465
+    v467 = cast v220 as Field
+    v468 = mul v467, Field 20282409603651670423947251286016
+    v469 = add v462, v468
+    v470 = cast v16 as Field
+    v472 = mul v470, Field 5192296858534827628530496329220096
+    v473 = add v466, v472
+    v474 = cast v208 as Field
+    v475 = mul v474, Field 5192296858534827628530496329220096
+    v476 = add v469, v475
+    v477 = cast v9 as Field
+    v479 = mul v477, Field 1329227995784915872903807060280344576
+    v480 = add v473, v479
+    v481 = cast v196 as Field
+    v482 = mul v481, Field 1329227995784915872903807060280344576
+    v483 = add v476, v482
+    v485 = mul v480, Field 340282366920938463463374607431768211456
+    v486 = add v483, v485
+    v488 = eq v4, Field 0
+    v489 = not v488
+    enable_side_effects v489
+    v491 = call f1(v4, Field 0) -> u1
+    v492 = mul v489, v491
+    enable_side_effects v492
+    v493 = cast v492 as Field
+    v495 = mul Field 53438638232309528389504892708671455232, v493
+    range_check v495 to 128 bits
+    v497 = mul Field 64323764613183177041862057485226039389, v493
+    range_check v497 to 128 bits
+    v499, v500 = call f3(v4) -> (Field, Field)
+    v501 = mul v499, v493
+    range_check v501 to 128 bits
+    v502 = mul v500, v493
+    range_check v502 to 128 bits
+    v503 = mul Field 340282366920938463463374607431768211456, v500
+    v504 = add v499, v503
+    v505 = mul v4, v493
+    v506 = mul v504, v493
+    constrain v505 == v506
+    v509 = call f2(Field 53438638232309528389504892708671455233, v499) -> u1
+    v510 = sub Field 53438638232309528389504892708671455233, v499
+    v512 = sub v510, Field 1
+    v513 = cast v509 as Field
+    v514 = mul v513, Field 340282366920938463463374607431768211456
+    v515 = add v512, v514
+    v516 = sub Field 64323764613183177041862057485226039389, v500
+    v517 = sub v516, v513
+    v518 = mul v515, v493
+    range_check v518 to 128 bits
+    v519 = mul v517, v493
+    range_check v519 to 128 bits
+    v521 = call f2(Field 0, v499) -> u1
+    v522 = sub Field 0, v499
+    v523 = sub v522, Field 1
+    v524 = cast v521 as Field
+    v525 = mul v524, Field 340282366920938463463374607431768211456
+    v526 = add v523, v525
+    v527 = sub Field 0, v500
+    v528 = sub v527, v524
+    v529 = mul v526, v493
+    range_check v529 to 128 bits
+    v530 = mul v528, v493
+    range_check v530 to 128 bits
+    v531 = not v491
+    v532 = mul v489, v531
+    enable_side_effects v532
+    v534, v535 = call f3(v4) -> (Field, Field)
+    v536 = cast v532 as Field
+    v537 = mul v534, v536
+    range_check v537 to 128 bits
+    v538 = mul v535, v536
+    range_check v538 to 128 bits
+    v539 = mul Field 340282366920938463463374607431768211456, v535
+    v540 = add v534, v539
+    v541 = mul v4, v536
+    v542 = mul v540, v536
+    constrain v541 == v542
+    v544 = call f2(Field 53438638232309528389504892708671455233, v534) -> u1
+    v545 = sub Field 53438638232309528389504892708671455233, v534
+    v546 = sub v545, Field 1
+    v547 = cast v544 as Field
+    v548 = mul v547, Field 340282366920938463463374607431768211456
+    v549 = add v546, v548
+    v550 = sub Field 64323764613183177041862057485226039389, v535
+    v551 = sub v550, v547
+    v552 = mul v549, v536
+    range_check v552 to 128 bits
+    v553 = mul v551, v536
+    range_check v553 to 128 bits
+    v554 = mul Field 53438638232309528389504892708671455232, v536
+    range_check v554 to 128 bits
+    v555 = mul Field 64323764613183177041862057485226039389, v536
+    range_check v555 to 128 bits
+    v557 = call f2(v534, Field 0) -> u1
+    v558 = sub v534, Field 1
+    v559 = cast v557 as Field
+    v560 = mul v559, Field 340282366920938463463374607431768211456
+    v561 = add v558, v560
+    v562 = sub v535, v559
+    v563 = mul v561, v536
+    range_check v563 to 128 bits
+    v564 = mul v562, v536
+    range_check v564 to 128 bits
+    enable_side_effects u1 1
+    v565 = sub v536, v486
+    return v565
+}
+brillig(inline) fn field_less_than f1 {
+  b0(v4: Field, v5: Field):
+    v7 = call field_less_than(v4, v5) -> u1
+    return v7
+}
+brillig(inline) fn lte_hint f2 {
+  b0(v4: Field, v5: Field):
+    v7 = eq v4, v5
+    jmpif v7 then: b2, else: b1
+  b1():
+    v9 = call f1(v4, v5) -> u1
+    jmp b3(v9)
+  b2():
+    jmp b3(u1 1)
+  b3(v6: u1):
+    return v6
+}
+brillig(inline) fn decompose_hint f3 {
+  b0(v4: Field):
+    v5 = truncate v4 to 64 bits, max_bit_size: 254
+    v6 = sub v4, v5
+    v7 = div v6, Field 18446744073709551616
+    v8 = truncate v7 to 64 bits, max_bit_size: 254
+    v9 = sub v7, v8
+    v10 = div v9, Field 18446744073709551616
+    v11 = mul v8, Field 18446744073709551616
+    v12 = add v11, v5
+    return v12, v10
+}
+
+[regression_7128] Circuit witness successfully solved
+[regression_7128] Circuit output: Field(0)
+[regression_7128] Witness saved to /mnt/user-data/maxim/noir/test_programs/execution_success/regression_7128/target/regression_7128.gz

From eda949b54e5be63d497a16d318e92f47ab9245a3 Mon Sep 17 00:00:00 2001
From: Maxim Vezenov <mvezenov@gmail.com>
Date: Tue, 21 Jan 2025 21:52:21 +0000
Subject: [PATCH 2/4] fmt and cleanup

---
 .../src/ssa/opt/loop_invariant.rs             |    10 +-
 .../execution_success/regression_7128/ssa.txt | 19189 ----------------
 2 files changed, 8 insertions(+), 19191 deletions(-)
 delete mode 100644 test_programs/execution_success/regression_7128/ssa.txt

diff --git a/compiler/noirc_evaluator/src/ssa/opt/loop_invariant.rs b/compiler/noirc_evaluator/src/ssa/opt/loop_invariant.rs
index 796879738b1..1e2e783d516 100644
--- a/compiler/noirc_evaluator/src/ssa/opt/loop_invariant.rs
+++ b/compiler/noirc_evaluator/src/ssa/opt/loop_invariant.rs
@@ -12,7 +12,13 @@ use fxhash::{FxHashMap as HashMap, FxHashSet as HashSet};
 
 use crate::ssa::{
     ir::{
-        basic_block::BasicBlockId, function::Function, function_inserter::FunctionInserter, instruction::{binary::eval_constant_binary_op, BinaryOp, Instruction, InstructionId}, post_order::PostOrder, types::Type, value::ValueId
+        basic_block::BasicBlockId,
+        function::Function,
+        function_inserter::FunctionInserter,
+        instruction::{binary::eval_constant_binary_op, BinaryOp, Instruction, InstructionId},
+        post_order::PostOrder,
+        types::Type,
+        value::ValueId,
     },
     Ssa,
 };
@@ -268,7 +274,7 @@ impl<'f> LoopInvariantContext<'f> {
     /// Leaving out this mapping could lead to instructions with values that do not exist.
     fn map_dependent_instructions(&mut self) {
         let mut block_order = PostOrder::with_function(self.inserter.function).into_vec();
-        block_order.reverse(); 
+        block_order.reverse();
 
         for block in block_order {
             for instruction_id in self.inserter.function.dfg[block].take_instructions() {
diff --git a/test_programs/execution_success/regression_7128/ssa.txt b/test_programs/execution_success/regression_7128/ssa.txt
deleted file mode 100644
index 7665d52c992..00000000000
--- a/test_programs/execution_success/regression_7128/ssa.txt
+++ /dev/null
@@ -1,19189 +0,0 @@
-After Initial SSA:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v6 = allocate -> &mut Field
-    store Field 0 at v6
-    v8 = allocate -> &mut Field
-    store Field 0 at v8
-    v9 = load v6 -> Field
-    v10 = load v6 -> Field
-    v11 = eq v9, v10
-    v13 = unchecked_mul v11, u1 1
-    jmpif v13 then: b1, else: b4
-  b1():
-    v15 = call f1(v4) -> [u8; 32]
-    v17 = call f1(Field 0) -> [u8; 32]
-    v18 = allocate -> &mut [u8; 32]
-    store v17 at v18
-    jmp b2(u32 0)
-  b2(v5: u32):
-    v21 = lt v5, u32 32
-    jmpif v21 then: b7, else: b3
-  b3():
-    v22 = load v18 -> [u8; 32]
-    v24 = call f2(v22) -> Field
-    store v24 at v8
-    jmp b4()
-  b4():
-    v25 = allocate -> &mut Field
-    store Field 0 at v25
-    v27 = call f3(Field 0, v4) -> u1
-    jmpif v27 then: b5, else: b6
-  b5():
-    store Field 1 at v25
-    jmp b6()
-  b6():
-    v29 = load v25 -> Field
-    v30 = load v8 -> Field
-    v31 = sub v29, v30
-    store v31 at v6
-    v32 = load v6 -> Field
-    return v32
-  b7():
-    v33 = load v18 -> [u8; 32]
-    v34 = array_get v15, index v5 -> u8
-    v35 = load v18 -> [u8; 32]
-    v36 = array_get v35, index v5 -> u8
-    v37 = xor v34, v36
-    v38 = array_set v33, index v5, value v37
-    v40 = unchecked_add v5, u32 1
-    store v38 at v18
-    v41 = unchecked_add v5, u32 1
-    jmp b2(v41)
-}
-acir(inline) fn to_be_bytes f1 {
-  b0(v4: Field):
-    v8 = call f18(v4, u32 256) -> [u8; 32]
-    v38 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v39 = allocate -> &mut u1
-    store u1 0 at v39
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v43 = lt v5, u32 32
-    jmpif v43 then: b3, else: b2
-  b2():
-    v44 = load v39 -> u1
-    constrain v44 == u1 1
-    return v8
-  b3():
-    v46 = load v39 -> u1
-    v47 = not v46
-    jmpif v47 then: b4, else: b7
-  b4():
-    v48 = array_get v8, index v5 -> u8
-    v49 = lt v5, u32 32
-    constrain v49 == u1 1, "Index out of bounds"
-    v50 = array_get v38, index v5 -> u8
-    v51 = eq v48, v50
-    v52 = not v51
-    jmpif v52 then: b5, else: b6
-  b5():
-    v53 = array_get v8, index v5 -> u8
-    v54 = lt v5, u32 32
-    constrain v54 == u1 1, "Index out of bounds"
-    v55 = array_get v38, index v5 -> u8
-    v56 = lt v53, v55
-    constrain v56 == u1 1
-    store u1 1 at v39
-    jmp b6()
-  b6():
-    jmp b7()
-  b7():
-    v58 = unchecked_add v5, u32 1
-    jmp b1(v58)
-}
-acir(inline) fn bytes32_to_field f2 {
-  b0(v4: [u8; 32]):
-    v6 = allocate -> &mut Field
-    store Field 1 at v6
-    v8 = allocate -> &mut Field
-    store Field 0 at v8
-    v10 = allocate -> &mut Field
-    store Field 0 at v10
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v13 = lt v5, u32 16
-    jmpif v13 then: b3, else: b2
-  b2():
-    v14 = load v10 -> Field
-    v15 = load v8 -> Field
-    v16 = load v6 -> Field
-    v17 = mul v15, v16
-    v18 = add v14, v17
-    return v18
-  b3():
-    v19 = load v8 -> Field
-    v21 = sub u32 15, v5
-    v22 = array_get v4, index v21 -> u8
-    v23 = cast v22 as Field
-    v24 = load v6 -> Field
-    v25 = mul v23, v24
-    v26 = add v19, v25
-    store v26 at v8
-    v27 = load v10 -> Field
-    v29 = sub u32 31, v5
-    v30 = array_get v4, index v29 -> u8
-    v31 = cast v30 as Field
-    v32 = load v6 -> Field
-    v33 = mul v31, v32
-    v34 = add v27, v33
-    store v34 at v10
-    v35 = load v6 -> Field
-    v37 = mul v35, Field 256
-    store v37 at v6
-    v39 = unchecked_add v5, u32 1
-    jmp b1(v39)
-}
-acir(inline) fn lt f3 {
-  b0(v4: Field, v5: Field):
-    v8 = call f4() -> u1
-    jmpif v8 then: b2, else: b1
-  b1():
-    v10 = call f6(v4, v5) -> u1
-    jmp b3(v10)
-  b2():
-    v12 = call f5(v4, v5) -> u1
-    jmp b3(v12)
-  b3(v6: u1):
-    return v6
-}
-acir(inline) fn is_bn254 f4 {
-  b0():
-    return u1 1
-}
-acir(inline) fn lt f5 {
-  b0(v4: Field, v5: Field):
-    v7 = call f9(v5, v4) -> u1
-    return v7
-}
-acir(inline) fn lt_fallback f6 {
-  b0(v4: Field, v5: Field):
-    v8 = call f7(v4) -> [u8; 32]
-    v10 = call f7(v5) -> [u8; 32]
-    v11 = allocate -> &mut u1
-    store u1 0 at v11
-    v13 = allocate -> &mut u1
-    store u1 0 at v13
-    jmp b1(u32 0)
-  b1(v6: u32):
-    v16 = lt v6, u32 32
-    jmpif v16 then: b3, else: b2
-  b2():
-    v17 = load v11 -> u1
-    return v17
-  b3():
-    v18 = load v13 -> u1
-    v19 = not v18
-    jmpif v19 then: b4, else: b7
-  b4():
-    v21 = sub u32 31, v6
-    v22 = array_get v8, index v21 -> u8
-    v23 = sub u32 31, v6
-    v24 = array_get v10, index v23 -> u8
-    v25 = eq v22, v24
-    v26 = not v25
-    jmpif v26 then: b5, else: b6
-  b5():
-    v27 = lt v22, v24
-    store v27 at v11
-    store u1 1 at v13
-    jmp b6()
-  b6():
-    jmp b7()
-  b7():
-    v30 = unchecked_add v6, u32 1
-    jmp b1(v30)
-}
-acir(inline) fn to_le_bytes f7 {
-  b0(v4: Field):
-    v8 = call f8(v4, u32 256) -> [u8; 32]
-    v38 = make_array [u8 1, u8 0, u8 0, u8 240, u8 147, u8 245, u8 225, u8 67, u8 145, u8 112, u8 185, u8 121, u8 72, u8 232, u8 51, u8 40, u8 93, u8 88, u8 129, u8 129, u8 182, u8 69, u8 80, u8 184, u8 41, u8 160, u8 49, u8 225, u8 114, u8 78, u8 100, u8 48] : [u8]
-    v39 = allocate -> &mut u1
-    store u1 0 at v39
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v43 = lt v5, u32 32
-    jmpif v43 then: b3, else: b2
-  b2():
-    v44 = load v39 -> u1
-    constrain v44 == u1 1
-    return v8
-  b3():
-    v46 = load v39 -> u1
-    v47 = not v46
-    jmpif v47 then: b4, else: b7
-  b4():
-    v49 = sub u32 31, v5
-    v50 = array_get v8, index v49 -> u8
-    v51 = sub u32 31, v5
-    v52 = lt v51, u32 32
-    constrain v52 == u1 1, "Index out of bounds"
-    v53 = array_get v38, index v51 -> u8
-    v54 = eq v50, v53
-    v55 = not v54
-    jmpif v55 then: b5, else: b6
-  b5():
-    v56 = sub u32 31, v5
-    v57 = array_get v8, index v56 -> u8
-    v58 = sub u32 31, v5
-    v59 = lt v58, u32 32
-    constrain v59 == u1 1, "Index out of bounds"
-    v60 = array_get v38, index v58 -> u8
-    v61 = lt v57, v60
-    constrain v61 == u1 1
-    store u1 1 at v39
-    jmp b6()
-  b6():
-    jmp b7()
-  b7():
-    v63 = unchecked_add v5, u32 1
-    jmp b1(v63)
-}
-acir(inline) fn to_le_radix f8 {
-  b0(v4: Field, v5: u32):
-    call assert_constant(v5)
-    v8 = call to_le_radix(v4, v5) -> [u8; 32]
-    return v8
-}
-acir(inline) fn gt f9 {
-  b0(v4: Field, v5: Field):
-    v8 = eq v4, v5
-    jmpif v8 then: b5, else: b1
-  b1():
-    v10 = call f10(v4, v5) -> u1
-    jmpif v10 then: b3, else: b2
-  b2():
-    call f11(v4, v5)
-    jmp b4(u1 1)
-  b3():
-    call f11(v5, v4)
-    jmp b4(u1 0)
-  b4(v6: u1):
-    jmp b6(v6)
-  b5():
-    jmp b6(u1 0)
-  b6(v7: u1):
-    return v7
-}
-brillig(inline) fn field_less_than f10 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-acir(inline) fn assert_gt f11 {
-  b0(v4: Field, v5: Field):
-    v7, v8 = call f12(v4) -> (Field, Field)
-    v10, v11 = call f12(v5) -> (Field, Field)
-    call f13(v7, v8, v10, v11)
-    return
-}
-acir(inline) fn decompose f12 {
-  b0(v4: Field):
-    v6, v7 = call f16(v4) -> (Field, Field)
-    call f15(v6)
-    call f15(v7)
-    v10 = mul Field 340282366920938463463374607431768211456, v7
-    v11 = add v6, v10
-    v12 = eq v4, v11
-    constrain v4 == v11
-    call f13(Field 53438638232309528389504892708671455233, Field 64323764613183177041862057485226039389, v6, v7)
-    return v6, v7
-}
-acir(inline) fn assert_gt_limbs f13 {
-  b0(v4: Field, v5: Field, v6: Field, v7: Field):
-    v9 = call f14(v4, v6) -> u1
-    v10 = sub v4, v6
-    v12 = sub v10, Field 1
-    v13 = cast v9 as Field
-    v14 = mul v13, Field 340282366920938463463374607431768211456
-    v15 = add v12, v14
-    v16 = sub v5, v7
-    v17 = cast v9 as Field
-    v18 = sub v16, v17
-    call f15(v15)
-    call f15(v18)
-    return
-}
-brillig(inline) fn lte_hint f14 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f10(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-acir(inline) fn assert_max_bit_size f15 {
-  b0(v4: Field):
-    range_check v4 to 128 bits
-    return
-}
-brillig(inline) fn decompose_hint f16 {
-  b0(v4: Field):
-    v6, v7 = call f17(v4) -> (Field, Field)
-    return v6, v7
-}
-brillig(inline) fn compute_decomposition f17 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    store v4 at v5
-    v6 = load v5 -> Field
-    v7 = truncate v6 to 64 bits, max_bit_size: 254
-    v8 = cast v7 as u64
-    v9 = cast v7 as Field
-    v10 = load v5 -> Field
-    v11 = sub v10, v9
-    v12 = div v11, Field 18446744073709551616
-    store v12 at v5
-    v13 = load v5 -> Field
-    v14 = truncate v13 to 64 bits, max_bit_size: 254
-    v15 = cast v14 as u64
-    v16 = cast v14 as Field
-    v17 = load v5 -> Field
-    v18 = sub v17, v16
-    v19 = div v18, Field 18446744073709551616
-    v20 = mul v16, Field 18446744073709551616
-    v21 = add v20, v9
-    return v21, v19
-}
-acir(inline) fn to_be_radix f18 {
-  b0(v4: Field, v5: u32):
-    call assert_constant(v5)
-    v8 = call to_be_radix(v4, v5) -> [u8; 32]
-    return v8
-}
-
-After Removing Unreachable Functions:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v6 = allocate -> &mut Field
-    store Field 0 at v6
-    v8 = allocate -> &mut Field
-    store Field 0 at v8
-    v9 = load v6 -> Field
-    v10 = load v6 -> Field
-    v11 = eq v9, v10
-    v13 = unchecked_mul v11, u1 1
-    jmpif v13 then: b1, else: b4
-  b1():
-    v15 = call f1(v4) -> [u8; 32]
-    v17 = call f1(Field 0) -> [u8; 32]
-    v18 = allocate -> &mut [u8; 32]
-    store v17 at v18
-    jmp b2(u32 0)
-  b2(v5: u32):
-    v21 = lt v5, u32 32
-    jmpif v21 then: b7, else: b3
-  b3():
-    v22 = load v18 -> [u8; 32]
-    v24 = call f2(v22) -> Field
-    store v24 at v8
-    jmp b4()
-  b4():
-    v25 = allocate -> &mut Field
-    store Field 0 at v25
-    v27 = call f3(Field 0, v4) -> u1
-    jmpif v27 then: b5, else: b6
-  b5():
-    store Field 1 at v25
-    jmp b6()
-  b6():
-    v29 = load v25 -> Field
-    v30 = load v8 -> Field
-    v31 = sub v29, v30
-    store v31 at v6
-    v32 = load v6 -> Field
-    return v32
-  b7():
-    v33 = load v18 -> [u8; 32]
-    v34 = array_get v15, index v5 -> u8
-    v35 = load v18 -> [u8; 32]
-    v36 = array_get v35, index v5 -> u8
-    v37 = xor v34, v36
-    v38 = array_set v33, index v5, value v37
-    v40 = unchecked_add v5, u32 1
-    store v38 at v18
-    v41 = unchecked_add v5, u32 1
-    jmp b2(v41)
-}
-acir(inline) fn to_be_bytes f1 {
-  b0(v4: Field):
-    v8 = call f18(v4, u32 256) -> [u8; 32]
-    v38 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v39 = allocate -> &mut u1
-    store u1 0 at v39
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v43 = lt v5, u32 32
-    jmpif v43 then: b3, else: b2
-  b2():
-    v44 = load v39 -> u1
-    constrain v44 == u1 1
-    return v8
-  b3():
-    v46 = load v39 -> u1
-    v47 = not v46
-    jmpif v47 then: b4, else: b7
-  b4():
-    v48 = array_get v8, index v5 -> u8
-    v49 = lt v5, u32 32
-    constrain v49 == u1 1, "Index out of bounds"
-    v50 = array_get v38, index v5 -> u8
-    v51 = eq v48, v50
-    v52 = not v51
-    jmpif v52 then: b5, else: b6
-  b5():
-    v53 = array_get v8, index v5 -> u8
-    v54 = lt v5, u32 32
-    constrain v54 == u1 1, "Index out of bounds"
-    v55 = array_get v38, index v5 -> u8
-    v56 = lt v53, v55
-    constrain v56 == u1 1
-    store u1 1 at v39
-    jmp b6()
-  b6():
-    jmp b7()
-  b7():
-    v58 = unchecked_add v5, u32 1
-    jmp b1(v58)
-}
-acir(inline) fn bytes32_to_field f2 {
-  b0(v4: [u8; 32]):
-    v6 = allocate -> &mut Field
-    store Field 1 at v6
-    v8 = allocate -> &mut Field
-    store Field 0 at v8
-    v10 = allocate -> &mut Field
-    store Field 0 at v10
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v13 = lt v5, u32 16
-    jmpif v13 then: b3, else: b2
-  b2():
-    v14 = load v10 -> Field
-    v15 = load v8 -> Field
-    v16 = load v6 -> Field
-    v17 = mul v15, v16
-    v18 = add v14, v17
-    return v18
-  b3():
-    v19 = load v8 -> Field
-    v21 = sub u32 15, v5
-    v22 = array_get v4, index v21 -> u8
-    v23 = cast v22 as Field
-    v24 = load v6 -> Field
-    v25 = mul v23, v24
-    v26 = add v19, v25
-    store v26 at v8
-    v27 = load v10 -> Field
-    v29 = sub u32 31, v5
-    v30 = array_get v4, index v29 -> u8
-    v31 = cast v30 as Field
-    v32 = load v6 -> Field
-    v33 = mul v31, v32
-    v34 = add v27, v33
-    store v34 at v10
-    v35 = load v6 -> Field
-    v37 = mul v35, Field 256
-    store v37 at v6
-    v39 = unchecked_add v5, u32 1
-    jmp b1(v39)
-}
-acir(inline) fn lt f3 {
-  b0(v4: Field, v5: Field):
-    v8 = call f4() -> u1
-    jmpif v8 then: b2, else: b1
-  b1():
-    v10 = call f6(v4, v5) -> u1
-    jmp b3(v10)
-  b2():
-    v12 = call f5(v4, v5) -> u1
-    jmp b3(v12)
-  b3(v6: u1):
-    return v6
-}
-acir(inline) fn is_bn254 f4 {
-  b0():
-    return u1 1
-}
-acir(inline) fn lt f5 {
-  b0(v4: Field, v5: Field):
-    v7 = call f9(v5, v4) -> u1
-    return v7
-}
-acir(inline) fn lt_fallback f6 {
-  b0(v4: Field, v5: Field):
-    v8 = call f7(v4) -> [u8; 32]
-    v10 = call f7(v5) -> [u8; 32]
-    v11 = allocate -> &mut u1
-    store u1 0 at v11
-    v13 = allocate -> &mut u1
-    store u1 0 at v13
-    jmp b1(u32 0)
-  b1(v6: u32):
-    v16 = lt v6, u32 32
-    jmpif v16 then: b3, else: b2
-  b2():
-    v17 = load v11 -> u1
-    return v17
-  b3():
-    v18 = load v13 -> u1
-    v19 = not v18
-    jmpif v19 then: b4, else: b7
-  b4():
-    v21 = sub u32 31, v6
-    v22 = array_get v8, index v21 -> u8
-    v23 = sub u32 31, v6
-    v24 = array_get v10, index v23 -> u8
-    v25 = eq v22, v24
-    v26 = not v25
-    jmpif v26 then: b5, else: b6
-  b5():
-    v27 = lt v22, v24
-    store v27 at v11
-    store u1 1 at v13
-    jmp b6()
-  b6():
-    jmp b7()
-  b7():
-    v30 = unchecked_add v6, u32 1
-    jmp b1(v30)
-}
-acir(inline) fn to_le_bytes f7 {
-  b0(v4: Field):
-    v8 = call f8(v4, u32 256) -> [u8; 32]
-    v38 = make_array [u8 1, u8 0, u8 0, u8 240, u8 147, u8 245, u8 225, u8 67, u8 145, u8 112, u8 185, u8 121, u8 72, u8 232, u8 51, u8 40, u8 93, u8 88, u8 129, u8 129, u8 182, u8 69, u8 80, u8 184, u8 41, u8 160, u8 49, u8 225, u8 114, u8 78, u8 100, u8 48] : [u8]
-    v39 = allocate -> &mut u1
-    store u1 0 at v39
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v43 = lt v5, u32 32
-    jmpif v43 then: b3, else: b2
-  b2():
-    v44 = load v39 -> u1
-    constrain v44 == u1 1
-    return v8
-  b3():
-    v46 = load v39 -> u1
-    v47 = not v46
-    jmpif v47 then: b4, else: b7
-  b4():
-    v49 = sub u32 31, v5
-    v50 = array_get v8, index v49 -> u8
-    v51 = sub u32 31, v5
-    v52 = lt v51, u32 32
-    constrain v52 == u1 1, "Index out of bounds"
-    v53 = array_get v38, index v51 -> u8
-    v54 = eq v50, v53
-    v55 = not v54
-    jmpif v55 then: b5, else: b6
-  b5():
-    v56 = sub u32 31, v5
-    v57 = array_get v8, index v56 -> u8
-    v58 = sub u32 31, v5
-    v59 = lt v58, u32 32
-    constrain v59 == u1 1, "Index out of bounds"
-    v60 = array_get v38, index v58 -> u8
-    v61 = lt v57, v60
-    constrain v61 == u1 1
-    store u1 1 at v39
-    jmp b6()
-  b6():
-    jmp b7()
-  b7():
-    v63 = unchecked_add v5, u32 1
-    jmp b1(v63)
-}
-acir(inline) fn to_le_radix f8 {
-  b0(v4: Field, v5: u32):
-    call assert_constant(v5)
-    v8 = call to_le_radix(v4, v5) -> [u8; 32]
-    return v8
-}
-acir(inline) fn gt f9 {
-  b0(v4: Field, v5: Field):
-    v8 = eq v4, v5
-    jmpif v8 then: b5, else: b1
-  b1():
-    v10 = call f10(v4, v5) -> u1
-    jmpif v10 then: b3, else: b2
-  b2():
-    call f11(v4, v5)
-    jmp b4(u1 1)
-  b3():
-    call f11(v5, v4)
-    jmp b4(u1 0)
-  b4(v6: u1):
-    jmp b6(v6)
-  b5():
-    jmp b6(u1 0)
-  b6(v7: u1):
-    return v7
-}
-brillig(inline) fn field_less_than f10 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-acir(inline) fn assert_gt f11 {
-  b0(v4: Field, v5: Field):
-    v7, v8 = call f12(v4) -> (Field, Field)
-    v10, v11 = call f12(v5) -> (Field, Field)
-    call f13(v7, v8, v10, v11)
-    return
-}
-acir(inline) fn decompose f12 {
-  b0(v4: Field):
-    v6, v7 = call f16(v4) -> (Field, Field)
-    call f15(v6)
-    call f15(v7)
-    v10 = mul Field 340282366920938463463374607431768211456, v7
-    v11 = add v6, v10
-    v12 = eq v4, v11
-    constrain v4 == v11
-    call f13(Field 53438638232309528389504892708671455233, Field 64323764613183177041862057485226039389, v6, v7)
-    return v6, v7
-}
-acir(inline) fn assert_gt_limbs f13 {
-  b0(v4: Field, v5: Field, v6: Field, v7: Field):
-    v9 = call f14(v4, v6) -> u1
-    v10 = sub v4, v6
-    v12 = sub v10, Field 1
-    v13 = cast v9 as Field
-    v14 = mul v13, Field 340282366920938463463374607431768211456
-    v15 = add v12, v14
-    v16 = sub v5, v7
-    v17 = cast v9 as Field
-    v18 = sub v16, v17
-    call f15(v15)
-    call f15(v18)
-    return
-}
-brillig(inline) fn lte_hint f14 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f10(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-acir(inline) fn assert_max_bit_size f15 {
-  b0(v4: Field):
-    range_check v4 to 128 bits
-    return
-}
-brillig(inline) fn decompose_hint f16 {
-  b0(v4: Field):
-    v6, v7 = call f17(v4) -> (Field, Field)
-    return v6, v7
-}
-brillig(inline) fn compute_decomposition f17 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    store v4 at v5
-    v6 = load v5 -> Field
-    v7 = truncate v6 to 64 bits, max_bit_size: 254
-    v8 = cast v7 as u64
-    v9 = cast v7 as Field
-    v10 = load v5 -> Field
-    v11 = sub v10, v9
-    v12 = div v11, Field 18446744073709551616
-    store v12 at v5
-    v13 = load v5 -> Field
-    v14 = truncate v13 to 64 bits, max_bit_size: 254
-    v15 = cast v14 as u64
-    v16 = cast v14 as Field
-    v17 = load v5 -> Field
-    v18 = sub v17, v16
-    v19 = div v18, Field 18446744073709551616
-    v20 = mul v16, Field 18446744073709551616
-    v21 = add v20, v9
-    return v21, v19
-}
-acir(inline) fn to_be_radix f18 {
-  b0(v4: Field, v5: u32):
-    call assert_constant(v5)
-    v8 = call to_be_radix(v4, v5) -> [u8; 32]
-    return v8
-}
-
-After Defunctionalization:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v6 = allocate -> &mut Field
-    store Field 0 at v6
-    v8 = allocate -> &mut Field
-    store Field 0 at v8
-    v9 = load v6 -> Field
-    v10 = load v6 -> Field
-    v11 = eq v9, v10
-    v13 = unchecked_mul v11, u1 1
-    jmpif v13 then: b1, else: b4
-  b1():
-    v15 = call f1(v4) -> [u8; 32]
-    v17 = call f1(Field 0) -> [u8; 32]
-    v18 = allocate -> &mut [u8; 32]
-    store v17 at v18
-    jmp b2(u32 0)
-  b2(v5: u32):
-    v21 = lt v5, u32 32
-    jmpif v21 then: b7, else: b3
-  b3():
-    v22 = load v18 -> [u8; 32]
-    v24 = call f2(v22) -> Field
-    store v24 at v8
-    jmp b4()
-  b4():
-    v25 = allocate -> &mut Field
-    store Field 0 at v25
-    v27 = call f3(Field 0, v4) -> u1
-    jmpif v27 then: b5, else: b6
-  b5():
-    store Field 1 at v25
-    jmp b6()
-  b6():
-    v29 = load v25 -> Field
-    v30 = load v8 -> Field
-    v31 = sub v29, v30
-    store v31 at v6
-    v32 = load v6 -> Field
-    return v32
-  b7():
-    v33 = load v18 -> [u8; 32]
-    v34 = array_get v15, index v5 -> u8
-    v35 = load v18 -> [u8; 32]
-    v36 = array_get v35, index v5 -> u8
-    v37 = xor v34, v36
-    v38 = array_set v33, index v5, value v37
-    v40 = unchecked_add v5, u32 1
-    store v38 at v18
-    v41 = unchecked_add v5, u32 1
-    jmp b2(v41)
-}
-acir(inline) fn to_be_bytes f1 {
-  b0(v4: Field):
-    v8 = call f18(v4, u32 256) -> [u8; 32]
-    v38 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v39 = allocate -> &mut u1
-    store u1 0 at v39
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v43 = lt v5, u32 32
-    jmpif v43 then: b3, else: b2
-  b2():
-    v44 = load v39 -> u1
-    constrain v44 == u1 1
-    return v8
-  b3():
-    v46 = load v39 -> u1
-    v47 = not v46
-    jmpif v47 then: b4, else: b7
-  b4():
-    v48 = array_get v8, index v5 -> u8
-    v49 = lt v5, u32 32
-    constrain v49 == u1 1, "Index out of bounds"
-    v50 = array_get v38, index v5 -> u8
-    v51 = eq v48, v50
-    v52 = not v51
-    jmpif v52 then: b5, else: b6
-  b5():
-    v53 = array_get v8, index v5 -> u8
-    v54 = lt v5, u32 32
-    constrain v54 == u1 1, "Index out of bounds"
-    v55 = array_get v38, index v5 -> u8
-    v56 = lt v53, v55
-    constrain v56 == u1 1
-    store u1 1 at v39
-    jmp b6()
-  b6():
-    jmp b7()
-  b7():
-    v58 = unchecked_add v5, u32 1
-    jmp b1(v58)
-}
-acir(inline) fn bytes32_to_field f2 {
-  b0(v4: [u8; 32]):
-    v6 = allocate -> &mut Field
-    store Field 1 at v6
-    v8 = allocate -> &mut Field
-    store Field 0 at v8
-    v10 = allocate -> &mut Field
-    store Field 0 at v10
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v13 = lt v5, u32 16
-    jmpif v13 then: b3, else: b2
-  b2():
-    v14 = load v10 -> Field
-    v15 = load v8 -> Field
-    v16 = load v6 -> Field
-    v17 = mul v15, v16
-    v18 = add v14, v17
-    return v18
-  b3():
-    v19 = load v8 -> Field
-    v21 = sub u32 15, v5
-    v22 = array_get v4, index v21 -> u8
-    v23 = cast v22 as Field
-    v24 = load v6 -> Field
-    v25 = mul v23, v24
-    v26 = add v19, v25
-    store v26 at v8
-    v27 = load v10 -> Field
-    v29 = sub u32 31, v5
-    v30 = array_get v4, index v29 -> u8
-    v31 = cast v30 as Field
-    v32 = load v6 -> Field
-    v33 = mul v31, v32
-    v34 = add v27, v33
-    store v34 at v10
-    v35 = load v6 -> Field
-    v37 = mul v35, Field 256
-    store v37 at v6
-    v39 = unchecked_add v5, u32 1
-    jmp b1(v39)
-}
-acir(inline) fn lt f3 {
-  b0(v4: Field, v5: Field):
-    v8 = call f4() -> u1
-    jmpif v8 then: b2, else: b1
-  b1():
-    v10 = call f6(v4, v5) -> u1
-    jmp b3(v10)
-  b2():
-    v12 = call f5(v4, v5) -> u1
-    jmp b3(v12)
-  b3(v6: u1):
-    return v6
-}
-acir(inline) fn is_bn254 f4 {
-  b0():
-    return u1 1
-}
-acir(inline) fn lt f5 {
-  b0(v4: Field, v5: Field):
-    v7 = call f9(v5, v4) -> u1
-    return v7
-}
-acir(inline) fn lt_fallback f6 {
-  b0(v4: Field, v5: Field):
-    v8 = call f7(v4) -> [u8; 32]
-    v10 = call f7(v5) -> [u8; 32]
-    v11 = allocate -> &mut u1
-    store u1 0 at v11
-    v13 = allocate -> &mut u1
-    store u1 0 at v13
-    jmp b1(u32 0)
-  b1(v6: u32):
-    v16 = lt v6, u32 32
-    jmpif v16 then: b3, else: b2
-  b2():
-    v17 = load v11 -> u1
-    return v17
-  b3():
-    v18 = load v13 -> u1
-    v19 = not v18
-    jmpif v19 then: b4, else: b7
-  b4():
-    v21 = sub u32 31, v6
-    v22 = array_get v8, index v21 -> u8
-    v23 = sub u32 31, v6
-    v24 = array_get v10, index v23 -> u8
-    v25 = eq v22, v24
-    v26 = not v25
-    jmpif v26 then: b5, else: b6
-  b5():
-    v27 = lt v22, v24
-    store v27 at v11
-    store u1 1 at v13
-    jmp b6()
-  b6():
-    jmp b7()
-  b7():
-    v30 = unchecked_add v6, u32 1
-    jmp b1(v30)
-}
-acir(inline) fn to_le_bytes f7 {
-  b0(v4: Field):
-    v8 = call f8(v4, u32 256) -> [u8; 32]
-    v38 = make_array [u8 1, u8 0, u8 0, u8 240, u8 147, u8 245, u8 225, u8 67, u8 145, u8 112, u8 185, u8 121, u8 72, u8 232, u8 51, u8 40, u8 93, u8 88, u8 129, u8 129, u8 182, u8 69, u8 80, u8 184, u8 41, u8 160, u8 49, u8 225, u8 114, u8 78, u8 100, u8 48] : [u8]
-    v39 = allocate -> &mut u1
-    store u1 0 at v39
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v43 = lt v5, u32 32
-    jmpif v43 then: b3, else: b2
-  b2():
-    v44 = load v39 -> u1
-    constrain v44 == u1 1
-    return v8
-  b3():
-    v46 = load v39 -> u1
-    v47 = not v46
-    jmpif v47 then: b4, else: b7
-  b4():
-    v49 = sub u32 31, v5
-    v50 = array_get v8, index v49 -> u8
-    v51 = sub u32 31, v5
-    v52 = lt v51, u32 32
-    constrain v52 == u1 1, "Index out of bounds"
-    v53 = array_get v38, index v51 -> u8
-    v54 = eq v50, v53
-    v55 = not v54
-    jmpif v55 then: b5, else: b6
-  b5():
-    v56 = sub u32 31, v5
-    v57 = array_get v8, index v56 -> u8
-    v58 = sub u32 31, v5
-    v59 = lt v58, u32 32
-    constrain v59 == u1 1, "Index out of bounds"
-    v60 = array_get v38, index v58 -> u8
-    v61 = lt v57, v60
-    constrain v61 == u1 1
-    store u1 1 at v39
-    jmp b6()
-  b6():
-    jmp b7()
-  b7():
-    v63 = unchecked_add v5, u32 1
-    jmp b1(v63)
-}
-acir(inline) fn to_le_radix f8 {
-  b0(v4: Field, v5: u32):
-    call assert_constant(v5)
-    v8 = call to_le_radix(v4, v5) -> [u8; 32]
-    return v8
-}
-acir(inline) fn gt f9 {
-  b0(v4: Field, v5: Field):
-    v8 = eq v4, v5
-    jmpif v8 then: b5, else: b1
-  b1():
-    v10 = call f10(v4, v5) -> u1
-    jmpif v10 then: b3, else: b2
-  b2():
-    call f11(v4, v5)
-    jmp b4(u1 1)
-  b3():
-    call f11(v5, v4)
-    jmp b4(u1 0)
-  b4(v6: u1):
-    jmp b6(v6)
-  b5():
-    jmp b6(u1 0)
-  b6(v7: u1):
-    return v7
-}
-brillig(inline) fn field_less_than f10 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-acir(inline) fn assert_gt f11 {
-  b0(v4: Field, v5: Field):
-    v7, v8 = call f12(v4) -> (Field, Field)
-    v10, v11 = call f12(v5) -> (Field, Field)
-    call f13(v7, v8, v10, v11)
-    return
-}
-acir(inline) fn decompose f12 {
-  b0(v4: Field):
-    v6, v7 = call f16(v4) -> (Field, Field)
-    call f15(v6)
-    call f15(v7)
-    v10 = mul Field 340282366920938463463374607431768211456, v7
-    v11 = add v6, v10
-    v12 = eq v4, v11
-    constrain v4 == v11
-    call f13(Field 53438638232309528389504892708671455233, Field 64323764613183177041862057485226039389, v6, v7)
-    return v6, v7
-}
-acir(inline) fn assert_gt_limbs f13 {
-  b0(v4: Field, v5: Field, v6: Field, v7: Field):
-    v9 = call f14(v4, v6) -> u1
-    v10 = sub v4, v6
-    v12 = sub v10, Field 1
-    v13 = cast v9 as Field
-    v14 = mul v13, Field 340282366920938463463374607431768211456
-    v15 = add v12, v14
-    v16 = sub v5, v7
-    v17 = cast v9 as Field
-    v18 = sub v16, v17
-    call f15(v15)
-    call f15(v18)
-    return
-}
-brillig(inline) fn lte_hint f14 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f10(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-acir(inline) fn assert_max_bit_size f15 {
-  b0(v4: Field):
-    range_check v4 to 128 bits
-    return
-}
-brillig(inline) fn decompose_hint f16 {
-  b0(v4: Field):
-    v6, v7 = call f17(v4) -> (Field, Field)
-    return v6, v7
-}
-brillig(inline) fn compute_decomposition f17 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    store v4 at v5
-    v6 = load v5 -> Field
-    v7 = truncate v6 to 64 bits, max_bit_size: 254
-    v8 = cast v7 as u64
-    v9 = cast v7 as Field
-    v10 = load v5 -> Field
-    v11 = sub v10, v9
-    v12 = div v11, Field 18446744073709551616
-    store v12 at v5
-    v13 = load v5 -> Field
-    v14 = truncate v13 to 64 bits, max_bit_size: 254
-    v15 = cast v14 as u64
-    v16 = cast v14 as Field
-    v17 = load v5 -> Field
-    v18 = sub v17, v16
-    v19 = div v18, Field 18446744073709551616
-    v20 = mul v16, Field 18446744073709551616
-    v21 = add v20, v9
-    return v21, v19
-}
-acir(inline) fn to_be_radix f18 {
-  b0(v4: Field, v5: u32):
-    call assert_constant(v5)
-    v8 = call to_be_radix(v4, v5) -> [u8; 32]
-    return v8
-}
-
-After Removing Paired rc_inc & rc_decs:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v6 = allocate -> &mut Field
-    store Field 0 at v6
-    v8 = allocate -> &mut Field
-    store Field 0 at v8
-    v9 = load v6 -> Field
-    v10 = load v6 -> Field
-    v11 = eq v9, v10
-    v13 = unchecked_mul v11, u1 1
-    jmpif v13 then: b1, else: b4
-  b1():
-    v15 = call f1(v4) -> [u8; 32]
-    v17 = call f1(Field 0) -> [u8; 32]
-    v18 = allocate -> &mut [u8; 32]
-    store v17 at v18
-    jmp b2(u32 0)
-  b2(v5: u32):
-    v21 = lt v5, u32 32
-    jmpif v21 then: b7, else: b3
-  b3():
-    v22 = load v18 -> [u8; 32]
-    v24 = call f2(v22) -> Field
-    store v24 at v8
-    jmp b4()
-  b4():
-    v25 = allocate -> &mut Field
-    store Field 0 at v25
-    v27 = call f3(Field 0, v4) -> u1
-    jmpif v27 then: b5, else: b6
-  b5():
-    store Field 1 at v25
-    jmp b6()
-  b6():
-    v29 = load v25 -> Field
-    v30 = load v8 -> Field
-    v31 = sub v29, v30
-    store v31 at v6
-    v32 = load v6 -> Field
-    return v32
-  b7():
-    v33 = load v18 -> [u8; 32]
-    v34 = array_get v15, index v5 -> u8
-    v35 = load v18 -> [u8; 32]
-    v36 = array_get v35, index v5 -> u8
-    v37 = xor v34, v36
-    v38 = array_set v33, index v5, value v37
-    v40 = unchecked_add v5, u32 1
-    store v38 at v18
-    v41 = unchecked_add v5, u32 1
-    jmp b2(v41)
-}
-acir(inline) fn to_be_bytes f1 {
-  b0(v4: Field):
-    v8 = call f18(v4, u32 256) -> [u8; 32]
-    v38 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v39 = allocate -> &mut u1
-    store u1 0 at v39
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v43 = lt v5, u32 32
-    jmpif v43 then: b3, else: b2
-  b2():
-    v44 = load v39 -> u1
-    constrain v44 == u1 1
-    return v8
-  b3():
-    v46 = load v39 -> u1
-    v47 = not v46
-    jmpif v47 then: b4, else: b7
-  b4():
-    v48 = array_get v8, index v5 -> u8
-    v49 = lt v5, u32 32
-    constrain v49 == u1 1, "Index out of bounds"
-    v50 = array_get v38, index v5 -> u8
-    v51 = eq v48, v50
-    v52 = not v51
-    jmpif v52 then: b5, else: b6
-  b5():
-    v53 = array_get v8, index v5 -> u8
-    v54 = lt v5, u32 32
-    constrain v54 == u1 1, "Index out of bounds"
-    v55 = array_get v38, index v5 -> u8
-    v56 = lt v53, v55
-    constrain v56 == u1 1
-    store u1 1 at v39
-    jmp b6()
-  b6():
-    jmp b7()
-  b7():
-    v58 = unchecked_add v5, u32 1
-    jmp b1(v58)
-}
-acir(inline) fn bytes32_to_field f2 {
-  b0(v4: [u8; 32]):
-    v6 = allocate -> &mut Field
-    store Field 1 at v6
-    v8 = allocate -> &mut Field
-    store Field 0 at v8
-    v10 = allocate -> &mut Field
-    store Field 0 at v10
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v13 = lt v5, u32 16
-    jmpif v13 then: b3, else: b2
-  b2():
-    v14 = load v10 -> Field
-    v15 = load v8 -> Field
-    v16 = load v6 -> Field
-    v17 = mul v15, v16
-    v18 = add v14, v17
-    return v18
-  b3():
-    v19 = load v8 -> Field
-    v21 = sub u32 15, v5
-    v22 = array_get v4, index v21 -> u8
-    v23 = cast v22 as Field
-    v24 = load v6 -> Field
-    v25 = mul v23, v24
-    v26 = add v19, v25
-    store v26 at v8
-    v27 = load v10 -> Field
-    v29 = sub u32 31, v5
-    v30 = array_get v4, index v29 -> u8
-    v31 = cast v30 as Field
-    v32 = load v6 -> Field
-    v33 = mul v31, v32
-    v34 = add v27, v33
-    store v34 at v10
-    v35 = load v6 -> Field
-    v37 = mul v35, Field 256
-    store v37 at v6
-    v39 = unchecked_add v5, u32 1
-    jmp b1(v39)
-}
-acir(inline) fn lt f3 {
-  b0(v4: Field, v5: Field):
-    v8 = call f4() -> u1
-    jmpif v8 then: b2, else: b1
-  b1():
-    v10 = call f6(v4, v5) -> u1
-    jmp b3(v10)
-  b2():
-    v12 = call f5(v4, v5) -> u1
-    jmp b3(v12)
-  b3(v6: u1):
-    return v6
-}
-acir(inline) fn is_bn254 f4 {
-  b0():
-    return u1 1
-}
-acir(inline) fn lt f5 {
-  b0(v4: Field, v5: Field):
-    v7 = call f9(v5, v4) -> u1
-    return v7
-}
-acir(inline) fn lt_fallback f6 {
-  b0(v4: Field, v5: Field):
-    v8 = call f7(v4) -> [u8; 32]
-    v10 = call f7(v5) -> [u8; 32]
-    v11 = allocate -> &mut u1
-    store u1 0 at v11
-    v13 = allocate -> &mut u1
-    store u1 0 at v13
-    jmp b1(u32 0)
-  b1(v6: u32):
-    v16 = lt v6, u32 32
-    jmpif v16 then: b3, else: b2
-  b2():
-    v17 = load v11 -> u1
-    return v17
-  b3():
-    v18 = load v13 -> u1
-    v19 = not v18
-    jmpif v19 then: b4, else: b7
-  b4():
-    v21 = sub u32 31, v6
-    v22 = array_get v8, index v21 -> u8
-    v23 = sub u32 31, v6
-    v24 = array_get v10, index v23 -> u8
-    v25 = eq v22, v24
-    v26 = not v25
-    jmpif v26 then: b5, else: b6
-  b5():
-    v27 = lt v22, v24
-    store v27 at v11
-    store u1 1 at v13
-    jmp b6()
-  b6():
-    jmp b7()
-  b7():
-    v30 = unchecked_add v6, u32 1
-    jmp b1(v30)
-}
-acir(inline) fn to_le_bytes f7 {
-  b0(v4: Field):
-    v8 = call f8(v4, u32 256) -> [u8; 32]
-    v38 = make_array [u8 1, u8 0, u8 0, u8 240, u8 147, u8 245, u8 225, u8 67, u8 145, u8 112, u8 185, u8 121, u8 72, u8 232, u8 51, u8 40, u8 93, u8 88, u8 129, u8 129, u8 182, u8 69, u8 80, u8 184, u8 41, u8 160, u8 49, u8 225, u8 114, u8 78, u8 100, u8 48] : [u8]
-    v39 = allocate -> &mut u1
-    store u1 0 at v39
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v43 = lt v5, u32 32
-    jmpif v43 then: b3, else: b2
-  b2():
-    v44 = load v39 -> u1
-    constrain v44 == u1 1
-    return v8
-  b3():
-    v46 = load v39 -> u1
-    v47 = not v46
-    jmpif v47 then: b4, else: b7
-  b4():
-    v49 = sub u32 31, v5
-    v50 = array_get v8, index v49 -> u8
-    v51 = sub u32 31, v5
-    v52 = lt v51, u32 32
-    constrain v52 == u1 1, "Index out of bounds"
-    v53 = array_get v38, index v51 -> u8
-    v54 = eq v50, v53
-    v55 = not v54
-    jmpif v55 then: b5, else: b6
-  b5():
-    v56 = sub u32 31, v5
-    v57 = array_get v8, index v56 -> u8
-    v58 = sub u32 31, v5
-    v59 = lt v58, u32 32
-    constrain v59 == u1 1, "Index out of bounds"
-    v60 = array_get v38, index v58 -> u8
-    v61 = lt v57, v60
-    constrain v61 == u1 1
-    store u1 1 at v39
-    jmp b6()
-  b6():
-    jmp b7()
-  b7():
-    v63 = unchecked_add v5, u32 1
-    jmp b1(v63)
-}
-acir(inline) fn to_le_radix f8 {
-  b0(v4: Field, v5: u32):
-    call assert_constant(v5)
-    v8 = call to_le_radix(v4, v5) -> [u8; 32]
-    return v8
-}
-acir(inline) fn gt f9 {
-  b0(v4: Field, v5: Field):
-    v8 = eq v4, v5
-    jmpif v8 then: b5, else: b1
-  b1():
-    v10 = call f10(v4, v5) -> u1
-    jmpif v10 then: b3, else: b2
-  b2():
-    call f11(v4, v5)
-    jmp b4(u1 1)
-  b3():
-    call f11(v5, v4)
-    jmp b4(u1 0)
-  b4(v6: u1):
-    jmp b6(v6)
-  b5():
-    jmp b6(u1 0)
-  b6(v7: u1):
-    return v7
-}
-brillig(inline) fn field_less_than f10 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-acir(inline) fn assert_gt f11 {
-  b0(v4: Field, v5: Field):
-    v7, v8 = call f12(v4) -> (Field, Field)
-    v10, v11 = call f12(v5) -> (Field, Field)
-    call f13(v7, v8, v10, v11)
-    return
-}
-acir(inline) fn decompose f12 {
-  b0(v4: Field):
-    v6, v7 = call f16(v4) -> (Field, Field)
-    call f15(v6)
-    call f15(v7)
-    v10 = mul Field 340282366920938463463374607431768211456, v7
-    v11 = add v6, v10
-    v12 = eq v4, v11
-    constrain v4 == v11
-    call f13(Field 53438638232309528389504892708671455233, Field 64323764613183177041862057485226039389, v6, v7)
-    return v6, v7
-}
-acir(inline) fn assert_gt_limbs f13 {
-  b0(v4: Field, v5: Field, v6: Field, v7: Field):
-    v9 = call f14(v4, v6) -> u1
-    v10 = sub v4, v6
-    v12 = sub v10, Field 1
-    v13 = cast v9 as Field
-    v14 = mul v13, Field 340282366920938463463374607431768211456
-    v15 = add v12, v14
-    v16 = sub v5, v7
-    v17 = cast v9 as Field
-    v18 = sub v16, v17
-    call f15(v15)
-    call f15(v18)
-    return
-}
-brillig(inline) fn lte_hint f14 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f10(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-acir(inline) fn assert_max_bit_size f15 {
-  b0(v4: Field):
-    range_check v4 to 128 bits
-    return
-}
-brillig(inline) fn decompose_hint f16 {
-  b0(v4: Field):
-    v6, v7 = call f17(v4) -> (Field, Field)
-    return v6, v7
-}
-brillig(inline) fn compute_decomposition f17 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    store v4 at v5
-    v6 = load v5 -> Field
-    v7 = truncate v6 to 64 bits, max_bit_size: 254
-    v8 = cast v7 as u64
-    v9 = cast v7 as Field
-    v10 = load v5 -> Field
-    v11 = sub v10, v9
-    v12 = div v11, Field 18446744073709551616
-    store v12 at v5
-    v13 = load v5 -> Field
-    v14 = truncate v13 to 64 bits, max_bit_size: 254
-    v15 = cast v14 as u64
-    v16 = cast v14 as Field
-    v17 = load v5 -> Field
-    v18 = sub v17, v16
-    v19 = div v18, Field 18446744073709551616
-    v20 = mul v16, Field 18446744073709551616
-    v21 = add v20, v9
-    return v21, v19
-}
-acir(inline) fn to_be_radix f18 {
-  b0(v4: Field, v5: u32):
-    call assert_constant(v5)
-    v8 = call to_be_radix(v4, v5) -> [u8; 32]
-    return v8
-}
-
-After Inlining (1st):
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v12 = allocate -> &mut Field
-    store Field 0 at v12
-    v14 = allocate -> &mut Field
-    store Field 0 at v14
-    v15 = load v12 -> Field
-    v16 = load v12 -> Field
-    v17 = eq v15, v16
-    jmpif v17 then: b1, else: b10
-  b1():
-    v20 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v50 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v51 = allocate -> &mut u1
-    store u1 0 at v51
-    jmp b2(u32 0)
-  b2(v5: u32):
-    v55 = lt v5, u32 32
-    jmpif v55 then: b28, else: b3
-  b3():
-    v56 = load v51 -> u1
-    constrain v56 == u1 1
-    v58 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v59 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v60 = allocate -> &mut u1
-    store u1 0 at v60
-    jmp b4(u32 0)
-  b4(v6: u32):
-    v61 = lt v6, u32 32
-    jmpif v61 then: b23, else: b5
-  b5():
-    v62 = load v60 -> u1
-    constrain v62 == u1 1
-    v63 = allocate -> &mut [u8; 32]
-    store v58 at v63
-    jmp b6(u32 0)
-  b6(v7: u32):
-    v64 = lt v7, u32 32
-    jmpif v64 then: b22, else: b7
-  b7():
-    v65 = load v63 -> [u8; 32]
-    v66 = allocate -> &mut Field
-    store Field 1 at v66
-    v68 = allocate -> &mut Field
-    store Field 0 at v68
-    v69 = allocate -> &mut Field
-    store Field 0 at v69
-    jmp b8(u32 0)
-  b8(v8: u32):
-    v71 = lt v8, u32 16
-    jmpif v71 then: b21, else: b9
-  b9():
-    v72 = load v69 -> Field
-    v73 = load v68 -> Field
-    v74 = load v66 -> Field
-    v75 = mul v73, v74
-    v76 = add v72, v75
-    store v76 at v14
-    jmp b10()
-  b10():
-    v77 = allocate -> &mut Field
-    store Field 0 at v77
-    jmp b11()
-  b11():
-    v78 = eq v4, Field 0
-    jmpif v78 then: b16, else: b12
-  b12():
-    v80 = call f1(v4, Field 0) -> u1
-    jmpif v80 then: b14, else: b13
-  b13():
-    v82, v83 = call f3(v4) -> (Field, Field)
-    range_check v82 to 128 bits
-    range_check v83 to 128 bits
-    v85 = mul Field 340282366920938463463374607431768211456, v83
-    v86 = add v82, v85
-    v87 = eq v4, v86
-    constrain v4 == v86
-    v90 = call f2(Field 53438638232309528389504892708671455233, v82) -> u1
-    v91 = sub Field 53438638232309528389504892708671455233, v82
-    v92 = sub v91, Field 1
-    v93 = cast v90 as Field
-    v94 = mul v93, Field 340282366920938463463374607431768211456
-    v95 = add v92, v94
-    v97 = sub Field 64323764613183177041862057485226039389, v83
-    v98 = cast v90 as Field
-    v99 = sub v97, v98
-    range_check v95 to 128 bits
-    range_check v99 to 128 bits
-    v101, v102 = call f3(Field 0) -> (Field, Field)
-    range_check v101 to 128 bits
-    range_check v102 to 128 bits
-    v103 = mul Field 340282366920938463463374607431768211456, v102
-    v104 = add v101, v103
-    v105 = eq Field 0, v104
-    constrain Field 0 == v104
-    v107 = call f2(Field 53438638232309528389504892708671455233, v101) -> u1
-    v108 = sub Field 53438638232309528389504892708671455233, v101
-    v109 = sub v108, Field 1
-    v110 = cast v107 as Field
-    v111 = mul v110, Field 340282366920938463463374607431768211456
-    v112 = add v109, v111
-    v113 = sub Field 64323764613183177041862057485226039389, v102
-    v114 = cast v107 as Field
-    v115 = sub v113, v114
-    range_check v112 to 128 bits
-    range_check v115 to 128 bits
-    v117 = call f2(v82, v101) -> u1
-    v118 = sub v82, v101
-    v119 = sub v118, Field 1
-    v120 = cast v117 as Field
-    v121 = mul v120, Field 340282366920938463463374607431768211456
-    v122 = add v119, v121
-    v123 = sub v83, v102
-    v124 = cast v117 as Field
-    v125 = sub v123, v124
-    range_check v122 to 128 bits
-    range_check v125 to 128 bits
-    jmp b15(u1 1)
-  b14():
-    v127, v128 = call f3(Field 0) -> (Field, Field)
-    range_check v127 to 128 bits
-    range_check v128 to 128 bits
-    v129 = mul Field 340282366920938463463374607431768211456, v128
-    v130 = add v127, v129
-    v131 = eq Field 0, v130
-    constrain Field 0 == v130
-    v133 = call f2(Field 53438638232309528389504892708671455233, v127) -> u1
-    v134 = sub Field 53438638232309528389504892708671455233, v127
-    v135 = sub v134, Field 1
-    v136 = cast v133 as Field
-    v137 = mul v136, Field 340282366920938463463374607431768211456
-    v138 = add v135, v137
-    v139 = sub Field 64323764613183177041862057485226039389, v128
-    v140 = cast v133 as Field
-    v141 = sub v139, v140
-    range_check v138 to 128 bits
-    range_check v141 to 128 bits
-    v143, v144 = call f3(v4) -> (Field, Field)
-    range_check v143 to 128 bits
-    range_check v144 to 128 bits
-    v145 = mul Field 340282366920938463463374607431768211456, v144
-    v146 = add v143, v145
-    v147 = eq v4, v146
-    constrain v4 == v146
-    v149 = call f2(Field 53438638232309528389504892708671455233, v143) -> u1
-    v150 = sub Field 53438638232309528389504892708671455233, v143
-    v151 = sub v150, Field 1
-    v152 = cast v149 as Field
-    v153 = mul v152, Field 340282366920938463463374607431768211456
-    v154 = add v151, v153
-    v155 = sub Field 64323764613183177041862057485226039389, v144
-    v156 = cast v149 as Field
-    v157 = sub v155, v156
-    range_check v154 to 128 bits
-    range_check v157 to 128 bits
-    v159 = call f2(v127, v143) -> u1
-    v160 = sub v127, v143
-    v161 = sub v160, Field 1
-    v162 = cast v159 as Field
-    v163 = mul v162, Field 340282366920938463463374607431768211456
-    v164 = add v161, v163
-    v165 = sub v128, v144
-    v166 = cast v159 as Field
-    v167 = sub v165, v166
-    range_check v164 to 128 bits
-    range_check v167 to 128 bits
-    jmp b15(u1 0)
-  b15(v9: u1):
-    jmp b17(v9)
-  b16():
-    jmp b17(u1 0)
-  b17(v10: u1):
-    jmp b18(v10)
-  b18(v11: u1):
-    jmpif v11 then: b19, else: b20
-  b19():
-    store Field 1 at v77
-    jmp b20()
-  b20():
-    v168 = load v77 -> Field
-    v169 = load v14 -> Field
-    v170 = sub v168, v169
-    store v170 at v12
-    v171 = load v12 -> Field
-    return v171
-  b21():
-    v172 = load v68 -> Field
-    v174 = sub u32 15, v8
-    v175 = array_get v65, index v174 -> u8
-    v176 = cast v175 as Field
-    v177 = load v66 -> Field
-    v178 = mul v176, v177
-    v179 = add v172, v178
-    store v179 at v68
-    v180 = load v69 -> Field
-    v182 = sub u32 31, v8
-    v183 = array_get v65, index v182 -> u8
-    v184 = cast v183 as Field
-    v185 = load v66 -> Field
-    v186 = mul v184, v185
-    v187 = add v180, v186
-    store v187 at v69
-    v188 = load v66 -> Field
-    v190 = mul v188, Field 256
-    store v190 at v66
-    v192 = unchecked_add v8, u32 1
-    jmp b8(v192)
-  b22():
-    v193 = load v63 -> [u8; 32]
-    v194 = array_get v20, index v7 -> u8
-    v195 = load v63 -> [u8; 32]
-    v196 = array_get v195, index v7 -> u8
-    v197 = xor v194, v196
-    v198 = array_set v193, index v7, value v197
-    v199 = unchecked_add v7, u32 1
-    store v198 at v63
-    v200 = unchecked_add v7, u32 1
-    jmp b6(v200)
-  b23():
-    v201 = load v60 -> u1
-    v202 = not v201
-    jmpif v202 then: b24, else: b27
-  b24():
-    v203 = array_get v58, index v6 -> u8
-    v204 = lt v6, u32 32
-    constrain v204 == u1 1, "Index out of bounds"
-    v205 = array_get v59, index v6 -> u8
-    v206 = eq v203, v205
-    v207 = not v206
-    jmpif v207 then: b25, else: b26
-  b25():
-    v208 = array_get v58, index v6 -> u8
-    v209 = lt v6, u32 32
-    constrain v209 == u1 1, "Index out of bounds"
-    v210 = array_get v59, index v6 -> u8
-    v211 = lt v208, v210
-    constrain v211 == u1 1
-    store u1 1 at v60
-    jmp b26()
-  b26():
-    jmp b27()
-  b27():
-    v212 = unchecked_add v6, u32 1
-    jmp b4(v212)
-  b28():
-    v213 = load v51 -> u1
-    v214 = not v213
-    jmpif v214 then: b29, else: b32
-  b29():
-    v215 = array_get v20, index v5 -> u8
-    v216 = lt v5, u32 32
-    constrain v216 == u1 1, "Index out of bounds"
-    v217 = array_get v50, index v5 -> u8
-    v218 = eq v215, v217
-    v219 = not v218
-    jmpif v219 then: b30, else: b31
-  b30():
-    v220 = array_get v20, index v5 -> u8
-    v221 = lt v5, u32 32
-    constrain v221 == u1 1, "Index out of bounds"
-    v222 = array_get v50, index v5 -> u8
-    v223 = lt v220, v222
-    constrain v223 == u1 1
-    store u1 1 at v51
-    jmp b31()
-  b31():
-    jmp b32()
-  b32():
-    v224 = unchecked_add v5, u32 1
-    jmp b2(v224)
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    store v4 at v5
-    v6 = load v5 -> Field
-    v7 = truncate v6 to 64 bits, max_bit_size: 254
-    v8 = cast v7 as u64
-    v9 = load v5 -> Field
-    v10 = sub v9, v7
-    v11 = div v10, Field 18446744073709551616
-    store v11 at v5
-    v12 = load v5 -> Field
-    v13 = truncate v12 to 64 bits, max_bit_size: 254
-    v14 = cast v13 as u64
-    v15 = load v5 -> Field
-    v16 = sub v15, v13
-    v17 = div v16, Field 18446744073709551616
-    v18 = mul v13, Field 18446744073709551616
-    v19 = add v18, v7
-    return v19, v17
-}
-
-After Mem2Reg (1st):
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v12 = allocate -> &mut Field
-    v13 = allocate -> &mut Field
-    store Field 0 at v13
-    jmpif u1 1 then: b1, else: b10
-  b1():
-    v18 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v48 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v49 = allocate -> &mut u1
-    store u1 0 at v49
-    jmp b2(u32 0)
-  b2(v5: u32):
-    v53 = lt v5, u32 32
-    jmpif v53 then: b28, else: b3
-  b3():
-    v54 = load v49 -> u1
-    constrain v54 == u1 1
-    v55 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v56 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v57 = allocate -> &mut u1
-    store u1 0 at v57
-    jmp b4(u32 0)
-  b4(v6: u32):
-    v58 = lt v6, u32 32
-    jmpif v58 then: b23, else: b5
-  b5():
-    v59 = load v57 -> u1
-    constrain v59 == u1 1
-    v60 = allocate -> &mut [u8; 32]
-    store v55 at v60
-    jmp b6(u32 0)
-  b6(v7: u32):
-    v61 = lt v7, u32 32
-    jmpif v61 then: b22, else: b7
-  b7():
-    v62 = load v60 -> [u8; 32]
-    v63 = allocate -> &mut Field
-    store Field 1 at v63
-    v65 = allocate -> &mut Field
-    store Field 0 at v65
-    v66 = allocate -> &mut Field
-    store Field 0 at v66
-    jmp b8(u32 0)
-  b8(v8: u32):
-    v68 = lt v8, u32 16
-    jmpif v68 then: b21, else: b9
-  b9():
-    v69 = load v66 -> Field
-    v70 = load v65 -> Field
-    v71 = load v63 -> Field
-    v72 = mul v70, v71
-    v73 = add v69, v72
-    store v73 at v13
-    jmp b10()
-  b10():
-    v74 = allocate -> &mut Field
-    store Field 0 at v74
-    jmp b11()
-  b11():
-    v75 = eq v4, Field 0
-    jmpif v75 then: b16, else: b12
-  b12():
-    v77 = call f1(v4, Field 0) -> u1
-    jmpif v77 then: b14, else: b13
-  b13():
-    v79, v80 = call f3(v4) -> (Field, Field)
-    range_check v79 to 128 bits
-    range_check v80 to 128 bits
-    v82 = mul Field 340282366920938463463374607431768211456, v80
-    v83 = add v79, v82
-    v84 = eq v4, v83
-    constrain v4 == v83
-    v87 = call f2(Field 53438638232309528389504892708671455233, v79) -> u1
-    v88 = sub Field 53438638232309528389504892708671455233, v79
-    v89 = sub v88, Field 1
-    v90 = cast v87 as Field
-    v91 = mul v90, Field 340282366920938463463374607431768211456
-    v92 = add v89, v91
-    v94 = sub Field 64323764613183177041862057485226039389, v80
-    v95 = cast v87 as Field
-    v96 = sub v94, v95
-    range_check v92 to 128 bits
-    range_check v96 to 128 bits
-    v98, v99 = call f3(Field 0) -> (Field, Field)
-    range_check v98 to 128 bits
-    range_check v99 to 128 bits
-    v100 = mul Field 340282366920938463463374607431768211456, v99
-    v101 = add v98, v100
-    v102 = eq Field 0, v101
-    constrain Field 0 == v101
-    v104 = call f2(Field 53438638232309528389504892708671455233, v98) -> u1
-    v105 = sub Field 53438638232309528389504892708671455233, v98
-    v106 = sub v105, Field 1
-    v107 = cast v104 as Field
-    v108 = mul v107, Field 340282366920938463463374607431768211456
-    v109 = add v106, v108
-    v110 = sub Field 64323764613183177041862057485226039389, v99
-    v111 = cast v104 as Field
-    v112 = sub v110, v111
-    range_check v109 to 128 bits
-    range_check v112 to 128 bits
-    v114 = call f2(v79, v98) -> u1
-    v115 = sub v79, v98
-    v116 = sub v115, Field 1
-    v117 = cast v114 as Field
-    v118 = mul v117, Field 340282366920938463463374607431768211456
-    v119 = add v116, v118
-    v120 = sub v80, v99
-    v121 = cast v114 as Field
-    v122 = sub v120, v121
-    range_check v119 to 128 bits
-    range_check v122 to 128 bits
-    jmp b15(u1 1)
-  b14():
-    v124, v125 = call f3(Field 0) -> (Field, Field)
-    range_check v124 to 128 bits
-    range_check v125 to 128 bits
-    v126 = mul Field 340282366920938463463374607431768211456, v125
-    v127 = add v124, v126
-    v128 = eq Field 0, v127
-    constrain Field 0 == v127
-    v130 = call f2(Field 53438638232309528389504892708671455233, v124) -> u1
-    v131 = sub Field 53438638232309528389504892708671455233, v124
-    v132 = sub v131, Field 1
-    v133 = cast v130 as Field
-    v134 = mul v133, Field 340282366920938463463374607431768211456
-    v135 = add v132, v134
-    v136 = sub Field 64323764613183177041862057485226039389, v125
-    v137 = cast v130 as Field
-    v138 = sub v136, v137
-    range_check v135 to 128 bits
-    range_check v138 to 128 bits
-    v140, v141 = call f3(v4) -> (Field, Field)
-    range_check v140 to 128 bits
-    range_check v141 to 128 bits
-    v142 = mul Field 340282366920938463463374607431768211456, v141
-    v143 = add v140, v142
-    v144 = eq v4, v143
-    constrain v4 == v143
-    v146 = call f2(Field 53438638232309528389504892708671455233, v140) -> u1
-    v147 = sub Field 53438638232309528389504892708671455233, v140
-    v148 = sub v147, Field 1
-    v149 = cast v146 as Field
-    v150 = mul v149, Field 340282366920938463463374607431768211456
-    v151 = add v148, v150
-    v152 = sub Field 64323764613183177041862057485226039389, v141
-    v153 = cast v146 as Field
-    v154 = sub v152, v153
-    range_check v151 to 128 bits
-    range_check v154 to 128 bits
-    v156 = call f2(v124, v140) -> u1
-    v157 = sub v124, v140
-    v158 = sub v157, Field 1
-    v159 = cast v156 as Field
-    v160 = mul v159, Field 340282366920938463463374607431768211456
-    v161 = add v158, v160
-    v162 = sub v125, v141
-    v163 = cast v156 as Field
-    v164 = sub v162, v163
-    range_check v161 to 128 bits
-    range_check v164 to 128 bits
-    jmp b15(u1 0)
-  b15(v9: u1):
-    jmp b17(v9)
-  b16():
-    jmp b17(u1 0)
-  b17(v10: u1):
-    jmp b18(v10)
-  b18(v11: u1):
-    jmpif v11 then: b19, else: b20
-  b19():
-    store Field 1 at v74
-    jmp b20()
-  b20():
-    v165 = load v74 -> Field
-    v166 = load v13 -> Field
-    v167 = sub v165, v166
-    return v167
-  b21():
-    v168 = load v65 -> Field
-    v170 = sub u32 15, v8
-    v171 = array_get v62, index v170 -> u8
-    v172 = cast v171 as Field
-    v173 = load v63 -> Field
-    v174 = mul v172, v173
-    v175 = add v168, v174
-    store v175 at v65
-    v176 = load v66 -> Field
-    v178 = sub u32 31, v8
-    v179 = array_get v62, index v178 -> u8
-    v180 = cast v179 as Field
-    v181 = mul v180, v173
-    v182 = add v176, v181
-    store v182 at v66
-    v184 = mul v173, Field 256
-    store v184 at v63
-    v186 = unchecked_add v8, u32 1
-    jmp b8(v186)
-  b22():
-    v187 = load v60 -> [u8; 32]
-    v188 = array_get v18, index v7 -> u8
-    v189 = array_get v187, index v7 -> u8
-    v190 = xor v188, v189
-    v191 = array_set v187, index v7, value v190
-    v192 = unchecked_add v7, u32 1
-    store v191 at v60
-    v193 = unchecked_add v7, u32 1
-    jmp b6(v193)
-  b23():
-    v194 = load v57 -> u1
-    v195 = not v194
-    jmpif v195 then: b24, else: b27
-  b24():
-    v196 = array_get v55, index v6 -> u8
-    v197 = lt v6, u32 32
-    constrain v197 == u1 1, "Index out of bounds"
-    v198 = array_get v56, index v6 -> u8
-    v199 = eq v196, v198
-    v200 = not v199
-    jmpif v200 then: b25, else: b26
-  b25():
-    v201 = array_get v55, index v6 -> u8
-    v202 = lt v6, u32 32
-    constrain v202 == u1 1, "Index out of bounds"
-    v203 = array_get v56, index v6 -> u8
-    v204 = lt v201, v203
-    constrain v204 == u1 1
-    store u1 1 at v57
-    jmp b26()
-  b26():
-    jmp b27()
-  b27():
-    v205 = unchecked_add v6, u32 1
-    jmp b4(v205)
-  b28():
-    v206 = load v49 -> u1
-    v207 = not v206
-    jmpif v207 then: b29, else: b32
-  b29():
-    v208 = array_get v18, index v5 -> u8
-    v209 = lt v5, u32 32
-    constrain v209 == u1 1, "Index out of bounds"
-    v210 = array_get v48, index v5 -> u8
-    v211 = eq v208, v210
-    v212 = not v211
-    jmpif v212 then: b30, else: b31
-  b30():
-    v213 = array_get v18, index v5 -> u8
-    v214 = lt v5, u32 32
-    constrain v214 == u1 1, "Index out of bounds"
-    v215 = array_get v48, index v5 -> u8
-    v216 = lt v213, v215
-    constrain v216 == u1 1
-    store u1 1 at v49
-    jmp b31()
-  b31():
-    jmp b32()
-  b32():
-    v217 = unchecked_add v5, u32 1
-    jmp b2(v217)
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Simplifying (1st):
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v11 = allocate -> &mut Field
-    v12 = allocate -> &mut Field
-    store Field 0 at v12
-    v16 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v46 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v47 = allocate -> &mut u1
-    store u1 0 at v47
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v51 = lt v5, u32 32
-    jmpif v51 then: b24, else: b2
-  b2():
-    v52 = load v47 -> u1
-    constrain v52 == u1 1
-    v54 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v55 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v56 = allocate -> &mut u1
-    store u1 0 at v56
-    jmp b3(u32 0)
-  b3(v6: u32):
-    v57 = lt v6, u32 32
-    jmpif v57 then: b19, else: b4
-  b4():
-    v58 = load v56 -> u1
-    constrain v58 == u1 1
-    v59 = allocate -> &mut [u8; 32]
-    store v54 at v59
-    jmp b5(u32 0)
-  b5(v7: u32):
-    v60 = lt v7, u32 32
-    jmpif v60 then: b18, else: b6
-  b6():
-    v61 = load v59 -> [u8; 32]
-    v62 = allocate -> &mut Field
-    store Field 1 at v62
-    v64 = allocate -> &mut Field
-    store Field 0 at v64
-    v65 = allocate -> &mut Field
-    store Field 0 at v65
-    jmp b7(u32 0)
-  b7(v8: u32):
-    v67 = lt v8, u32 16
-    jmpif v67 then: b17, else: b8
-  b8():
-    v68 = load v65 -> Field
-    v69 = load v64 -> Field
-    v70 = load v62 -> Field
-    v71 = mul v69, v70
-    v72 = add v68, v71
-    store v72 at v12
-    v73 = allocate -> &mut Field
-    store Field 0 at v73
-    v74 = eq v4, Field 0
-    jmpif v74 then: b13, else: b9
-  b9():
-    v76 = call f1(v4, Field 0) -> u1
-    jmpif v76 then: b11, else: b10
-  b10():
-    v78, v79 = call f3(v4) -> (Field, Field)
-    range_check v78 to 128 bits
-    range_check v79 to 128 bits
-    v81 = mul Field 340282366920938463463374607431768211456, v79
-    v82 = add v78, v81
-    v83 = eq v4, v82
-    constrain v4 == v82
-    v86 = call f2(Field 53438638232309528389504892708671455233, v78) -> u1
-    v87 = sub Field 53438638232309528389504892708671455233, v78
-    v88 = sub v87, Field 1
-    v89 = cast v86 as Field
-    v90 = mul v89, Field 340282366920938463463374607431768211456
-    v91 = add v88, v90
-    v93 = sub Field 64323764613183177041862057485226039389, v79
-    v94 = cast v86 as Field
-    v95 = sub v93, v94
-    range_check v91 to 128 bits
-    range_check v95 to 128 bits
-    v97, v98 = call f3(Field 0) -> (Field, Field)
-    range_check v97 to 128 bits
-    range_check v98 to 128 bits
-    v99 = mul Field 340282366920938463463374607431768211456, v98
-    v100 = add v97, v99
-    v101 = eq Field 0, v100
-    constrain Field 0 == v100
-    v103 = call f2(Field 53438638232309528389504892708671455233, v97) -> u1
-    v104 = sub Field 53438638232309528389504892708671455233, v97
-    v105 = sub v104, Field 1
-    v106 = cast v103 as Field
-    v107 = mul v106, Field 340282366920938463463374607431768211456
-    v108 = add v105, v107
-    v109 = sub Field 64323764613183177041862057485226039389, v98
-    v110 = cast v103 as Field
-    v111 = sub v109, v110
-    range_check v108 to 128 bits
-    range_check v111 to 128 bits
-    v113 = call f2(v78, v97) -> u1
-    v114 = sub v78, v97
-    v115 = sub v114, Field 1
-    v116 = cast v113 as Field
-    v117 = mul v116, Field 340282366920938463463374607431768211456
-    v118 = add v115, v117
-    v119 = sub v79, v98
-    v120 = cast v113 as Field
-    v121 = sub v119, v120
-    range_check v118 to 128 bits
-    range_check v121 to 128 bits
-    jmp b12(u1 1)
-  b11():
-    v123, v124 = call f3(Field 0) -> (Field, Field)
-    range_check v123 to 128 bits
-    range_check v124 to 128 bits
-    v125 = mul Field 340282366920938463463374607431768211456, v124
-    v126 = add v123, v125
-    v127 = eq Field 0, v126
-    constrain Field 0 == v126
-    v129 = call f2(Field 53438638232309528389504892708671455233, v123) -> u1
-    v130 = sub Field 53438638232309528389504892708671455233, v123
-    v131 = sub v130, Field 1
-    v132 = cast v129 as Field
-    v133 = mul v132, Field 340282366920938463463374607431768211456
-    v134 = add v131, v133
-    v135 = sub Field 64323764613183177041862057485226039389, v124
-    v136 = cast v129 as Field
-    v137 = sub v135, v136
-    range_check v134 to 128 bits
-    range_check v137 to 128 bits
-    v139, v140 = call f3(v4) -> (Field, Field)
-    range_check v139 to 128 bits
-    range_check v140 to 128 bits
-    v141 = mul Field 340282366920938463463374607431768211456, v140
-    v142 = add v139, v141
-    v143 = eq v4, v142
-    constrain v4 == v142
-    v145 = call f2(Field 53438638232309528389504892708671455233, v139) -> u1
-    v146 = sub Field 53438638232309528389504892708671455233, v139
-    v147 = sub v146, Field 1
-    v148 = cast v145 as Field
-    v149 = mul v148, Field 340282366920938463463374607431768211456
-    v150 = add v147, v149
-    v151 = sub Field 64323764613183177041862057485226039389, v140
-    v152 = cast v145 as Field
-    v153 = sub v151, v152
-    range_check v150 to 128 bits
-    range_check v153 to 128 bits
-    v155 = call f2(v123, v139) -> u1
-    v156 = sub v123, v139
-    v157 = sub v156, Field 1
-    v158 = cast v155 as Field
-    v159 = mul v158, Field 340282366920938463463374607431768211456
-    v160 = add v157, v159
-    v161 = sub v124, v140
-    v162 = cast v155 as Field
-    v163 = sub v161, v162
-    range_check v160 to 128 bits
-    range_check v163 to 128 bits
-    jmp b12(u1 0)
-  b12(v9: u1):
-    jmp b14(v9)
-  b13():
-    jmp b14(u1 0)
-  b14(v10: u1):
-    jmpif v10 then: b15, else: b16
-  b15():
-    store Field 1 at v73
-    jmp b16()
-  b16():
-    v164 = load v73 -> Field
-    v165 = load v12 -> Field
-    v166 = sub v164, v165
-    return v166
-  b17():
-    v167 = load v64 -> Field
-    v169 = sub u32 15, v8
-    v170 = array_get v61, index v169 -> u8
-    v171 = cast v170 as Field
-    v172 = load v62 -> Field
-    v173 = mul v171, v172
-    v174 = add v167, v173
-    store v174 at v64
-    v175 = load v65 -> Field
-    v177 = sub u32 31, v8
-    v178 = array_get v61, index v177 -> u8
-    v179 = cast v178 as Field
-    v180 = mul v179, v172
-    v181 = add v175, v180
-    store v181 at v65
-    v183 = mul v172, Field 256
-    store v183 at v62
-    v185 = unchecked_add v8, u32 1
-    jmp b7(v185)
-  b18():
-    v186 = load v59 -> [u8; 32]
-    v187 = array_get v16, index v7 -> u8
-    v188 = array_get v186, index v7 -> u8
-    v189 = xor v187, v188
-    v190 = array_set v186, index v7, value v189
-    v191 = unchecked_add v7, u32 1
-    store v190 at v59
-    v192 = unchecked_add v7, u32 1
-    jmp b5(v192)
-  b19():
-    v193 = load v56 -> u1
-    v194 = not v193
-    jmpif v194 then: b20, else: b23
-  b20():
-    v195 = array_get v54, index v6 -> u8
-    v196 = lt v6, u32 32
-    constrain v196 == u1 1, "Index out of bounds"
-    v197 = array_get v55, index v6 -> u8
-    v198 = eq v195, v197
-    v199 = not v198
-    jmpif v199 then: b21, else: b22
-  b21():
-    v200 = array_get v54, index v6 -> u8
-    v201 = lt v6, u32 32
-    constrain v201 == u1 1, "Index out of bounds"
-    v202 = array_get v55, index v6 -> u8
-    v203 = lt v200, v202
-    constrain v203 == u1 1
-    store u1 1 at v56
-    jmp b22()
-  b22():
-    jmp b23()
-  b23():
-    v204 = unchecked_add v6, u32 1
-    jmp b3(v204)
-  b24():
-    v205 = load v47 -> u1
-    v206 = not v205
-    jmpif v206 then: b25, else: b28
-  b25():
-    v207 = array_get v16, index v5 -> u8
-    v208 = lt v5, u32 32
-    constrain v208 == u1 1, "Index out of bounds"
-    v209 = array_get v46, index v5 -> u8
-    v210 = eq v207, v209
-    v211 = not v210
-    jmpif v211 then: b26, else: b27
-  b26():
-    v212 = array_get v16, index v5 -> u8
-    v213 = lt v5, u32 32
-    constrain v213 == u1 1, "Index out of bounds"
-    v214 = array_get v46, index v5 -> u8
-    v215 = lt v212, v214
-    constrain v215 == u1 1
-    store u1 1 at v47
-    jmp b27()
-  b27():
-    jmp b28()
-  b28():
-    v216 = unchecked_add v5, u32 1
-    jmp b1(v216)
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After `as_slice` optimization:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v11 = allocate -> &mut Field
-    v12 = allocate -> &mut Field
-    store Field 0 at v12
-    v16 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v46 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v47 = allocate -> &mut u1
-    store u1 0 at v47
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v51 = lt v5, u32 32
-    jmpif v51 then: b24, else: b2
-  b2():
-    v52 = load v47 -> u1
-    constrain v52 == u1 1
-    v54 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v55 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v56 = allocate -> &mut u1
-    store u1 0 at v56
-    jmp b3(u32 0)
-  b3(v6: u32):
-    v57 = lt v6, u32 32
-    jmpif v57 then: b19, else: b4
-  b4():
-    v58 = load v56 -> u1
-    constrain v58 == u1 1
-    v59 = allocate -> &mut [u8; 32]
-    store v54 at v59
-    jmp b5(u32 0)
-  b5(v7: u32):
-    v60 = lt v7, u32 32
-    jmpif v60 then: b18, else: b6
-  b6():
-    v61 = load v59 -> [u8; 32]
-    v62 = allocate -> &mut Field
-    store Field 1 at v62
-    v64 = allocate -> &mut Field
-    store Field 0 at v64
-    v65 = allocate -> &mut Field
-    store Field 0 at v65
-    jmp b7(u32 0)
-  b7(v8: u32):
-    v67 = lt v8, u32 16
-    jmpif v67 then: b17, else: b8
-  b8():
-    v68 = load v65 -> Field
-    v69 = load v64 -> Field
-    v70 = load v62 -> Field
-    v71 = mul v69, v70
-    v72 = add v68, v71
-    store v72 at v12
-    v73 = allocate -> &mut Field
-    store Field 0 at v73
-    v74 = eq v4, Field 0
-    jmpif v74 then: b13, else: b9
-  b9():
-    v76 = call f1(v4, Field 0) -> u1
-    jmpif v76 then: b11, else: b10
-  b10():
-    v78, v79 = call f3(v4) -> (Field, Field)
-    range_check v78 to 128 bits
-    range_check v79 to 128 bits
-    v81 = mul Field 340282366920938463463374607431768211456, v79
-    v82 = add v78, v81
-    v83 = eq v4, v82
-    constrain v4 == v82
-    v86 = call f2(Field 53438638232309528389504892708671455233, v78) -> u1
-    v87 = sub Field 53438638232309528389504892708671455233, v78
-    v88 = sub v87, Field 1
-    v89 = cast v86 as Field
-    v90 = mul v89, Field 340282366920938463463374607431768211456
-    v91 = add v88, v90
-    v93 = sub Field 64323764613183177041862057485226039389, v79
-    v94 = cast v86 as Field
-    v95 = sub v93, v94
-    range_check v91 to 128 bits
-    range_check v95 to 128 bits
-    v97, v98 = call f3(Field 0) -> (Field, Field)
-    range_check v97 to 128 bits
-    range_check v98 to 128 bits
-    v99 = mul Field 340282366920938463463374607431768211456, v98
-    v100 = add v97, v99
-    v101 = eq Field 0, v100
-    constrain Field 0 == v100
-    v103 = call f2(Field 53438638232309528389504892708671455233, v97) -> u1
-    v104 = sub Field 53438638232309528389504892708671455233, v97
-    v105 = sub v104, Field 1
-    v106 = cast v103 as Field
-    v107 = mul v106, Field 340282366920938463463374607431768211456
-    v108 = add v105, v107
-    v109 = sub Field 64323764613183177041862057485226039389, v98
-    v110 = cast v103 as Field
-    v111 = sub v109, v110
-    range_check v108 to 128 bits
-    range_check v111 to 128 bits
-    v113 = call f2(v78, v97) -> u1
-    v114 = sub v78, v97
-    v115 = sub v114, Field 1
-    v116 = cast v113 as Field
-    v117 = mul v116, Field 340282366920938463463374607431768211456
-    v118 = add v115, v117
-    v119 = sub v79, v98
-    v120 = cast v113 as Field
-    v121 = sub v119, v120
-    range_check v118 to 128 bits
-    range_check v121 to 128 bits
-    jmp b12(u1 1)
-  b11():
-    v123, v124 = call f3(Field 0) -> (Field, Field)
-    range_check v123 to 128 bits
-    range_check v124 to 128 bits
-    v125 = mul Field 340282366920938463463374607431768211456, v124
-    v126 = add v123, v125
-    v127 = eq Field 0, v126
-    constrain Field 0 == v126
-    v129 = call f2(Field 53438638232309528389504892708671455233, v123) -> u1
-    v130 = sub Field 53438638232309528389504892708671455233, v123
-    v131 = sub v130, Field 1
-    v132 = cast v129 as Field
-    v133 = mul v132, Field 340282366920938463463374607431768211456
-    v134 = add v131, v133
-    v135 = sub Field 64323764613183177041862057485226039389, v124
-    v136 = cast v129 as Field
-    v137 = sub v135, v136
-    range_check v134 to 128 bits
-    range_check v137 to 128 bits
-    v139, v140 = call f3(v4) -> (Field, Field)
-    range_check v139 to 128 bits
-    range_check v140 to 128 bits
-    v141 = mul Field 340282366920938463463374607431768211456, v140
-    v142 = add v139, v141
-    v143 = eq v4, v142
-    constrain v4 == v142
-    v145 = call f2(Field 53438638232309528389504892708671455233, v139) -> u1
-    v146 = sub Field 53438638232309528389504892708671455233, v139
-    v147 = sub v146, Field 1
-    v148 = cast v145 as Field
-    v149 = mul v148, Field 340282366920938463463374607431768211456
-    v150 = add v147, v149
-    v151 = sub Field 64323764613183177041862057485226039389, v140
-    v152 = cast v145 as Field
-    v153 = sub v151, v152
-    range_check v150 to 128 bits
-    range_check v153 to 128 bits
-    v155 = call f2(v123, v139) -> u1
-    v156 = sub v123, v139
-    v157 = sub v156, Field 1
-    v158 = cast v155 as Field
-    v159 = mul v158, Field 340282366920938463463374607431768211456
-    v160 = add v157, v159
-    v161 = sub v124, v140
-    v162 = cast v155 as Field
-    v163 = sub v161, v162
-    range_check v160 to 128 bits
-    range_check v163 to 128 bits
-    jmp b12(u1 0)
-  b12(v9: u1):
-    jmp b14(v9)
-  b13():
-    jmp b14(u1 0)
-  b14(v10: u1):
-    jmpif v10 then: b15, else: b16
-  b15():
-    store Field 1 at v73
-    jmp b16()
-  b16():
-    v164 = load v73 -> Field
-    v165 = load v12 -> Field
-    v166 = sub v164, v165
-    return v166
-  b17():
-    v167 = load v64 -> Field
-    v169 = sub u32 15, v8
-    v170 = array_get v61, index v169 -> u8
-    v171 = cast v170 as Field
-    v172 = load v62 -> Field
-    v173 = mul v171, v172
-    v174 = add v167, v173
-    store v174 at v64
-    v175 = load v65 -> Field
-    v177 = sub u32 31, v8
-    v178 = array_get v61, index v177 -> u8
-    v179 = cast v178 as Field
-    v180 = mul v179, v172
-    v181 = add v175, v180
-    store v181 at v65
-    v183 = mul v172, Field 256
-    store v183 at v62
-    v185 = unchecked_add v8, u32 1
-    jmp b7(v185)
-  b18():
-    v186 = load v59 -> [u8; 32]
-    v187 = array_get v16, index v7 -> u8
-    v188 = array_get v186, index v7 -> u8
-    v189 = xor v187, v188
-    v190 = array_set v186, index v7, value v189
-    v191 = unchecked_add v7, u32 1
-    store v190 at v59
-    v192 = unchecked_add v7, u32 1
-    jmp b5(v192)
-  b19():
-    v193 = load v56 -> u1
-    v194 = not v193
-    jmpif v194 then: b20, else: b23
-  b20():
-    v195 = array_get v54, index v6 -> u8
-    v196 = lt v6, u32 32
-    constrain v196 == u1 1, "Index out of bounds"
-    v197 = array_get v55, index v6 -> u8
-    v198 = eq v195, v197
-    v199 = not v198
-    jmpif v199 then: b21, else: b22
-  b21():
-    v200 = array_get v54, index v6 -> u8
-    v201 = lt v6, u32 32
-    constrain v201 == u1 1, "Index out of bounds"
-    v202 = array_get v55, index v6 -> u8
-    v203 = lt v200, v202
-    constrain v203 == u1 1
-    store u1 1 at v56
-    jmp b22()
-  b22():
-    jmp b23()
-  b23():
-    v204 = unchecked_add v6, u32 1
-    jmp b3(v204)
-  b24():
-    v205 = load v47 -> u1
-    v206 = not v205
-    jmpif v206 then: b25, else: b28
-  b25():
-    v207 = array_get v16, index v5 -> u8
-    v208 = lt v5, u32 32
-    constrain v208 == u1 1, "Index out of bounds"
-    v209 = array_get v46, index v5 -> u8
-    v210 = eq v207, v209
-    v211 = not v210
-    jmpif v211 then: b26, else: b27
-  b26():
-    v212 = array_get v16, index v5 -> u8
-    v213 = lt v5, u32 32
-    constrain v213 == u1 1, "Index out of bounds"
-    v214 = array_get v46, index v5 -> u8
-    v215 = lt v212, v214
-    constrain v215 == u1 1
-    store u1 1 at v47
-    jmp b27()
-  b27():
-    jmp b28()
-  b28():
-    v216 = unchecked_add v5, u32 1
-    jmp b1(v216)
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Removing Unreachable Functions:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v11 = allocate -> &mut Field
-    v12 = allocate -> &mut Field
-    store Field 0 at v12
-    v16 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v46 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v47 = allocate -> &mut u1
-    store u1 0 at v47
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v51 = lt v5, u32 32
-    jmpif v51 then: b24, else: b2
-  b2():
-    v52 = load v47 -> u1
-    constrain v52 == u1 1
-    v54 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v55 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v56 = allocate -> &mut u1
-    store u1 0 at v56
-    jmp b3(u32 0)
-  b3(v6: u32):
-    v57 = lt v6, u32 32
-    jmpif v57 then: b19, else: b4
-  b4():
-    v58 = load v56 -> u1
-    constrain v58 == u1 1
-    v59 = allocate -> &mut [u8; 32]
-    store v54 at v59
-    jmp b5(u32 0)
-  b5(v7: u32):
-    v60 = lt v7, u32 32
-    jmpif v60 then: b18, else: b6
-  b6():
-    v61 = load v59 -> [u8; 32]
-    v62 = allocate -> &mut Field
-    store Field 1 at v62
-    v64 = allocate -> &mut Field
-    store Field 0 at v64
-    v65 = allocate -> &mut Field
-    store Field 0 at v65
-    jmp b7(u32 0)
-  b7(v8: u32):
-    v67 = lt v8, u32 16
-    jmpif v67 then: b17, else: b8
-  b8():
-    v68 = load v65 -> Field
-    v69 = load v64 -> Field
-    v70 = load v62 -> Field
-    v71 = mul v69, v70
-    v72 = add v68, v71
-    store v72 at v12
-    v73 = allocate -> &mut Field
-    store Field 0 at v73
-    v74 = eq v4, Field 0
-    jmpif v74 then: b13, else: b9
-  b9():
-    v76 = call f1(v4, Field 0) -> u1
-    jmpif v76 then: b11, else: b10
-  b10():
-    v78, v79 = call f3(v4) -> (Field, Field)
-    range_check v78 to 128 bits
-    range_check v79 to 128 bits
-    v81 = mul Field 340282366920938463463374607431768211456, v79
-    v82 = add v78, v81
-    v83 = eq v4, v82
-    constrain v4 == v82
-    v86 = call f2(Field 53438638232309528389504892708671455233, v78) -> u1
-    v87 = sub Field 53438638232309528389504892708671455233, v78
-    v88 = sub v87, Field 1
-    v89 = cast v86 as Field
-    v90 = mul v89, Field 340282366920938463463374607431768211456
-    v91 = add v88, v90
-    v93 = sub Field 64323764613183177041862057485226039389, v79
-    v94 = cast v86 as Field
-    v95 = sub v93, v94
-    range_check v91 to 128 bits
-    range_check v95 to 128 bits
-    v97, v98 = call f3(Field 0) -> (Field, Field)
-    range_check v97 to 128 bits
-    range_check v98 to 128 bits
-    v99 = mul Field 340282366920938463463374607431768211456, v98
-    v100 = add v97, v99
-    v101 = eq Field 0, v100
-    constrain Field 0 == v100
-    v103 = call f2(Field 53438638232309528389504892708671455233, v97) -> u1
-    v104 = sub Field 53438638232309528389504892708671455233, v97
-    v105 = sub v104, Field 1
-    v106 = cast v103 as Field
-    v107 = mul v106, Field 340282366920938463463374607431768211456
-    v108 = add v105, v107
-    v109 = sub Field 64323764613183177041862057485226039389, v98
-    v110 = cast v103 as Field
-    v111 = sub v109, v110
-    range_check v108 to 128 bits
-    range_check v111 to 128 bits
-    v113 = call f2(v78, v97) -> u1
-    v114 = sub v78, v97
-    v115 = sub v114, Field 1
-    v116 = cast v113 as Field
-    v117 = mul v116, Field 340282366920938463463374607431768211456
-    v118 = add v115, v117
-    v119 = sub v79, v98
-    v120 = cast v113 as Field
-    v121 = sub v119, v120
-    range_check v118 to 128 bits
-    range_check v121 to 128 bits
-    jmp b12(u1 1)
-  b11():
-    v123, v124 = call f3(Field 0) -> (Field, Field)
-    range_check v123 to 128 bits
-    range_check v124 to 128 bits
-    v125 = mul Field 340282366920938463463374607431768211456, v124
-    v126 = add v123, v125
-    v127 = eq Field 0, v126
-    constrain Field 0 == v126
-    v129 = call f2(Field 53438638232309528389504892708671455233, v123) -> u1
-    v130 = sub Field 53438638232309528389504892708671455233, v123
-    v131 = sub v130, Field 1
-    v132 = cast v129 as Field
-    v133 = mul v132, Field 340282366920938463463374607431768211456
-    v134 = add v131, v133
-    v135 = sub Field 64323764613183177041862057485226039389, v124
-    v136 = cast v129 as Field
-    v137 = sub v135, v136
-    range_check v134 to 128 bits
-    range_check v137 to 128 bits
-    v139, v140 = call f3(v4) -> (Field, Field)
-    range_check v139 to 128 bits
-    range_check v140 to 128 bits
-    v141 = mul Field 340282366920938463463374607431768211456, v140
-    v142 = add v139, v141
-    v143 = eq v4, v142
-    constrain v4 == v142
-    v145 = call f2(Field 53438638232309528389504892708671455233, v139) -> u1
-    v146 = sub Field 53438638232309528389504892708671455233, v139
-    v147 = sub v146, Field 1
-    v148 = cast v145 as Field
-    v149 = mul v148, Field 340282366920938463463374607431768211456
-    v150 = add v147, v149
-    v151 = sub Field 64323764613183177041862057485226039389, v140
-    v152 = cast v145 as Field
-    v153 = sub v151, v152
-    range_check v150 to 128 bits
-    range_check v153 to 128 bits
-    v155 = call f2(v123, v139) -> u1
-    v156 = sub v123, v139
-    v157 = sub v156, Field 1
-    v158 = cast v155 as Field
-    v159 = mul v158, Field 340282366920938463463374607431768211456
-    v160 = add v157, v159
-    v161 = sub v124, v140
-    v162 = cast v155 as Field
-    v163 = sub v161, v162
-    range_check v160 to 128 bits
-    range_check v163 to 128 bits
-    jmp b12(u1 0)
-  b12(v9: u1):
-    jmp b14(v9)
-  b13():
-    jmp b14(u1 0)
-  b14(v10: u1):
-    jmpif v10 then: b15, else: b16
-  b15():
-    store Field 1 at v73
-    jmp b16()
-  b16():
-    v164 = load v73 -> Field
-    v165 = load v12 -> Field
-    v166 = sub v164, v165
-    return v166
-  b17():
-    v167 = load v64 -> Field
-    v169 = sub u32 15, v8
-    v170 = array_get v61, index v169 -> u8
-    v171 = cast v170 as Field
-    v172 = load v62 -> Field
-    v173 = mul v171, v172
-    v174 = add v167, v173
-    store v174 at v64
-    v175 = load v65 -> Field
-    v177 = sub u32 31, v8
-    v178 = array_get v61, index v177 -> u8
-    v179 = cast v178 as Field
-    v180 = mul v179, v172
-    v181 = add v175, v180
-    store v181 at v65
-    v183 = mul v172, Field 256
-    store v183 at v62
-    v185 = unchecked_add v8, u32 1
-    jmp b7(v185)
-  b18():
-    v186 = load v59 -> [u8; 32]
-    v187 = array_get v16, index v7 -> u8
-    v188 = array_get v186, index v7 -> u8
-    v189 = xor v187, v188
-    v190 = array_set v186, index v7, value v189
-    v191 = unchecked_add v7, u32 1
-    store v190 at v59
-    v192 = unchecked_add v7, u32 1
-    jmp b5(v192)
-  b19():
-    v193 = load v56 -> u1
-    v194 = not v193
-    jmpif v194 then: b20, else: b23
-  b20():
-    v195 = array_get v54, index v6 -> u8
-    v196 = lt v6, u32 32
-    constrain v196 == u1 1, "Index out of bounds"
-    v197 = array_get v55, index v6 -> u8
-    v198 = eq v195, v197
-    v199 = not v198
-    jmpif v199 then: b21, else: b22
-  b21():
-    v200 = array_get v54, index v6 -> u8
-    v201 = lt v6, u32 32
-    constrain v201 == u1 1, "Index out of bounds"
-    v202 = array_get v55, index v6 -> u8
-    v203 = lt v200, v202
-    constrain v203 == u1 1
-    store u1 1 at v56
-    jmp b22()
-  b22():
-    jmp b23()
-  b23():
-    v204 = unchecked_add v6, u32 1
-    jmp b3(v204)
-  b24():
-    v205 = load v47 -> u1
-    v206 = not v205
-    jmpif v206 then: b25, else: b28
-  b25():
-    v207 = array_get v16, index v5 -> u8
-    v208 = lt v5, u32 32
-    constrain v208 == u1 1, "Index out of bounds"
-    v209 = array_get v46, index v5 -> u8
-    v210 = eq v207, v209
-    v211 = not v210
-    jmpif v211 then: b26, else: b27
-  b26():
-    v212 = array_get v16, index v5 -> u8
-    v213 = lt v5, u32 32
-    constrain v213 == u1 1, "Index out of bounds"
-    v214 = array_get v46, index v5 -> u8
-    v215 = lt v212, v214
-    constrain v215 == u1 1
-    store u1 1 at v47
-    jmp b27()
-  b27():
-    jmp b28()
-  b28():
-    v216 = unchecked_add v5, u32 1
-    jmp b1(v216)
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After `static_assert` and `assert_constant`:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v11 = allocate -> &mut Field
-    v12 = allocate -> &mut Field
-    store Field 0 at v12
-    v16 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v46 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v47 = allocate -> &mut u1
-    store u1 0 at v47
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v51 = lt v5, u32 32
-    jmpif v51 then: b24, else: b2
-  b2():
-    v52 = load v47 -> u1
-    constrain v52 == u1 1
-    v54 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v55 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v56 = allocate -> &mut u1
-    store u1 0 at v56
-    jmp b3(u32 0)
-  b3(v6: u32):
-    v57 = lt v6, u32 32
-    jmpif v57 then: b19, else: b4
-  b4():
-    v58 = load v56 -> u1
-    constrain v58 == u1 1
-    v59 = allocate -> &mut [u8; 32]
-    store v54 at v59
-    jmp b5(u32 0)
-  b5(v7: u32):
-    v60 = lt v7, u32 32
-    jmpif v60 then: b18, else: b6
-  b6():
-    v61 = load v59 -> [u8; 32]
-    v62 = allocate -> &mut Field
-    store Field 1 at v62
-    v64 = allocate -> &mut Field
-    store Field 0 at v64
-    v65 = allocate -> &mut Field
-    store Field 0 at v65
-    jmp b7(u32 0)
-  b7(v8: u32):
-    v67 = lt v8, u32 16
-    jmpif v67 then: b17, else: b8
-  b8():
-    v68 = load v65 -> Field
-    v69 = load v64 -> Field
-    v70 = load v62 -> Field
-    v71 = mul v69, v70
-    v72 = add v68, v71
-    store v72 at v12
-    v73 = allocate -> &mut Field
-    store Field 0 at v73
-    v74 = eq v4, Field 0
-    jmpif v74 then: b13, else: b9
-  b9():
-    v76 = call f1(v4, Field 0) -> u1
-    jmpif v76 then: b11, else: b10
-  b10():
-    v78, v79 = call f3(v4) -> (Field, Field)
-    range_check v78 to 128 bits
-    range_check v79 to 128 bits
-    v81 = mul Field 340282366920938463463374607431768211456, v79
-    v82 = add v78, v81
-    v83 = eq v4, v82
-    constrain v4 == v82
-    v86 = call f2(Field 53438638232309528389504892708671455233, v78) -> u1
-    v87 = sub Field 53438638232309528389504892708671455233, v78
-    v88 = sub v87, Field 1
-    v89 = cast v86 as Field
-    v90 = mul v89, Field 340282366920938463463374607431768211456
-    v91 = add v88, v90
-    v93 = sub Field 64323764613183177041862057485226039389, v79
-    v94 = cast v86 as Field
-    v95 = sub v93, v94
-    range_check v91 to 128 bits
-    range_check v95 to 128 bits
-    v97, v98 = call f3(Field 0) -> (Field, Field)
-    range_check v97 to 128 bits
-    range_check v98 to 128 bits
-    v99 = mul Field 340282366920938463463374607431768211456, v98
-    v100 = add v97, v99
-    v101 = eq Field 0, v100
-    constrain Field 0 == v100
-    v103 = call f2(Field 53438638232309528389504892708671455233, v97) -> u1
-    v104 = sub Field 53438638232309528389504892708671455233, v97
-    v105 = sub v104, Field 1
-    v106 = cast v103 as Field
-    v107 = mul v106, Field 340282366920938463463374607431768211456
-    v108 = add v105, v107
-    v109 = sub Field 64323764613183177041862057485226039389, v98
-    v110 = cast v103 as Field
-    v111 = sub v109, v110
-    range_check v108 to 128 bits
-    range_check v111 to 128 bits
-    v113 = call f2(v78, v97) -> u1
-    v114 = sub v78, v97
-    v115 = sub v114, Field 1
-    v116 = cast v113 as Field
-    v117 = mul v116, Field 340282366920938463463374607431768211456
-    v118 = add v115, v117
-    v119 = sub v79, v98
-    v120 = cast v113 as Field
-    v121 = sub v119, v120
-    range_check v118 to 128 bits
-    range_check v121 to 128 bits
-    jmp b12(u1 1)
-  b11():
-    v123, v124 = call f3(Field 0) -> (Field, Field)
-    range_check v123 to 128 bits
-    range_check v124 to 128 bits
-    v125 = mul Field 340282366920938463463374607431768211456, v124
-    v126 = add v123, v125
-    v127 = eq Field 0, v126
-    constrain Field 0 == v126
-    v129 = call f2(Field 53438638232309528389504892708671455233, v123) -> u1
-    v130 = sub Field 53438638232309528389504892708671455233, v123
-    v131 = sub v130, Field 1
-    v132 = cast v129 as Field
-    v133 = mul v132, Field 340282366920938463463374607431768211456
-    v134 = add v131, v133
-    v135 = sub Field 64323764613183177041862057485226039389, v124
-    v136 = cast v129 as Field
-    v137 = sub v135, v136
-    range_check v134 to 128 bits
-    range_check v137 to 128 bits
-    v139, v140 = call f3(v4) -> (Field, Field)
-    range_check v139 to 128 bits
-    range_check v140 to 128 bits
-    v141 = mul Field 340282366920938463463374607431768211456, v140
-    v142 = add v139, v141
-    v143 = eq v4, v142
-    constrain v4 == v142
-    v145 = call f2(Field 53438638232309528389504892708671455233, v139) -> u1
-    v146 = sub Field 53438638232309528389504892708671455233, v139
-    v147 = sub v146, Field 1
-    v148 = cast v145 as Field
-    v149 = mul v148, Field 340282366920938463463374607431768211456
-    v150 = add v147, v149
-    v151 = sub Field 64323764613183177041862057485226039389, v140
-    v152 = cast v145 as Field
-    v153 = sub v151, v152
-    range_check v150 to 128 bits
-    range_check v153 to 128 bits
-    v155 = call f2(v123, v139) -> u1
-    v156 = sub v123, v139
-    v157 = sub v156, Field 1
-    v158 = cast v155 as Field
-    v159 = mul v158, Field 340282366920938463463374607431768211456
-    v160 = add v157, v159
-    v161 = sub v124, v140
-    v162 = cast v155 as Field
-    v163 = sub v161, v162
-    range_check v160 to 128 bits
-    range_check v163 to 128 bits
-    jmp b12(u1 0)
-  b12(v9: u1):
-    jmp b14(v9)
-  b13():
-    jmp b14(u1 0)
-  b14(v10: u1):
-    jmpif v10 then: b15, else: b16
-  b15():
-    store Field 1 at v73
-    jmp b16()
-  b16():
-    v164 = load v73 -> Field
-    v165 = load v12 -> Field
-    v166 = sub v164, v165
-    return v166
-  b17():
-    v167 = load v64 -> Field
-    v169 = sub u32 15, v8
-    v170 = array_get v61, index v169 -> u8
-    v171 = cast v170 as Field
-    v172 = load v62 -> Field
-    v173 = mul v171, v172
-    v174 = add v167, v173
-    store v174 at v64
-    v175 = load v65 -> Field
-    v177 = sub u32 31, v8
-    v178 = array_get v61, index v177 -> u8
-    v179 = cast v178 as Field
-    v180 = mul v179, v172
-    v181 = add v175, v180
-    store v181 at v65
-    v183 = mul v172, Field 256
-    store v183 at v62
-    v185 = unchecked_add v8, u32 1
-    jmp b7(v185)
-  b18():
-    v186 = load v59 -> [u8; 32]
-    v187 = array_get v16, index v7 -> u8
-    v188 = array_get v186, index v7 -> u8
-    v189 = xor v187, v188
-    v190 = array_set v186, index v7, value v189
-    v191 = unchecked_add v7, u32 1
-    store v190 at v59
-    v192 = unchecked_add v7, u32 1
-    jmp b5(v192)
-  b19():
-    v193 = load v56 -> u1
-    v194 = not v193
-    jmpif v194 then: b20, else: b23
-  b20():
-    v195 = array_get v54, index v6 -> u8
-    v196 = lt v6, u32 32
-    constrain v196 == u1 1, "Index out of bounds"
-    v197 = array_get v55, index v6 -> u8
-    v198 = eq v195, v197
-    v199 = not v198
-    jmpif v199 then: b21, else: b22
-  b21():
-    v200 = array_get v54, index v6 -> u8
-    v201 = lt v6, u32 32
-    constrain v201 == u1 1, "Index out of bounds"
-    v202 = array_get v55, index v6 -> u8
-    v203 = lt v200, v202
-    constrain v203 == u1 1
-    store u1 1 at v56
-    jmp b22()
-  b22():
-    jmp b23()
-  b23():
-    v204 = unchecked_add v6, u32 1
-    jmp b3(v204)
-  b24():
-    v205 = load v47 -> u1
-    v206 = not v205
-    jmpif v206 then: b25, else: b28
-  b25():
-    v207 = array_get v16, index v5 -> u8
-    v208 = lt v5, u32 32
-    constrain v208 == u1 1, "Index out of bounds"
-    v209 = array_get v46, index v5 -> u8
-    v210 = eq v207, v209
-    v211 = not v210
-    jmpif v211 then: b26, else: b27
-  b26():
-    v212 = array_get v16, index v5 -> u8
-    v213 = lt v5, u32 32
-    constrain v213 == u1 1, "Index out of bounds"
-    v214 = array_get v46, index v5 -> u8
-    v215 = lt v212, v214
-    constrain v215 == u1 1
-    store u1 1 at v47
-    jmp b27()
-  b27():
-    jmp b28()
-  b28():
-    v216 = unchecked_add v5, u32 1
-    jmp b1(v216)
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Loop Invariant Code Motion:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v11 = allocate -> &mut Field
-    v12 = allocate -> &mut Field
-    store Field 0 at v12
-    v16 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v46 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v47 = allocate -> &mut u1
-    store u1 0 at v47
-    jmp b1(u32 0)
-  b1(v5: u32):
-    v51 = lt v5, u32 32
-    jmpif v51 then: b24, else: b2
-  b2():
-    v52 = load v47 -> u1
-    constrain v52 == u1 1
-    v54 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v55 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v56 = allocate -> &mut u1
-    store u1 0 at v56
-    jmp b3(u32 0)
-  b3(v6: u32):
-    v57 = lt v6, u32 32
-    jmpif v57 then: b19, else: b4
-  b4():
-    v58 = load v56 -> u1
-    constrain v58 == u1 1
-    v59 = allocate -> &mut [u8; 32]
-    store v54 at v59
-    jmp b5(u32 0)
-  b5(v7: u32):
-    v60 = lt v7, u32 32
-    jmpif v60 then: b18, else: b6
-  b6():
-    v61 = load v59 -> [u8; 32]
-    v62 = allocate -> &mut Field
-    store Field 1 at v62
-    v64 = allocate -> &mut Field
-    store Field 0 at v64
-    v65 = allocate -> &mut Field
-    store Field 0 at v65
-    jmp b7(u32 0)
-  b7(v8: u32):
-    v67 = lt v8, u32 16
-    jmpif v67 then: b17, else: b8
-  b8():
-    v68 = load v65 -> Field
-    v69 = load v64 -> Field
-    v70 = load v62 -> Field
-    v71 = mul v69, v70
-    v72 = add v68, v71
-    store v72 at v12
-    v73 = allocate -> &mut Field
-    store Field 0 at v73
-    v74 = eq v4, Field 0
-    jmpif v74 then: b13, else: b9
-  b9():
-    v76 = call f1(v4, Field 0) -> u1
-    jmpif v76 then: b11, else: b10
-  b10():
-    v78, v79 = call f3(v4) -> (Field, Field)
-    range_check v78 to 128 bits
-    range_check v79 to 128 bits
-    v81 = mul Field 340282366920938463463374607431768211456, v79
-    v82 = add v78, v81
-    v83 = eq v4, v82
-    constrain v4 == v82
-    v86 = call f2(Field 53438638232309528389504892708671455233, v78) -> u1
-    v87 = sub Field 53438638232309528389504892708671455233, v78
-    v88 = sub v87, Field 1
-    v89 = cast v86 as Field
-    v90 = mul v89, Field 340282366920938463463374607431768211456
-    v91 = add v88, v90
-    v93 = sub Field 64323764613183177041862057485226039389, v79
-    v94 = cast v86 as Field
-    v95 = sub v93, v94
-    range_check v91 to 128 bits
-    range_check v95 to 128 bits
-    v97, v98 = call f3(Field 0) -> (Field, Field)
-    range_check v97 to 128 bits
-    range_check v98 to 128 bits
-    v99 = mul Field 340282366920938463463374607431768211456, v98
-    v100 = add v97, v99
-    v101 = eq Field 0, v100
-    constrain Field 0 == v100
-    v103 = call f2(Field 53438638232309528389504892708671455233, v97) -> u1
-    v104 = sub Field 53438638232309528389504892708671455233, v97
-    v105 = sub v104, Field 1
-    v106 = cast v103 as Field
-    v107 = mul v106, Field 340282366920938463463374607431768211456
-    v108 = add v105, v107
-    v109 = sub Field 64323764613183177041862057485226039389, v98
-    v110 = cast v103 as Field
-    v111 = sub v109, v110
-    range_check v108 to 128 bits
-    range_check v111 to 128 bits
-    v113 = call f2(v78, v97) -> u1
-    v114 = sub v78, v97
-    v115 = sub v114, Field 1
-    v116 = cast v113 as Field
-    v117 = mul v116, Field 340282366920938463463374607431768211456
-    v118 = add v115, v117
-    v119 = sub v79, v98
-    v120 = cast v113 as Field
-    v121 = sub v119, v120
-    range_check v118 to 128 bits
-    range_check v121 to 128 bits
-    jmp b12(u1 1)
-  b11():
-    v123, v124 = call f3(Field 0) -> (Field, Field)
-    range_check v123 to 128 bits
-    range_check v124 to 128 bits
-    v125 = mul Field 340282366920938463463374607431768211456, v124
-    v126 = add v123, v125
-    v127 = eq Field 0, v126
-    constrain Field 0 == v126
-    v129 = call f2(Field 53438638232309528389504892708671455233, v123) -> u1
-    v130 = sub Field 53438638232309528389504892708671455233, v123
-    v131 = sub v130, Field 1
-    v132 = cast v129 as Field
-    v133 = mul v132, Field 340282366920938463463374607431768211456
-    v134 = add v131, v133
-    v135 = sub Field 64323764613183177041862057485226039389, v124
-    v136 = cast v129 as Field
-    v137 = sub v135, v136
-    range_check v134 to 128 bits
-    range_check v137 to 128 bits
-    v139, v140 = call f3(v4) -> (Field, Field)
-    range_check v139 to 128 bits
-    range_check v140 to 128 bits
-    v141 = mul Field 340282366920938463463374607431768211456, v140
-    v142 = add v139, v141
-    v143 = eq v4, v142
-    constrain v4 == v142
-    v145 = call f2(Field 53438638232309528389504892708671455233, v139) -> u1
-    v146 = sub Field 53438638232309528389504892708671455233, v139
-    v147 = sub v146, Field 1
-    v148 = cast v145 as Field
-    v149 = mul v148, Field 340282366920938463463374607431768211456
-    v150 = add v147, v149
-    v151 = sub Field 64323764613183177041862057485226039389, v140
-    v152 = cast v145 as Field
-    v153 = sub v151, v152
-    range_check v150 to 128 bits
-    range_check v153 to 128 bits
-    v155 = call f2(v123, v139) -> u1
-    v156 = sub v123, v139
-    v157 = sub v156, Field 1
-    v158 = cast v155 as Field
-    v159 = mul v158, Field 340282366920938463463374607431768211456
-    v160 = add v157, v159
-    v161 = sub v124, v140
-    v162 = cast v155 as Field
-    v163 = sub v161, v162
-    range_check v160 to 128 bits
-    range_check v163 to 128 bits
-    jmp b12(u1 0)
-  b12(v9: u1):
-    jmp b14(v9)
-  b13():
-    jmp b14(u1 0)
-  b14(v10: u1):
-    jmpif v10 then: b15, else: b16
-  b15():
-    store Field 1 at v73
-    jmp b16()
-  b16():
-    v164 = load v73 -> Field
-    v165 = load v12 -> Field
-    v166 = sub v164, v165
-    return v166
-  b17():
-    v167 = load v64 -> Field
-    v169 = sub u32 15, v8
-    v170 = array_get v61, index v169 -> u8
-    v171 = cast v170 as Field
-    v172 = load v62 -> Field
-    v173 = mul v171, v172
-    v174 = add v167, v173
-    store v174 at v64
-    v175 = load v65 -> Field
-    v177 = sub u32 31, v8
-    v178 = array_get v61, index v177 -> u8
-    v179 = cast v178 as Field
-    v180 = mul v179, v172
-    v181 = add v175, v180
-    store v181 at v65
-    v183 = mul v172, Field 256
-    store v183 at v62
-    v185 = unchecked_add v8, u32 1
-    jmp b7(v185)
-  b18():
-    v186 = load v59 -> [u8; 32]
-    v187 = array_get v16, index v7 -> u8
-    v188 = array_get v186, index v7 -> u8
-    v189 = xor v187, v188
-    v190 = array_set v186, index v7, value v189
-    v191 = unchecked_add v7, u32 1
-    store v190 at v59
-    v192 = unchecked_add v7, u32 1
-    jmp b5(v192)
-  b19():
-    v193 = load v56 -> u1
-    v194 = not v193
-    jmpif v194 then: b20, else: b23
-  b20():
-    v195 = array_get v54, index v6 -> u8
-    v196 = lt v6, u32 32
-    constrain v196 == u1 1, "Index out of bounds"
-    v197 = array_get v55, index v6 -> u8
-    v198 = eq v195, v197
-    v199 = not v198
-    jmpif v199 then: b21, else: b22
-  b21():
-    v200 = array_get v54, index v6 -> u8
-    v201 = lt v6, u32 32
-    constrain v201 == u1 1, "Index out of bounds"
-    v202 = array_get v55, index v6 -> u8
-    v203 = lt v200, v202
-    constrain v203 == u1 1
-    store u1 1 at v56
-    jmp b22()
-  b22():
-    jmp b23()
-  b23():
-    v204 = unchecked_add v6, u32 1
-    jmp b3(v204)
-  b24():
-    v205 = load v47 -> u1
-    v206 = not v205
-    jmpif v206 then: b25, else: b28
-  b25():
-    v207 = array_get v16, index v5 -> u8
-    v208 = lt v5, u32 32
-    constrain v208 == u1 1, "Index out of bounds"
-    v209 = array_get v46, index v5 -> u8
-    v210 = eq v207, v209
-    v211 = not v210
-    jmpif v211 then: b26, else: b27
-  b26():
-    v212 = array_get v16, index v5 -> u8
-    v213 = lt v5, u32 32
-    constrain v213 == u1 1, "Index out of bounds"
-    v214 = array_get v46, index v5 -> u8
-    v215 = lt v212, v214
-    constrain v215 == u1 1
-    store u1 1 at v47
-    jmp b27()
-  b27():
-    jmp b28()
-  b28():
-    v216 = unchecked_add v5, u32 1
-    jmp b1(v216)
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Unrolling:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v7 = allocate -> &mut Field
-    v8 = allocate -> &mut Field
-    store Field 0 at v8
-    v12 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v42 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v43 = allocate -> &mut u1
-    store u1 0 at v43
-    v45 = load v43 -> u1
-    v46 = not v45
-    jmpif v46 then: b1, else: b4
-  b1():
-    v48 = array_get v12, index u32 0 -> u8
-    v49 = eq v48, u8 48
-    v50 = not v49
-    jmpif v50 then: b2, else: b3
-  b2():
-    v51 = array_get v12, index u32 0 -> u8
-    v52 = lt v51, u8 48
-    constrain v52 == u1 1
-    store u1 1 at v43
-    jmp b3()
-  b3():
-    jmp b4()
-  b4():
-    v54 = load v43 -> u1
-    v55 = not v54
-    jmpif v55 then: b5, else: b8
-  b5():
-    v57 = array_get v12, index u32 1 -> u8
-    v58 = eq v57, u8 100
-    v59 = not v58
-    jmpif v59 then: b6, else: b7
-  b6():
-    v60 = array_get v12, index u32 1 -> u8
-    v61 = lt v60, u8 100
-    constrain v61 == u1 1
-    store u1 1 at v43
-    jmp b7()
-  b7():
-    jmp b8()
-  b8():
-    v62 = load v43 -> u1
-    v63 = not v62
-    jmpif v63 then: b9, else: b12
-  b9():
-    v65 = array_get v12, index u32 2 -> u8
-    v66 = eq v65, u8 78
-    v67 = not v66
-    jmpif v67 then: b10, else: b11
-  b10():
-    v68 = array_get v12, index u32 2 -> u8
-    v69 = lt v68, u8 78
-    constrain v69 == u1 1
-    store u1 1 at v43
-    jmp b11()
-  b11():
-    jmp b12()
-  b12():
-    v70 = load v43 -> u1
-    v71 = not v70
-    jmpif v71 then: b13, else: b16
-  b13():
-    v73 = array_get v12, index u32 3 -> u8
-    v74 = eq v73, u8 114
-    v75 = not v74
-    jmpif v75 then: b14, else: b15
-  b14():
-    v76 = array_get v12, index u32 3 -> u8
-    v77 = lt v76, u8 114
-    constrain v77 == u1 1
-    store u1 1 at v43
-    jmp b15()
-  b15():
-    jmp b16()
-  b16():
-    v78 = load v43 -> u1
-    v79 = not v78
-    jmpif v79 then: b17, else: b20
-  b17():
-    v81 = array_get v12, index u32 4 -> u8
-    v82 = eq v81, u8 225
-    v83 = not v82
-    jmpif v83 then: b18, else: b19
-  b18():
-    v84 = array_get v12, index u32 4 -> u8
-    v85 = lt v84, u8 225
-    constrain v85 == u1 1
-    store u1 1 at v43
-    jmp b19()
-  b19():
-    jmp b20()
-  b20():
-    v86 = load v43 -> u1
-    v87 = not v86
-    jmpif v87 then: b21, else: b24
-  b21():
-    v89 = array_get v12, index u32 5 -> u8
-    v90 = eq v89, u8 49
-    v91 = not v90
-    jmpif v91 then: b22, else: b23
-  b22():
-    v92 = array_get v12, index u32 5 -> u8
-    v93 = lt v92, u8 49
-    constrain v93 == u1 1
-    store u1 1 at v43
-    jmp b23()
-  b23():
-    jmp b24()
-  b24():
-    v94 = load v43 -> u1
-    v95 = not v94
-    jmpif v95 then: b25, else: b28
-  b25():
-    v97 = array_get v12, index u32 6 -> u8
-    v98 = eq v97, u8 160
-    v99 = not v98
-    jmpif v99 then: b26, else: b27
-  b26():
-    v100 = array_get v12, index u32 6 -> u8
-    v101 = lt v100, u8 160
-    constrain v101 == u1 1
-    store u1 1 at v43
-    jmp b27()
-  b27():
-    jmp b28()
-  b28():
-    v102 = load v43 -> u1
-    v103 = not v102
-    jmpif v103 then: b29, else: b32
-  b29():
-    v105 = array_get v12, index u32 7 -> u8
-    v106 = eq v105, u8 41
-    v107 = not v106
-    jmpif v107 then: b30, else: b31
-  b30():
-    v108 = array_get v12, index u32 7 -> u8
-    v109 = lt v108, u8 41
-    constrain v109 == u1 1
-    store u1 1 at v43
-    jmp b31()
-  b31():
-    jmp b32()
-  b32():
-    v110 = load v43 -> u1
-    v111 = not v110
-    jmpif v111 then: b33, else: b36
-  b33():
-    v113 = array_get v12, index u32 8 -> u8
-    v114 = eq v113, u8 184
-    v115 = not v114
-    jmpif v115 then: b34, else: b35
-  b34():
-    v116 = array_get v12, index u32 8 -> u8
-    v117 = lt v116, u8 184
-    constrain v117 == u1 1
-    store u1 1 at v43
-    jmp b35()
-  b35():
-    jmp b36()
-  b36():
-    v118 = load v43 -> u1
-    v119 = not v118
-    jmpif v119 then: b37, else: b40
-  b37():
-    v121 = array_get v12, index u32 9 -> u8
-    v122 = eq v121, u8 80
-    v123 = not v122
-    jmpif v123 then: b38, else: b39
-  b38():
-    v124 = array_get v12, index u32 9 -> u8
-    v125 = lt v124, u8 80
-    constrain v125 == u1 1
-    store u1 1 at v43
-    jmp b39()
-  b39():
-    jmp b40()
-  b40():
-    v126 = load v43 -> u1
-    v127 = not v126
-    jmpif v127 then: b41, else: b44
-  b41():
-    v129 = array_get v12, index u32 10 -> u8
-    v130 = eq v129, u8 69
-    v131 = not v130
-    jmpif v131 then: b42, else: b43
-  b42():
-    v132 = array_get v12, index u32 10 -> u8
-    v133 = lt v132, u8 69
-    constrain v133 == u1 1
-    store u1 1 at v43
-    jmp b43()
-  b43():
-    jmp b44()
-  b44():
-    v134 = load v43 -> u1
-    v135 = not v134
-    jmpif v135 then: b45, else: b48
-  b45():
-    v137 = array_get v12, index u32 11 -> u8
-    v138 = eq v137, u8 182
-    v139 = not v138
-    jmpif v139 then: b46, else: b47
-  b46():
-    v140 = array_get v12, index u32 11 -> u8
-    v141 = lt v140, u8 182
-    constrain v141 == u1 1
-    store u1 1 at v43
-    jmp b47()
-  b47():
-    jmp b48()
-  b48():
-    v142 = load v43 -> u1
-    v143 = not v142
-    jmpif v143 then: b49, else: b52
-  b49():
-    v145 = array_get v12, index u32 12 -> u8
-    v146 = eq v145, u8 129
-    v147 = not v146
-    jmpif v147 then: b50, else: b51
-  b50():
-    v148 = array_get v12, index u32 12 -> u8
-    v149 = lt v148, u8 129
-    constrain v149 == u1 1
-    store u1 1 at v43
-    jmp b51()
-  b51():
-    jmp b52()
-  b52():
-    v150 = load v43 -> u1
-    v151 = not v150
-    jmpif v151 then: b53, else: b56
-  b53():
-    v153 = array_get v12, index u32 13 -> u8
-    v154 = eq v153, u8 129
-    v155 = not v154
-    jmpif v155 then: b54, else: b55
-  b54():
-    v156 = array_get v12, index u32 13 -> u8
-    v157 = lt v156, u8 129
-    constrain v157 == u1 1
-    store u1 1 at v43
-    jmp b55()
-  b55():
-    jmp b56()
-  b56():
-    v158 = load v43 -> u1
-    v159 = not v158
-    jmpif v159 then: b57, else: b60
-  b57():
-    v161 = array_get v12, index u32 14 -> u8
-    v162 = eq v161, u8 88
-    v163 = not v162
-    jmpif v163 then: b58, else: b59
-  b58():
-    v164 = array_get v12, index u32 14 -> u8
-    v165 = lt v164, u8 88
-    constrain v165 == u1 1
-    store u1 1 at v43
-    jmp b59()
-  b59():
-    jmp b60()
-  b60():
-    v166 = load v43 -> u1
-    v167 = not v166
-    jmpif v167 then: b61, else: b64
-  b61():
-    v169 = array_get v12, index u32 15 -> u8
-    v170 = eq v169, u8 93
-    v171 = not v170
-    jmpif v171 then: b62, else: b63
-  b62():
-    v172 = array_get v12, index u32 15 -> u8
-    v173 = lt v172, u8 93
-    constrain v173 == u1 1
-    store u1 1 at v43
-    jmp b63()
-  b63():
-    jmp b64()
-  b64():
-    v174 = load v43 -> u1
-    v175 = not v174
-    jmpif v175 then: b65, else: b68
-  b65():
-    v177 = array_get v12, index u32 16 -> u8
-    v178 = eq v177, u8 40
-    v179 = not v178
-    jmpif v179 then: b66, else: b67
-  b66():
-    v180 = array_get v12, index u32 16 -> u8
-    v181 = lt v180, u8 40
-    constrain v181 == u1 1
-    store u1 1 at v43
-    jmp b67()
-  b67():
-    jmp b68()
-  b68():
-    v182 = load v43 -> u1
-    v183 = not v182
-    jmpif v183 then: b69, else: b72
-  b69():
-    v185 = array_get v12, index u32 17 -> u8
-    v186 = eq v185, u8 51
-    v187 = not v186
-    jmpif v187 then: b70, else: b71
-  b70():
-    v188 = array_get v12, index u32 17 -> u8
-    v189 = lt v188, u8 51
-    constrain v189 == u1 1
-    store u1 1 at v43
-    jmp b71()
-  b71():
-    jmp b72()
-  b72():
-    v190 = load v43 -> u1
-    v191 = not v190
-    jmpif v191 then: b73, else: b76
-  b73():
-    v193 = array_get v12, index u32 18 -> u8
-    v194 = eq v193, u8 232
-    v195 = not v194
-    jmpif v195 then: b74, else: b75
-  b74():
-    v196 = array_get v12, index u32 18 -> u8
-    v197 = lt v196, u8 232
-    constrain v197 == u1 1
-    store u1 1 at v43
-    jmp b75()
-  b75():
-    jmp b76()
-  b76():
-    v198 = load v43 -> u1
-    v199 = not v198
-    jmpif v199 then: b77, else: b80
-  b77():
-    v201 = array_get v12, index u32 19 -> u8
-    v202 = eq v201, u8 72
-    v203 = not v202
-    jmpif v203 then: b78, else: b79
-  b78():
-    v204 = array_get v12, index u32 19 -> u8
-    v205 = lt v204, u8 72
-    constrain v205 == u1 1
-    store u1 1 at v43
-    jmp b79()
-  b79():
-    jmp b80()
-  b80():
-    v206 = load v43 -> u1
-    v207 = not v206
-    jmpif v207 then: b81, else: b84
-  b81():
-    v209 = array_get v12, index u32 20 -> u8
-    v210 = eq v209, u8 121
-    v211 = not v210
-    jmpif v211 then: b82, else: b83
-  b82():
-    v212 = array_get v12, index u32 20 -> u8
-    v213 = lt v212, u8 121
-    constrain v213 == u1 1
-    store u1 1 at v43
-    jmp b83()
-  b83():
-    jmp b84()
-  b84():
-    v214 = load v43 -> u1
-    v215 = not v214
-    jmpif v215 then: b85, else: b88
-  b85():
-    v217 = array_get v12, index u32 21 -> u8
-    v218 = eq v217, u8 185
-    v219 = not v218
-    jmpif v219 then: b86, else: b87
-  b86():
-    v220 = array_get v12, index u32 21 -> u8
-    v221 = lt v220, u8 185
-    constrain v221 == u1 1
-    store u1 1 at v43
-    jmp b87()
-  b87():
-    jmp b88()
-  b88():
-    v222 = load v43 -> u1
-    v223 = not v222
-    jmpif v223 then: b89, else: b92
-  b89():
-    v225 = array_get v12, index u32 22 -> u8
-    v226 = eq v225, u8 112
-    v227 = not v226
-    jmpif v227 then: b90, else: b91
-  b90():
-    v228 = array_get v12, index u32 22 -> u8
-    v229 = lt v228, u8 112
-    constrain v229 == u1 1
-    store u1 1 at v43
-    jmp b91()
-  b91():
-    jmp b92()
-  b92():
-    v230 = load v43 -> u1
-    v231 = not v230
-    jmpif v231 then: b93, else: b96
-  b93():
-    v233 = array_get v12, index u32 23 -> u8
-    v234 = eq v233, u8 145
-    v235 = not v234
-    jmpif v235 then: b94, else: b95
-  b94():
-    v236 = array_get v12, index u32 23 -> u8
-    v237 = lt v236, u8 145
-    constrain v237 == u1 1
-    store u1 1 at v43
-    jmp b95()
-  b95():
-    jmp b96()
-  b96():
-    v238 = load v43 -> u1
-    v239 = not v238
-    jmpif v239 then: b97, else: b100
-  b97():
-    v241 = array_get v12, index u32 24 -> u8
-    v242 = eq v241, u8 67
-    v243 = not v242
-    jmpif v243 then: b98, else: b99
-  b98():
-    v244 = array_get v12, index u32 24 -> u8
-    v245 = lt v244, u8 67
-    constrain v245 == u1 1
-    store u1 1 at v43
-    jmp b99()
-  b99():
-    jmp b100()
-  b100():
-    v246 = load v43 -> u1
-    v247 = not v246
-    jmpif v247 then: b101, else: b104
-  b101():
-    v249 = array_get v12, index u32 25 -> u8
-    v250 = eq v249, u8 225
-    v251 = not v250
-    jmpif v251 then: b102, else: b103
-  b102():
-    v252 = array_get v12, index u32 25 -> u8
-    v253 = lt v252, u8 225
-    constrain v253 == u1 1
-    store u1 1 at v43
-    jmp b103()
-  b103():
-    jmp b104()
-  b104():
-    v254 = load v43 -> u1
-    v255 = not v254
-    jmpif v255 then: b105, else: b108
-  b105():
-    v257 = array_get v12, index u32 26 -> u8
-    v258 = eq v257, u8 245
-    v259 = not v258
-    jmpif v259 then: b106, else: b107
-  b106():
-    v260 = array_get v12, index u32 26 -> u8
-    v261 = lt v260, u8 245
-    constrain v261 == u1 1
-    store u1 1 at v43
-    jmp b107()
-  b107():
-    jmp b108()
-  b108():
-    v262 = load v43 -> u1
-    v263 = not v262
-    jmpif v263 then: b109, else: b112
-  b109():
-    v265 = array_get v12, index u32 27 -> u8
-    v266 = eq v265, u8 147
-    v267 = not v266
-    jmpif v267 then: b110, else: b111
-  b110():
-    v268 = array_get v12, index u32 27 -> u8
-    v269 = lt v268, u8 147
-    constrain v269 == u1 1
-    store u1 1 at v43
-    jmp b111()
-  b111():
-    jmp b112()
-  b112():
-    v270 = load v43 -> u1
-    v271 = not v270
-    jmpif v271 then: b113, else: b116
-  b113():
-    v273 = array_get v12, index u32 28 -> u8
-    v274 = eq v273, u8 240
-    v275 = not v274
-    jmpif v275 then: b114, else: b115
-  b114():
-    v276 = array_get v12, index u32 28 -> u8
-    v277 = lt v276, u8 240
-    constrain v277 == u1 1
-    store u1 1 at v43
-    jmp b115()
-  b115():
-    jmp b116()
-  b116():
-    v278 = load v43 -> u1
-    v279 = not v278
-    jmpif v279 then: b117, else: b120
-  b117():
-    v281 = array_get v12, index u32 29 -> u8
-    v282 = eq v281, u8 0
-    v283 = not v282
-    jmpif v283 then: b118, else: b119
-  b118():
-    v284 = array_get v12, index u32 29 -> u8
-    constrain u1 0 == u1 1
-    store u1 1 at v43
-    jmp b119()
-  b119():
-    jmp b120()
-  b120():
-    v285 = load v43 -> u1
-    v286 = not v285
-    jmpif v286 then: b121, else: b124
-  b121():
-    v288 = array_get v12, index u32 30 -> u8
-    v289 = eq v288, u8 0
-    v290 = not v289
-    jmpif v290 then: b122, else: b123
-  b122():
-    v291 = array_get v12, index u32 30 -> u8
-    constrain u1 0 == u1 1
-    store u1 1 at v43
-    jmp b123()
-  b123():
-    jmp b124()
-  b124():
-    v292 = load v43 -> u1
-    v293 = not v292
-    jmpif v293 then: b125, else: b128
-  b125():
-    v295 = array_get v12, index u32 31 -> u8
-    v296 = eq v295, u8 1
-    v297 = not v296
-    jmpif v297 then: b126, else: b127
-  b126():
-    v298 = array_get v12, index u32 31 -> u8
-    v299 = eq v298, u8 0
-    constrain v298 == u8 0
-    store u1 1 at v43
-    jmp b127()
-  b127():
-    jmp b128()
-  b128():
-    jmp b129()
-  b129():
-    v300 = load v43 -> u1
-    constrain v300 == u1 1
-    v301 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v302 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v303 = allocate -> &mut u1
-    store u1 0 at v303
-    v304 = load v303 -> u1
-    v305 = not v304
-    jmpif v305 then: b130, else: b133
-  b130():
-    jmp b131()
-  b131():
-    store u1 1 at v303
-    jmp b132()
-  b132():
-    jmp b133()
-  b133():
-    v306 = load v303 -> u1
-    v307 = not v306
-    jmpif v307 then: b134, else: b137
-  b134():
-    jmp b135()
-  b135():
-    store u1 1 at v303
-    jmp b136()
-  b136():
-    jmp b137()
-  b137():
-    v308 = load v303 -> u1
-    v309 = not v308
-    jmpif v309 then: b138, else: b141
-  b138():
-    jmp b139()
-  b139():
-    store u1 1 at v303
-    jmp b140()
-  b140():
-    jmp b141()
-  b141():
-    v310 = load v303 -> u1
-    v311 = not v310
-    jmpif v311 then: b142, else: b145
-  b142():
-    jmp b143()
-  b143():
-    store u1 1 at v303
-    jmp b144()
-  b144():
-    jmp b145()
-  b145():
-    v312 = load v303 -> u1
-    v313 = not v312
-    jmpif v313 then: b146, else: b149
-  b146():
-    jmp b147()
-  b147():
-    store u1 1 at v303
-    jmp b148()
-  b148():
-    jmp b149()
-  b149():
-    v314 = load v303 -> u1
-    v315 = not v314
-    jmpif v315 then: b150, else: b153
-  b150():
-    jmp b151()
-  b151():
-    store u1 1 at v303
-    jmp b152()
-  b152():
-    jmp b153()
-  b153():
-    v316 = load v303 -> u1
-    v317 = not v316
-    jmpif v317 then: b154, else: b157
-  b154():
-    jmp b155()
-  b155():
-    store u1 1 at v303
-    jmp b156()
-  b156():
-    jmp b157()
-  b157():
-    v318 = load v303 -> u1
-    v319 = not v318
-    jmpif v319 then: b158, else: b161
-  b158():
-    jmp b159()
-  b159():
-    store u1 1 at v303
-    jmp b160()
-  b160():
-    jmp b161()
-  b161():
-    v320 = load v303 -> u1
-    v321 = not v320
-    jmpif v321 then: b162, else: b165
-  b162():
-    jmp b163()
-  b163():
-    store u1 1 at v303
-    jmp b164()
-  b164():
-    jmp b165()
-  b165():
-    v322 = load v303 -> u1
-    v323 = not v322
-    jmpif v323 then: b166, else: b169
-  b166():
-    jmp b167()
-  b167():
-    store u1 1 at v303
-    jmp b168()
-  b168():
-    jmp b169()
-  b169():
-    v324 = load v303 -> u1
-    v325 = not v324
-    jmpif v325 then: b170, else: b173
-  b170():
-    jmp b171()
-  b171():
-    store u1 1 at v303
-    jmp b172()
-  b172():
-    jmp b173()
-  b173():
-    v326 = load v303 -> u1
-    v327 = not v326
-    jmpif v327 then: b174, else: b177
-  b174():
-    jmp b175()
-  b175():
-    store u1 1 at v303
-    jmp b176()
-  b176():
-    jmp b177()
-  b177():
-    v328 = load v303 -> u1
-    v329 = not v328
-    jmpif v329 then: b178, else: b181
-  b178():
-    jmp b179()
-  b179():
-    store u1 1 at v303
-    jmp b180()
-  b180():
-    jmp b181()
-  b181():
-    v330 = load v303 -> u1
-    v331 = not v330
-    jmpif v331 then: b182, else: b185
-  b182():
-    jmp b183()
-  b183():
-    store u1 1 at v303
-    jmp b184()
-  b184():
-    jmp b185()
-  b185():
-    v332 = load v303 -> u1
-    v333 = not v332
-    jmpif v333 then: b186, else: b189
-  b186():
-    jmp b187()
-  b187():
-    store u1 1 at v303
-    jmp b188()
-  b188():
-    jmp b189()
-  b189():
-    v334 = load v303 -> u1
-    v335 = not v334
-    jmpif v335 then: b190, else: b193
-  b190():
-    jmp b191()
-  b191():
-    store u1 1 at v303
-    jmp b192()
-  b192():
-    jmp b193()
-  b193():
-    v336 = load v303 -> u1
-    v337 = not v336
-    jmpif v337 then: b194, else: b197
-  b194():
-    jmp b195()
-  b195():
-    store u1 1 at v303
-    jmp b196()
-  b196():
-    jmp b197()
-  b197():
-    v338 = load v303 -> u1
-    v339 = not v338
-    jmpif v339 then: b198, else: b201
-  b198():
-    jmp b199()
-  b199():
-    store u1 1 at v303
-    jmp b200()
-  b200():
-    jmp b201()
-  b201():
-    v340 = load v303 -> u1
-    v341 = not v340
-    jmpif v341 then: b202, else: b205
-  b202():
-    jmp b203()
-  b203():
-    store u1 1 at v303
-    jmp b204()
-  b204():
-    jmp b205()
-  b205():
-    v342 = load v303 -> u1
-    v343 = not v342
-    jmpif v343 then: b206, else: b209
-  b206():
-    jmp b207()
-  b207():
-    store u1 1 at v303
-    jmp b208()
-  b208():
-    jmp b209()
-  b209():
-    v344 = load v303 -> u1
-    v345 = not v344
-    jmpif v345 then: b210, else: b213
-  b210():
-    jmp b211()
-  b211():
-    store u1 1 at v303
-    jmp b212()
-  b212():
-    jmp b213()
-  b213():
-    v346 = load v303 -> u1
-    v347 = not v346
-    jmpif v347 then: b214, else: b217
-  b214():
-    jmp b215()
-  b215():
-    store u1 1 at v303
-    jmp b216()
-  b216():
-    jmp b217()
-  b217():
-    v348 = load v303 -> u1
-    v349 = not v348
-    jmpif v349 then: b218, else: b221
-  b218():
-    jmp b219()
-  b219():
-    store u1 1 at v303
-    jmp b220()
-  b220():
-    jmp b221()
-  b221():
-    v350 = load v303 -> u1
-    v351 = not v350
-    jmpif v351 then: b222, else: b225
-  b222():
-    jmp b223()
-  b223():
-    store u1 1 at v303
-    jmp b224()
-  b224():
-    jmp b225()
-  b225():
-    v352 = load v303 -> u1
-    v353 = not v352
-    jmpif v353 then: b226, else: b229
-  b226():
-    jmp b227()
-  b227():
-    store u1 1 at v303
-    jmp b228()
-  b228():
-    jmp b229()
-  b229():
-    v354 = load v303 -> u1
-    v355 = not v354
-    jmpif v355 then: b230, else: b233
-  b230():
-    jmp b231()
-  b231():
-    store u1 1 at v303
-    jmp b232()
-  b232():
-    jmp b233()
-  b233():
-    v356 = load v303 -> u1
-    v357 = not v356
-    jmpif v357 then: b234, else: b237
-  b234():
-    jmp b235()
-  b235():
-    store u1 1 at v303
-    jmp b236()
-  b236():
-    jmp b237()
-  b237():
-    v358 = load v303 -> u1
-    v359 = not v358
-    jmpif v359 then: b238, else: b241
-  b238():
-    jmp b239()
-  b239():
-    store u1 1 at v303
-    jmp b240()
-  b240():
-    jmp b241()
-  b241():
-    v360 = load v303 -> u1
-    v361 = not v360
-    jmpif v361 then: b242, else: b245
-  b242():
-    jmp b243()
-  b243():
-    store u1 1 at v303
-    jmp b244()
-  b244():
-    jmp b245()
-  b245():
-    v362 = load v303 -> u1
-    v363 = not v362
-    jmpif v363 then: b246, else: b248
-  b246():
-    jmp b247()
-  b247():
-    jmp b248()
-  b248():
-    v364 = load v303 -> u1
-    v365 = not v364
-    jmpif v365 then: b249, else: b251
-  b249():
-    jmp b250()
-  b250():
-    jmp b251()
-  b251():
-    v366 = load v303 -> u1
-    v367 = not v366
-    jmpif v367 then: b252, else: b255
-  b252():
-    jmp b253()
-  b253():
-    store u1 1 at v303
-    jmp b254()
-  b254():
-    jmp b255()
-  b255():
-    jmp b256()
-  b256():
-    v368 = load v303 -> u1
-    constrain v368 == u1 1
-    v369 = allocate -> &mut [u8; 32]
-    store v301 at v369
-    v370 = load v369 -> [u8; 32]
-    v371 = array_get v12, index u32 0 -> u8
-    v372 = array_get v370, index u32 0 -> u8
-    v373 = xor v371, v372
-    v374 = array_set v370, index u32 0, value v373
-    store v374 at v369
-    v375 = load v369 -> [u8; 32]
-    v376 = array_get v12, index u32 1 -> u8
-    v377 = array_get v375, index u32 1 -> u8
-    v378 = xor v376, v377
-    v379 = array_set v375, index u32 1, value v378
-    store v379 at v369
-    v380 = load v369 -> [u8; 32]
-    v381 = array_get v12, index u32 2 -> u8
-    v382 = array_get v380, index u32 2 -> u8
-    v383 = xor v381, v382
-    v384 = array_set v380, index u32 2, value v383
-    store v384 at v369
-    v385 = load v369 -> [u8; 32]
-    v386 = array_get v12, index u32 3 -> u8
-    v387 = array_get v385, index u32 3 -> u8
-    v388 = xor v386, v387
-    v389 = array_set v385, index u32 3, value v388
-    store v389 at v369
-    v390 = load v369 -> [u8; 32]
-    v391 = array_get v12, index u32 4 -> u8
-    v392 = array_get v390, index u32 4 -> u8
-    v393 = xor v391, v392
-    v394 = array_set v390, index u32 4, value v393
-    store v394 at v369
-    v395 = load v369 -> [u8; 32]
-    v396 = array_get v12, index u32 5 -> u8
-    v397 = array_get v395, index u32 5 -> u8
-    v398 = xor v396, v397
-    v399 = array_set v395, index u32 5, value v398
-    store v399 at v369
-    v400 = load v369 -> [u8; 32]
-    v401 = array_get v12, index u32 6 -> u8
-    v402 = array_get v400, index u32 6 -> u8
-    v403 = xor v401, v402
-    v404 = array_set v400, index u32 6, value v403
-    store v404 at v369
-    v405 = load v369 -> [u8; 32]
-    v406 = array_get v12, index u32 7 -> u8
-    v407 = array_get v405, index u32 7 -> u8
-    v408 = xor v406, v407
-    v409 = array_set v405, index u32 7, value v408
-    store v409 at v369
-    v410 = load v369 -> [u8; 32]
-    v411 = array_get v12, index u32 8 -> u8
-    v412 = array_get v410, index u32 8 -> u8
-    v413 = xor v411, v412
-    v414 = array_set v410, index u32 8, value v413
-    store v414 at v369
-    v415 = load v369 -> [u8; 32]
-    v416 = array_get v12, index u32 9 -> u8
-    v417 = array_get v415, index u32 9 -> u8
-    v418 = xor v416, v417
-    v419 = array_set v415, index u32 9, value v418
-    store v419 at v369
-    v420 = load v369 -> [u8; 32]
-    v421 = array_get v12, index u32 10 -> u8
-    v422 = array_get v420, index u32 10 -> u8
-    v423 = xor v421, v422
-    v424 = array_set v420, index u32 10, value v423
-    store v424 at v369
-    v425 = load v369 -> [u8; 32]
-    v426 = array_get v12, index u32 11 -> u8
-    v427 = array_get v425, index u32 11 -> u8
-    v428 = xor v426, v427
-    v429 = array_set v425, index u32 11, value v428
-    store v429 at v369
-    v430 = load v369 -> [u8; 32]
-    v431 = array_get v12, index u32 12 -> u8
-    v432 = array_get v430, index u32 12 -> u8
-    v433 = xor v431, v432
-    v434 = array_set v430, index u32 12, value v433
-    store v434 at v369
-    v435 = load v369 -> [u8; 32]
-    v436 = array_get v12, index u32 13 -> u8
-    v437 = array_get v435, index u32 13 -> u8
-    v438 = xor v436, v437
-    v439 = array_set v435, index u32 13, value v438
-    store v439 at v369
-    v440 = load v369 -> [u8; 32]
-    v441 = array_get v12, index u32 14 -> u8
-    v442 = array_get v440, index u32 14 -> u8
-    v443 = xor v441, v442
-    v444 = array_set v440, index u32 14, value v443
-    store v444 at v369
-    v445 = load v369 -> [u8; 32]
-    v446 = array_get v12, index u32 15 -> u8
-    v447 = array_get v445, index u32 15 -> u8
-    v448 = xor v446, v447
-    v449 = array_set v445, index u32 15, value v448
-    store v449 at v369
-    v450 = load v369 -> [u8; 32]
-    v451 = array_get v12, index u32 16 -> u8
-    v452 = array_get v450, index u32 16 -> u8
-    v453 = xor v451, v452
-    v454 = array_set v450, index u32 16, value v453
-    store v454 at v369
-    v455 = load v369 -> [u8; 32]
-    v456 = array_get v12, index u32 17 -> u8
-    v457 = array_get v455, index u32 17 -> u8
-    v458 = xor v456, v457
-    v459 = array_set v455, index u32 17, value v458
-    store v459 at v369
-    v460 = load v369 -> [u8; 32]
-    v461 = array_get v12, index u32 18 -> u8
-    v462 = array_get v460, index u32 18 -> u8
-    v463 = xor v461, v462
-    v464 = array_set v460, index u32 18, value v463
-    store v464 at v369
-    v465 = load v369 -> [u8; 32]
-    v466 = array_get v12, index u32 19 -> u8
-    v467 = array_get v465, index u32 19 -> u8
-    v468 = xor v466, v467
-    v469 = array_set v465, index u32 19, value v468
-    store v469 at v369
-    v470 = load v369 -> [u8; 32]
-    v471 = array_get v12, index u32 20 -> u8
-    v472 = array_get v470, index u32 20 -> u8
-    v473 = xor v471, v472
-    v474 = array_set v470, index u32 20, value v473
-    store v474 at v369
-    v475 = load v369 -> [u8; 32]
-    v476 = array_get v12, index u32 21 -> u8
-    v477 = array_get v475, index u32 21 -> u8
-    v478 = xor v476, v477
-    v479 = array_set v475, index u32 21, value v478
-    store v479 at v369
-    v480 = load v369 -> [u8; 32]
-    v481 = array_get v12, index u32 22 -> u8
-    v482 = array_get v480, index u32 22 -> u8
-    v483 = xor v481, v482
-    v484 = array_set v480, index u32 22, value v483
-    store v484 at v369
-    v485 = load v369 -> [u8; 32]
-    v486 = array_get v12, index u32 23 -> u8
-    v487 = array_get v485, index u32 23 -> u8
-    v488 = xor v486, v487
-    v489 = array_set v485, index u32 23, value v488
-    store v489 at v369
-    v490 = load v369 -> [u8; 32]
-    v491 = array_get v12, index u32 24 -> u8
-    v492 = array_get v490, index u32 24 -> u8
-    v493 = xor v491, v492
-    v494 = array_set v490, index u32 24, value v493
-    store v494 at v369
-    v495 = load v369 -> [u8; 32]
-    v496 = array_get v12, index u32 25 -> u8
-    v497 = array_get v495, index u32 25 -> u8
-    v498 = xor v496, v497
-    v499 = array_set v495, index u32 25, value v498
-    store v499 at v369
-    v500 = load v369 -> [u8; 32]
-    v501 = array_get v12, index u32 26 -> u8
-    v502 = array_get v500, index u32 26 -> u8
-    v503 = xor v501, v502
-    v504 = array_set v500, index u32 26, value v503
-    store v504 at v369
-    v505 = load v369 -> [u8; 32]
-    v506 = array_get v12, index u32 27 -> u8
-    v507 = array_get v505, index u32 27 -> u8
-    v508 = xor v506, v507
-    v509 = array_set v505, index u32 27, value v508
-    store v509 at v369
-    v510 = load v369 -> [u8; 32]
-    v511 = array_get v12, index u32 28 -> u8
-    v512 = array_get v510, index u32 28 -> u8
-    v513 = xor v511, v512
-    v514 = array_set v510, index u32 28, value v513
-    store v514 at v369
-    v515 = load v369 -> [u8; 32]
-    v516 = array_get v12, index u32 29 -> u8
-    v517 = array_get v515, index u32 29 -> u8
-    v518 = xor v516, v517
-    v519 = array_set v515, index u32 29, value v518
-    store v519 at v369
-    v520 = load v369 -> [u8; 32]
-    v521 = array_get v12, index u32 30 -> u8
-    v522 = array_get v520, index u32 30 -> u8
-    v523 = xor v521, v522
-    v524 = array_set v520, index u32 30, value v523
-    store v524 at v369
-    v525 = load v369 -> [u8; 32]
-    v526 = array_get v12, index u32 31 -> u8
-    v527 = array_get v525, index u32 31 -> u8
-    v528 = xor v526, v527
-    v529 = array_set v525, index u32 31, value v528
-    store v529 at v369
-    jmp b257()
-  b257():
-    v530 = load v369 -> [u8; 32]
-    v531 = allocate -> &mut Field
-    store Field 1 at v531
-    v533 = allocate -> &mut Field
-    store Field 0 at v533
-    v534 = allocate -> &mut Field
-    store Field 0 at v534
-    v535 = load v533 -> Field
-    v536 = array_get v530, index u32 15 -> u8
-    v537 = cast v536 as Field
-    v538 = load v531 -> Field
-    v539 = mul v537, v538
-    v540 = add v535, v539
-    store v540 at v533
-    v541 = load v534 -> Field
-    v542 = array_get v530, index u32 31 -> u8
-    v543 = cast v542 as Field
-    v544 = mul v543, v538
-    v545 = add v541, v544
-    store v545 at v534
-    v547 = mul v538, Field 256
-    store v547 at v531
-    v548 = load v533 -> Field
-    v549 = array_get v530, index u32 14 -> u8
-    v550 = cast v549 as Field
-    v551 = load v531 -> Field
-    v552 = mul v550, v551
-    v553 = add v548, v552
-    store v553 at v533
-    v554 = load v534 -> Field
-    v555 = array_get v530, index u32 30 -> u8
-    v556 = cast v555 as Field
-    v557 = mul v556, v551
-    v558 = add v554, v557
-    store v558 at v534
-    v559 = mul v551, Field 256
-    store v559 at v531
-    v560 = load v533 -> Field
-    v561 = array_get v530, index u32 13 -> u8
-    v562 = cast v561 as Field
-    v563 = load v531 -> Field
-    v564 = mul v562, v563
-    v565 = add v560, v564
-    store v565 at v533
-    v566 = load v534 -> Field
-    v567 = array_get v530, index u32 29 -> u8
-    v568 = cast v567 as Field
-    v569 = mul v568, v563
-    v570 = add v566, v569
-    store v570 at v534
-    v571 = mul v563, Field 256
-    store v571 at v531
-    v572 = load v533 -> Field
-    v573 = array_get v530, index u32 12 -> u8
-    v574 = cast v573 as Field
-    v575 = load v531 -> Field
-    v576 = mul v574, v575
-    v577 = add v572, v576
-    store v577 at v533
-    v578 = load v534 -> Field
-    v579 = array_get v530, index u32 28 -> u8
-    v580 = cast v579 as Field
-    v581 = mul v580, v575
-    v582 = add v578, v581
-    store v582 at v534
-    v583 = mul v575, Field 256
-    store v583 at v531
-    v584 = load v533 -> Field
-    v585 = array_get v530, index u32 11 -> u8
-    v586 = cast v585 as Field
-    v587 = load v531 -> Field
-    v588 = mul v586, v587
-    v589 = add v584, v588
-    store v589 at v533
-    v590 = load v534 -> Field
-    v591 = array_get v530, index u32 27 -> u8
-    v592 = cast v591 as Field
-    v593 = mul v592, v587
-    v594 = add v590, v593
-    store v594 at v534
-    v595 = mul v587, Field 256
-    store v595 at v531
-    v596 = load v533 -> Field
-    v597 = array_get v530, index u32 10 -> u8
-    v598 = cast v597 as Field
-    v599 = load v531 -> Field
-    v600 = mul v598, v599
-    v601 = add v596, v600
-    store v601 at v533
-    v602 = load v534 -> Field
-    v603 = array_get v530, index u32 26 -> u8
-    v604 = cast v603 as Field
-    v605 = mul v604, v599
-    v606 = add v602, v605
-    store v606 at v534
-    v607 = mul v599, Field 256
-    store v607 at v531
-    v608 = load v533 -> Field
-    v609 = array_get v530, index u32 9 -> u8
-    v610 = cast v609 as Field
-    v611 = load v531 -> Field
-    v612 = mul v610, v611
-    v613 = add v608, v612
-    store v613 at v533
-    v614 = load v534 -> Field
-    v615 = array_get v530, index u32 25 -> u8
-    v616 = cast v615 as Field
-    v617 = mul v616, v611
-    v618 = add v614, v617
-    store v618 at v534
-    v619 = mul v611, Field 256
-    store v619 at v531
-    v620 = load v533 -> Field
-    v621 = array_get v530, index u32 8 -> u8
-    v622 = cast v621 as Field
-    v623 = load v531 -> Field
-    v624 = mul v622, v623
-    v625 = add v620, v624
-    store v625 at v533
-    v626 = load v534 -> Field
-    v627 = array_get v530, index u32 24 -> u8
-    v628 = cast v627 as Field
-    v629 = mul v628, v623
-    v630 = add v626, v629
-    store v630 at v534
-    v631 = mul v623, Field 256
-    store v631 at v531
-    v632 = load v533 -> Field
-    v633 = array_get v530, index u32 7 -> u8
-    v634 = cast v633 as Field
-    v635 = load v531 -> Field
-    v636 = mul v634, v635
-    v637 = add v632, v636
-    store v637 at v533
-    v638 = load v534 -> Field
-    v639 = array_get v530, index u32 23 -> u8
-    v640 = cast v639 as Field
-    v641 = mul v640, v635
-    v642 = add v638, v641
-    store v642 at v534
-    v643 = mul v635, Field 256
-    store v643 at v531
-    v644 = load v533 -> Field
-    v645 = array_get v530, index u32 6 -> u8
-    v646 = cast v645 as Field
-    v647 = load v531 -> Field
-    v648 = mul v646, v647
-    v649 = add v644, v648
-    store v649 at v533
-    v650 = load v534 -> Field
-    v651 = array_get v530, index u32 22 -> u8
-    v652 = cast v651 as Field
-    v653 = mul v652, v647
-    v654 = add v650, v653
-    store v654 at v534
-    v655 = mul v647, Field 256
-    store v655 at v531
-    v656 = load v533 -> Field
-    v657 = array_get v530, index u32 5 -> u8
-    v658 = cast v657 as Field
-    v659 = load v531 -> Field
-    v660 = mul v658, v659
-    v661 = add v656, v660
-    store v661 at v533
-    v662 = load v534 -> Field
-    v663 = array_get v530, index u32 21 -> u8
-    v664 = cast v663 as Field
-    v665 = mul v664, v659
-    v666 = add v662, v665
-    store v666 at v534
-    v667 = mul v659, Field 256
-    store v667 at v531
-    v668 = load v533 -> Field
-    v669 = array_get v530, index u32 4 -> u8
-    v670 = cast v669 as Field
-    v671 = load v531 -> Field
-    v672 = mul v670, v671
-    v673 = add v668, v672
-    store v673 at v533
-    v674 = load v534 -> Field
-    v675 = array_get v530, index u32 20 -> u8
-    v676 = cast v675 as Field
-    v677 = mul v676, v671
-    v678 = add v674, v677
-    store v678 at v534
-    v679 = mul v671, Field 256
-    store v679 at v531
-    v680 = load v533 -> Field
-    v681 = array_get v530, index u32 3 -> u8
-    v682 = cast v681 as Field
-    v683 = load v531 -> Field
-    v684 = mul v682, v683
-    v685 = add v680, v684
-    store v685 at v533
-    v686 = load v534 -> Field
-    v687 = array_get v530, index u32 19 -> u8
-    v688 = cast v687 as Field
-    v689 = mul v688, v683
-    v690 = add v686, v689
-    store v690 at v534
-    v691 = mul v683, Field 256
-    store v691 at v531
-    v692 = load v533 -> Field
-    v693 = array_get v530, index u32 2 -> u8
-    v694 = cast v693 as Field
-    v695 = load v531 -> Field
-    v696 = mul v694, v695
-    v697 = add v692, v696
-    store v697 at v533
-    v698 = load v534 -> Field
-    v699 = array_get v530, index u32 18 -> u8
-    v700 = cast v699 as Field
-    v701 = mul v700, v695
-    v702 = add v698, v701
-    store v702 at v534
-    v703 = mul v695, Field 256
-    store v703 at v531
-    v704 = load v533 -> Field
-    v705 = array_get v530, index u32 1 -> u8
-    v706 = cast v705 as Field
-    v707 = load v531 -> Field
-    v708 = mul v706, v707
-    v709 = add v704, v708
-    store v709 at v533
-    v710 = load v534 -> Field
-    v711 = array_get v530, index u32 17 -> u8
-    v712 = cast v711 as Field
-    v713 = mul v712, v707
-    v714 = add v710, v713
-    store v714 at v534
-    v715 = mul v707, Field 256
-    store v715 at v531
-    v716 = load v533 -> Field
-    v717 = array_get v530, index u32 0 -> u8
-    v718 = cast v717 as Field
-    v719 = load v531 -> Field
-    v720 = mul v718, v719
-    v721 = add v716, v720
-    store v721 at v533
-    v722 = load v534 -> Field
-    v723 = array_get v530, index u32 16 -> u8
-    v724 = cast v723 as Field
-    v725 = mul v724, v719
-    v726 = add v722, v725
-    store v726 at v534
-    v727 = mul v719, Field 256
-    store v727 at v531
-    jmp b258()
-  b258():
-    v728 = load v534 -> Field
-    v729 = load v533 -> Field
-    v730 = load v531 -> Field
-    v731 = mul v729, v730
-    v732 = add v728, v731
-    store v732 at v8
-    v733 = allocate -> &mut Field
-    store Field 0 at v733
-    v734 = eq v4, Field 0
-    jmpif v734 then: b263, else: b259
-  b259():
-    v736 = call f1(v4, Field 0) -> u1
-    jmpif v736 then: b261, else: b260
-  b260():
-    v738, v739 = call f3(v4) -> (Field, Field)
-    range_check v738 to 128 bits
-    range_check v739 to 128 bits
-    v741 = mul Field 340282366920938463463374607431768211456, v739
-    v742 = add v738, v741
-    v743 = eq v4, v742
-    constrain v4 == v742
-    v746 = call f2(Field 53438638232309528389504892708671455233, v738) -> u1
-    v747 = sub Field 53438638232309528389504892708671455233, v738
-    v748 = sub v747, Field 1
-    v749 = cast v746 as Field
-    v750 = mul v749, Field 340282366920938463463374607431768211456
-    v751 = add v748, v750
-    v753 = sub Field 64323764613183177041862057485226039389, v739
-    v754 = cast v746 as Field
-    v755 = sub v753, v754
-    range_check v751 to 128 bits
-    range_check v755 to 128 bits
-    v757, v758 = call f3(Field 0) -> (Field, Field)
-    range_check v757 to 128 bits
-    range_check v758 to 128 bits
-    v759 = mul Field 340282366920938463463374607431768211456, v758
-    v760 = add v757, v759
-    v761 = eq Field 0, v760
-    constrain Field 0 == v760
-    v763 = call f2(Field 53438638232309528389504892708671455233, v757) -> u1
-    v764 = sub Field 53438638232309528389504892708671455233, v757
-    v765 = sub v764, Field 1
-    v766 = cast v763 as Field
-    v767 = mul v766, Field 340282366920938463463374607431768211456
-    v768 = add v765, v767
-    v769 = sub Field 64323764613183177041862057485226039389, v758
-    v770 = cast v763 as Field
-    v771 = sub v769, v770
-    range_check v768 to 128 bits
-    range_check v771 to 128 bits
-    v773 = call f2(v738, v757) -> u1
-    v774 = sub v738, v757
-    v775 = sub v774, Field 1
-    v776 = cast v773 as Field
-    v777 = mul v776, Field 340282366920938463463374607431768211456
-    v778 = add v775, v777
-    v779 = sub v739, v758
-    v780 = cast v773 as Field
-    v781 = sub v779, v780
-    range_check v778 to 128 bits
-    range_check v781 to 128 bits
-    jmp b262(u1 1)
-  b261():
-    v783, v784 = call f3(Field 0) -> (Field, Field)
-    range_check v783 to 128 bits
-    range_check v784 to 128 bits
-    v785 = mul Field 340282366920938463463374607431768211456, v784
-    v786 = add v783, v785
-    v787 = eq Field 0, v786
-    constrain Field 0 == v786
-    v789 = call f2(Field 53438638232309528389504892708671455233, v783) -> u1
-    v790 = sub Field 53438638232309528389504892708671455233, v783
-    v791 = sub v790, Field 1
-    v792 = cast v789 as Field
-    v793 = mul v792, Field 340282366920938463463374607431768211456
-    v794 = add v791, v793
-    v795 = sub Field 64323764613183177041862057485226039389, v784
-    v796 = cast v789 as Field
-    v797 = sub v795, v796
-    range_check v794 to 128 bits
-    range_check v797 to 128 bits
-    v799, v800 = call f3(v4) -> (Field, Field)
-    range_check v799 to 128 bits
-    range_check v800 to 128 bits
-    v801 = mul Field 340282366920938463463374607431768211456, v800
-    v802 = add v799, v801
-    v803 = eq v4, v802
-    constrain v4 == v802
-    v805 = call f2(Field 53438638232309528389504892708671455233, v799) -> u1
-    v806 = sub Field 53438638232309528389504892708671455233, v799
-    v807 = sub v806, Field 1
-    v808 = cast v805 as Field
-    v809 = mul v808, Field 340282366920938463463374607431768211456
-    v810 = add v807, v809
-    v811 = sub Field 64323764613183177041862057485226039389, v800
-    v812 = cast v805 as Field
-    v813 = sub v811, v812
-    range_check v810 to 128 bits
-    range_check v813 to 128 bits
-    v815 = call f2(v783, v799) -> u1
-    v816 = sub v783, v799
-    v817 = sub v816, Field 1
-    v818 = cast v815 as Field
-    v819 = mul v818, Field 340282366920938463463374607431768211456
-    v820 = add v817, v819
-    v821 = sub v784, v800
-    v822 = cast v815 as Field
-    v823 = sub v821, v822
-    range_check v820 to 128 bits
-    range_check v823 to 128 bits
-    jmp b262(u1 0)
-  b262(v5: u1):
-    jmp b264(v5)
-  b263():
-    jmp b264(u1 0)
-  b264(v6: u1):
-    jmpif v6 then: b265, else: b266
-  b265():
-    store Field 1 at v733
-    jmp b266()
-  b266():
-    v824 = load v733 -> Field
-    v825 = load v8 -> Field
-    v826 = sub v824, v825
-    return v826
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Simplifying (2nd):
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v7 = allocate -> &mut Field
-    v8 = allocate -> &mut Field
-    store Field 0 at v8
-    v12 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v42 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v43 = allocate -> &mut u1
-    store u1 0 at v43
-    v45 = load v43 -> u1
-    v46 = not v45
-    jmpif v46 then: b1, else: b4
-  b1():
-    v48 = array_get v12, index u32 0 -> u8
-    v49 = eq v48, u8 48
-    v50 = not v49
-    jmpif v50 then: b2, else: b3
-  b2():
-    v51 = array_get v12, index u32 0 -> u8
-    v52 = lt v51, u8 48
-    constrain v52 == u1 1
-    store u1 1 at v43
-    jmp b3()
-  b3():
-    jmp b4()
-  b4():
-    v54 = load v43 -> u1
-    v55 = not v54
-    jmpif v55 then: b5, else: b8
-  b5():
-    v57 = array_get v12, index u32 1 -> u8
-    v58 = eq v57, u8 100
-    v59 = not v58
-    jmpif v59 then: b6, else: b7
-  b6():
-    v60 = array_get v12, index u32 1 -> u8
-    v61 = lt v60, u8 100
-    constrain v61 == u1 1
-    store u1 1 at v43
-    jmp b7()
-  b7():
-    jmp b8()
-  b8():
-    v62 = load v43 -> u1
-    v63 = not v62
-    jmpif v63 then: b9, else: b12
-  b9():
-    v65 = array_get v12, index u32 2 -> u8
-    v66 = eq v65, u8 78
-    v67 = not v66
-    jmpif v67 then: b10, else: b11
-  b10():
-    v68 = array_get v12, index u32 2 -> u8
-    v69 = lt v68, u8 78
-    constrain v69 == u1 1
-    store u1 1 at v43
-    jmp b11()
-  b11():
-    jmp b12()
-  b12():
-    v70 = load v43 -> u1
-    v71 = not v70
-    jmpif v71 then: b13, else: b16
-  b13():
-    v73 = array_get v12, index u32 3 -> u8
-    v74 = eq v73, u8 114
-    v75 = not v74
-    jmpif v75 then: b14, else: b15
-  b14():
-    v76 = array_get v12, index u32 3 -> u8
-    v77 = lt v76, u8 114
-    constrain v77 == u1 1
-    store u1 1 at v43
-    jmp b15()
-  b15():
-    jmp b16()
-  b16():
-    v78 = load v43 -> u1
-    v79 = not v78
-    jmpif v79 then: b17, else: b20
-  b17():
-    v81 = array_get v12, index u32 4 -> u8
-    v82 = eq v81, u8 225
-    v83 = not v82
-    jmpif v83 then: b18, else: b19
-  b18():
-    v84 = array_get v12, index u32 4 -> u8
-    v85 = lt v84, u8 225
-    constrain v85 == u1 1
-    store u1 1 at v43
-    jmp b19()
-  b19():
-    jmp b20()
-  b20():
-    v86 = load v43 -> u1
-    v87 = not v86
-    jmpif v87 then: b21, else: b24
-  b21():
-    v89 = array_get v12, index u32 5 -> u8
-    v90 = eq v89, u8 49
-    v91 = not v90
-    jmpif v91 then: b22, else: b23
-  b22():
-    v92 = array_get v12, index u32 5 -> u8
-    v93 = lt v92, u8 49
-    constrain v93 == u1 1
-    store u1 1 at v43
-    jmp b23()
-  b23():
-    jmp b24()
-  b24():
-    v94 = load v43 -> u1
-    v95 = not v94
-    jmpif v95 then: b25, else: b28
-  b25():
-    v97 = array_get v12, index u32 6 -> u8
-    v98 = eq v97, u8 160
-    v99 = not v98
-    jmpif v99 then: b26, else: b27
-  b26():
-    v100 = array_get v12, index u32 6 -> u8
-    v101 = lt v100, u8 160
-    constrain v101 == u1 1
-    store u1 1 at v43
-    jmp b27()
-  b27():
-    jmp b28()
-  b28():
-    v102 = load v43 -> u1
-    v103 = not v102
-    jmpif v103 then: b29, else: b32
-  b29():
-    v105 = array_get v12, index u32 7 -> u8
-    v106 = eq v105, u8 41
-    v107 = not v106
-    jmpif v107 then: b30, else: b31
-  b30():
-    v108 = array_get v12, index u32 7 -> u8
-    v109 = lt v108, u8 41
-    constrain v109 == u1 1
-    store u1 1 at v43
-    jmp b31()
-  b31():
-    jmp b32()
-  b32():
-    v110 = load v43 -> u1
-    v111 = not v110
-    jmpif v111 then: b33, else: b36
-  b33():
-    v113 = array_get v12, index u32 8 -> u8
-    v114 = eq v113, u8 184
-    v115 = not v114
-    jmpif v115 then: b34, else: b35
-  b34():
-    v116 = array_get v12, index u32 8 -> u8
-    v117 = lt v116, u8 184
-    constrain v117 == u1 1
-    store u1 1 at v43
-    jmp b35()
-  b35():
-    jmp b36()
-  b36():
-    v118 = load v43 -> u1
-    v119 = not v118
-    jmpif v119 then: b37, else: b40
-  b37():
-    v121 = array_get v12, index u32 9 -> u8
-    v122 = eq v121, u8 80
-    v123 = not v122
-    jmpif v123 then: b38, else: b39
-  b38():
-    v124 = array_get v12, index u32 9 -> u8
-    v125 = lt v124, u8 80
-    constrain v125 == u1 1
-    store u1 1 at v43
-    jmp b39()
-  b39():
-    jmp b40()
-  b40():
-    v126 = load v43 -> u1
-    v127 = not v126
-    jmpif v127 then: b41, else: b44
-  b41():
-    v129 = array_get v12, index u32 10 -> u8
-    v130 = eq v129, u8 69
-    v131 = not v130
-    jmpif v131 then: b42, else: b43
-  b42():
-    v132 = array_get v12, index u32 10 -> u8
-    v133 = lt v132, u8 69
-    constrain v133 == u1 1
-    store u1 1 at v43
-    jmp b43()
-  b43():
-    jmp b44()
-  b44():
-    v134 = load v43 -> u1
-    v135 = not v134
-    jmpif v135 then: b45, else: b48
-  b45():
-    v137 = array_get v12, index u32 11 -> u8
-    v138 = eq v137, u8 182
-    v139 = not v138
-    jmpif v139 then: b46, else: b47
-  b46():
-    v140 = array_get v12, index u32 11 -> u8
-    v141 = lt v140, u8 182
-    constrain v141 == u1 1
-    store u1 1 at v43
-    jmp b47()
-  b47():
-    jmp b48()
-  b48():
-    v142 = load v43 -> u1
-    v143 = not v142
-    jmpif v143 then: b49, else: b52
-  b49():
-    v145 = array_get v12, index u32 12 -> u8
-    v146 = eq v145, u8 129
-    v147 = not v146
-    jmpif v147 then: b50, else: b51
-  b50():
-    v148 = array_get v12, index u32 12 -> u8
-    v149 = lt v148, u8 129
-    constrain v149 == u1 1
-    store u1 1 at v43
-    jmp b51()
-  b51():
-    jmp b52()
-  b52():
-    v150 = load v43 -> u1
-    v151 = not v150
-    jmpif v151 then: b53, else: b56
-  b53():
-    v153 = array_get v12, index u32 13 -> u8
-    v154 = eq v153, u8 129
-    v155 = not v154
-    jmpif v155 then: b54, else: b55
-  b54():
-    v156 = array_get v12, index u32 13 -> u8
-    v157 = lt v156, u8 129
-    constrain v157 == u1 1
-    store u1 1 at v43
-    jmp b55()
-  b55():
-    jmp b56()
-  b56():
-    v158 = load v43 -> u1
-    v159 = not v158
-    jmpif v159 then: b57, else: b60
-  b57():
-    v161 = array_get v12, index u32 14 -> u8
-    v162 = eq v161, u8 88
-    v163 = not v162
-    jmpif v163 then: b58, else: b59
-  b58():
-    v164 = array_get v12, index u32 14 -> u8
-    v165 = lt v164, u8 88
-    constrain v165 == u1 1
-    store u1 1 at v43
-    jmp b59()
-  b59():
-    jmp b60()
-  b60():
-    v166 = load v43 -> u1
-    v167 = not v166
-    jmpif v167 then: b61, else: b64
-  b61():
-    v169 = array_get v12, index u32 15 -> u8
-    v170 = eq v169, u8 93
-    v171 = not v170
-    jmpif v171 then: b62, else: b63
-  b62():
-    v172 = array_get v12, index u32 15 -> u8
-    v173 = lt v172, u8 93
-    constrain v173 == u1 1
-    store u1 1 at v43
-    jmp b63()
-  b63():
-    jmp b64()
-  b64():
-    v174 = load v43 -> u1
-    v175 = not v174
-    jmpif v175 then: b65, else: b68
-  b65():
-    v177 = array_get v12, index u32 16 -> u8
-    v178 = eq v177, u8 40
-    v179 = not v178
-    jmpif v179 then: b66, else: b67
-  b66():
-    v180 = array_get v12, index u32 16 -> u8
-    v181 = lt v180, u8 40
-    constrain v181 == u1 1
-    store u1 1 at v43
-    jmp b67()
-  b67():
-    jmp b68()
-  b68():
-    v182 = load v43 -> u1
-    v183 = not v182
-    jmpif v183 then: b69, else: b72
-  b69():
-    v185 = array_get v12, index u32 17 -> u8
-    v186 = eq v185, u8 51
-    v187 = not v186
-    jmpif v187 then: b70, else: b71
-  b70():
-    v188 = array_get v12, index u32 17 -> u8
-    v189 = lt v188, u8 51
-    constrain v189 == u1 1
-    store u1 1 at v43
-    jmp b71()
-  b71():
-    jmp b72()
-  b72():
-    v190 = load v43 -> u1
-    v191 = not v190
-    jmpif v191 then: b73, else: b76
-  b73():
-    v193 = array_get v12, index u32 18 -> u8
-    v194 = eq v193, u8 232
-    v195 = not v194
-    jmpif v195 then: b74, else: b75
-  b74():
-    v196 = array_get v12, index u32 18 -> u8
-    v197 = lt v196, u8 232
-    constrain v197 == u1 1
-    store u1 1 at v43
-    jmp b75()
-  b75():
-    jmp b76()
-  b76():
-    v198 = load v43 -> u1
-    v199 = not v198
-    jmpif v199 then: b77, else: b80
-  b77():
-    v201 = array_get v12, index u32 19 -> u8
-    v202 = eq v201, u8 72
-    v203 = not v202
-    jmpif v203 then: b78, else: b79
-  b78():
-    v204 = array_get v12, index u32 19 -> u8
-    v205 = lt v204, u8 72
-    constrain v205 == u1 1
-    store u1 1 at v43
-    jmp b79()
-  b79():
-    jmp b80()
-  b80():
-    v206 = load v43 -> u1
-    v207 = not v206
-    jmpif v207 then: b81, else: b84
-  b81():
-    v209 = array_get v12, index u32 20 -> u8
-    v210 = eq v209, u8 121
-    v211 = not v210
-    jmpif v211 then: b82, else: b83
-  b82():
-    v212 = array_get v12, index u32 20 -> u8
-    v213 = lt v212, u8 121
-    constrain v213 == u1 1
-    store u1 1 at v43
-    jmp b83()
-  b83():
-    jmp b84()
-  b84():
-    v214 = load v43 -> u1
-    v215 = not v214
-    jmpif v215 then: b85, else: b88
-  b85():
-    v217 = array_get v12, index u32 21 -> u8
-    v218 = eq v217, u8 185
-    v219 = not v218
-    jmpif v219 then: b86, else: b87
-  b86():
-    v220 = array_get v12, index u32 21 -> u8
-    v221 = lt v220, u8 185
-    constrain v221 == u1 1
-    store u1 1 at v43
-    jmp b87()
-  b87():
-    jmp b88()
-  b88():
-    v222 = load v43 -> u1
-    v223 = not v222
-    jmpif v223 then: b89, else: b92
-  b89():
-    v225 = array_get v12, index u32 22 -> u8
-    v226 = eq v225, u8 112
-    v227 = not v226
-    jmpif v227 then: b90, else: b91
-  b90():
-    v228 = array_get v12, index u32 22 -> u8
-    v229 = lt v228, u8 112
-    constrain v229 == u1 1
-    store u1 1 at v43
-    jmp b91()
-  b91():
-    jmp b92()
-  b92():
-    v230 = load v43 -> u1
-    v231 = not v230
-    jmpif v231 then: b93, else: b96
-  b93():
-    v233 = array_get v12, index u32 23 -> u8
-    v234 = eq v233, u8 145
-    v235 = not v234
-    jmpif v235 then: b94, else: b95
-  b94():
-    v236 = array_get v12, index u32 23 -> u8
-    v237 = lt v236, u8 145
-    constrain v237 == u1 1
-    store u1 1 at v43
-    jmp b95()
-  b95():
-    jmp b96()
-  b96():
-    v238 = load v43 -> u1
-    v239 = not v238
-    jmpif v239 then: b97, else: b100
-  b97():
-    v241 = array_get v12, index u32 24 -> u8
-    v242 = eq v241, u8 67
-    v243 = not v242
-    jmpif v243 then: b98, else: b99
-  b98():
-    v244 = array_get v12, index u32 24 -> u8
-    v245 = lt v244, u8 67
-    constrain v245 == u1 1
-    store u1 1 at v43
-    jmp b99()
-  b99():
-    jmp b100()
-  b100():
-    v246 = load v43 -> u1
-    v247 = not v246
-    jmpif v247 then: b101, else: b104
-  b101():
-    v249 = array_get v12, index u32 25 -> u8
-    v250 = eq v249, u8 225
-    v251 = not v250
-    jmpif v251 then: b102, else: b103
-  b102():
-    v252 = array_get v12, index u32 25 -> u8
-    v253 = lt v252, u8 225
-    constrain v253 == u1 1
-    store u1 1 at v43
-    jmp b103()
-  b103():
-    jmp b104()
-  b104():
-    v254 = load v43 -> u1
-    v255 = not v254
-    jmpif v255 then: b105, else: b108
-  b105():
-    v257 = array_get v12, index u32 26 -> u8
-    v258 = eq v257, u8 245
-    v259 = not v258
-    jmpif v259 then: b106, else: b107
-  b106():
-    v260 = array_get v12, index u32 26 -> u8
-    v261 = lt v260, u8 245
-    constrain v261 == u1 1
-    store u1 1 at v43
-    jmp b107()
-  b107():
-    jmp b108()
-  b108():
-    v262 = load v43 -> u1
-    v263 = not v262
-    jmpif v263 then: b109, else: b112
-  b109():
-    v265 = array_get v12, index u32 27 -> u8
-    v266 = eq v265, u8 147
-    v267 = not v266
-    jmpif v267 then: b110, else: b111
-  b110():
-    v268 = array_get v12, index u32 27 -> u8
-    v269 = lt v268, u8 147
-    constrain v269 == u1 1
-    store u1 1 at v43
-    jmp b111()
-  b111():
-    jmp b112()
-  b112():
-    v270 = load v43 -> u1
-    v271 = not v270
-    jmpif v271 then: b113, else: b116
-  b113():
-    v273 = array_get v12, index u32 28 -> u8
-    v274 = eq v273, u8 240
-    v275 = not v274
-    jmpif v275 then: b114, else: b115
-  b114():
-    v276 = array_get v12, index u32 28 -> u8
-    v277 = lt v276, u8 240
-    constrain v277 == u1 1
-    store u1 1 at v43
-    jmp b115()
-  b115():
-    jmp b116()
-  b116():
-    v278 = load v43 -> u1
-    v279 = not v278
-    jmpif v279 then: b117, else: b120
-  b117():
-    v281 = array_get v12, index u32 29 -> u8
-    v282 = eq v281, u8 0
-    v283 = not v282
-    jmpif v283 then: b118, else: b119
-  b118():
-    v284 = array_get v12, index u32 29 -> u8
-    constrain u1 0 == u1 1
-    store u1 1 at v43
-    jmp b119()
-  b119():
-    jmp b120()
-  b120():
-    v285 = load v43 -> u1
-    v286 = not v285
-    jmpif v286 then: b121, else: b124
-  b121():
-    v288 = array_get v12, index u32 30 -> u8
-    v289 = eq v288, u8 0
-    v290 = not v289
-    jmpif v290 then: b122, else: b123
-  b122():
-    v291 = array_get v12, index u32 30 -> u8
-    constrain u1 0 == u1 1
-    store u1 1 at v43
-    jmp b123()
-  b123():
-    jmp b124()
-  b124():
-    v292 = load v43 -> u1
-    v293 = not v292
-    jmpif v293 then: b125, else: b128
-  b125():
-    v295 = array_get v12, index u32 31 -> u8
-    v296 = eq v295, u8 1
-    v297 = not v296
-    jmpif v297 then: b126, else: b127
-  b126():
-    v298 = array_get v12, index u32 31 -> u8
-    v299 = eq v298, u8 0
-    constrain v298 == u8 0
-    store u1 1 at v43
-    jmp b127()
-  b127():
-    jmp b128()
-  b128():
-    v300 = load v43 -> u1
-    constrain v300 == u1 1
-    v301 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v302 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v303 = allocate -> &mut u1
-    store u1 0 at v303
-    v304 = load v303 -> u1
-    v305 = not v304
-    jmpif v305 then: b129, else: b130
-  b129():
-    store u1 1 at v303
-    jmp b130()
-  b130():
-    v306 = load v303 -> u1
-    v307 = not v306
-    jmpif v307 then: b131, else: b132
-  b131():
-    store u1 1 at v303
-    jmp b132()
-  b132():
-    v308 = load v303 -> u1
-    v309 = not v308
-    jmpif v309 then: b133, else: b134
-  b133():
-    store u1 1 at v303
-    jmp b134()
-  b134():
-    v310 = load v303 -> u1
-    v311 = not v310
-    jmpif v311 then: b135, else: b136
-  b135():
-    store u1 1 at v303
-    jmp b136()
-  b136():
-    v312 = load v303 -> u1
-    v313 = not v312
-    jmpif v313 then: b137, else: b138
-  b137():
-    store u1 1 at v303
-    jmp b138()
-  b138():
-    v314 = load v303 -> u1
-    v315 = not v314
-    jmpif v315 then: b139, else: b140
-  b139():
-    store u1 1 at v303
-    jmp b140()
-  b140():
-    v316 = load v303 -> u1
-    v317 = not v316
-    jmpif v317 then: b141, else: b142
-  b141():
-    store u1 1 at v303
-    jmp b142()
-  b142():
-    v318 = load v303 -> u1
-    v319 = not v318
-    jmpif v319 then: b143, else: b144
-  b143():
-    store u1 1 at v303
-    jmp b144()
-  b144():
-    v320 = load v303 -> u1
-    v321 = not v320
-    jmpif v321 then: b145, else: b146
-  b145():
-    store u1 1 at v303
-    jmp b146()
-  b146():
-    v322 = load v303 -> u1
-    v323 = not v322
-    jmpif v323 then: b147, else: b148
-  b147():
-    store u1 1 at v303
-    jmp b148()
-  b148():
-    v324 = load v303 -> u1
-    v325 = not v324
-    jmpif v325 then: b149, else: b150
-  b149():
-    store u1 1 at v303
-    jmp b150()
-  b150():
-    v326 = load v303 -> u1
-    v327 = not v326
-    jmpif v327 then: b151, else: b152
-  b151():
-    store u1 1 at v303
-    jmp b152()
-  b152():
-    v328 = load v303 -> u1
-    v329 = not v328
-    jmpif v329 then: b153, else: b154
-  b153():
-    store u1 1 at v303
-    jmp b154()
-  b154():
-    v330 = load v303 -> u1
-    v331 = not v330
-    jmpif v331 then: b155, else: b156
-  b155():
-    store u1 1 at v303
-    jmp b156()
-  b156():
-    v332 = load v303 -> u1
-    v333 = not v332
-    jmpif v333 then: b157, else: b158
-  b157():
-    store u1 1 at v303
-    jmp b158()
-  b158():
-    v334 = load v303 -> u1
-    v335 = not v334
-    jmpif v335 then: b159, else: b160
-  b159():
-    store u1 1 at v303
-    jmp b160()
-  b160():
-    v336 = load v303 -> u1
-    v337 = not v336
-    jmpif v337 then: b161, else: b162
-  b161():
-    store u1 1 at v303
-    jmp b162()
-  b162():
-    v338 = load v303 -> u1
-    v339 = not v338
-    jmpif v339 then: b163, else: b164
-  b163():
-    store u1 1 at v303
-    jmp b164()
-  b164():
-    v340 = load v303 -> u1
-    v341 = not v340
-    jmpif v341 then: b165, else: b166
-  b165():
-    store u1 1 at v303
-    jmp b166()
-  b166():
-    v342 = load v303 -> u1
-    v343 = not v342
-    jmpif v343 then: b167, else: b168
-  b167():
-    store u1 1 at v303
-    jmp b168()
-  b168():
-    v344 = load v303 -> u1
-    v345 = not v344
-    jmpif v345 then: b169, else: b170
-  b169():
-    store u1 1 at v303
-    jmp b170()
-  b170():
-    v346 = load v303 -> u1
-    v347 = not v346
-    jmpif v347 then: b171, else: b172
-  b171():
-    store u1 1 at v303
-    jmp b172()
-  b172():
-    v348 = load v303 -> u1
-    v349 = not v348
-    jmpif v349 then: b173, else: b174
-  b173():
-    store u1 1 at v303
-    jmp b174()
-  b174():
-    v350 = load v303 -> u1
-    v351 = not v350
-    jmpif v351 then: b175, else: b176
-  b175():
-    store u1 1 at v303
-    jmp b176()
-  b176():
-    v352 = load v303 -> u1
-    v353 = not v352
-    jmpif v353 then: b177, else: b178
-  b177():
-    store u1 1 at v303
-    jmp b178()
-  b178():
-    v354 = load v303 -> u1
-    v355 = not v354
-    jmpif v355 then: b179, else: b180
-  b179():
-    store u1 1 at v303
-    jmp b180()
-  b180():
-    v356 = load v303 -> u1
-    v357 = not v356
-    jmpif v357 then: b181, else: b182
-  b181():
-    store u1 1 at v303
-    jmp b182()
-  b182():
-    v358 = load v303 -> u1
-    v359 = not v358
-    jmpif v359 then: b183, else: b184
-  b183():
-    store u1 1 at v303
-    jmp b184()
-  b184():
-    v360 = load v303 -> u1
-    v361 = not v360
-    jmpif v361 then: b185, else: b186
-  b185():
-    store u1 1 at v303
-    jmp b186()
-  b186():
-    v362 = load v303 -> u1
-    v363 = not v362
-    jmpif v363 then: b187, else: b188
-  b187():
-    jmp b188()
-  b188():
-    v364 = load v303 -> u1
-    v365 = not v364
-    jmpif v365 then: b189, else: b190
-  b189():
-    jmp b190()
-  b190():
-    v366 = load v303 -> u1
-    v367 = not v366
-    jmpif v367 then: b191, else: b192
-  b191():
-    store u1 1 at v303
-    jmp b192()
-  b192():
-    v368 = load v303 -> u1
-    constrain v368 == u1 1
-    v369 = allocate -> &mut [u8; 32]
-    store v301 at v369
-    v370 = load v369 -> [u8; 32]
-    v371 = array_get v12, index u32 0 -> u8
-    v372 = array_get v370, index u32 0 -> u8
-    v373 = xor v371, v372
-    v374 = array_set v370, index u32 0, value v373
-    store v374 at v369
-    v375 = load v369 -> [u8; 32]
-    v376 = array_get v12, index u32 1 -> u8
-    v377 = array_get v375, index u32 1 -> u8
-    v378 = xor v376, v377
-    v379 = array_set v375, index u32 1, value v378
-    store v379 at v369
-    v380 = load v369 -> [u8; 32]
-    v381 = array_get v12, index u32 2 -> u8
-    v382 = array_get v380, index u32 2 -> u8
-    v383 = xor v381, v382
-    v384 = array_set v380, index u32 2, value v383
-    store v384 at v369
-    v385 = load v369 -> [u8; 32]
-    v386 = array_get v12, index u32 3 -> u8
-    v387 = array_get v385, index u32 3 -> u8
-    v388 = xor v386, v387
-    v389 = array_set v385, index u32 3, value v388
-    store v389 at v369
-    v390 = load v369 -> [u8; 32]
-    v391 = array_get v12, index u32 4 -> u8
-    v392 = array_get v390, index u32 4 -> u8
-    v393 = xor v391, v392
-    v394 = array_set v390, index u32 4, value v393
-    store v394 at v369
-    v395 = load v369 -> [u8; 32]
-    v396 = array_get v12, index u32 5 -> u8
-    v397 = array_get v395, index u32 5 -> u8
-    v398 = xor v396, v397
-    v399 = array_set v395, index u32 5, value v398
-    store v399 at v369
-    v400 = load v369 -> [u8; 32]
-    v401 = array_get v12, index u32 6 -> u8
-    v402 = array_get v400, index u32 6 -> u8
-    v403 = xor v401, v402
-    v404 = array_set v400, index u32 6, value v403
-    store v404 at v369
-    v405 = load v369 -> [u8; 32]
-    v406 = array_get v12, index u32 7 -> u8
-    v407 = array_get v405, index u32 7 -> u8
-    v408 = xor v406, v407
-    v409 = array_set v405, index u32 7, value v408
-    store v409 at v369
-    v410 = load v369 -> [u8; 32]
-    v411 = array_get v12, index u32 8 -> u8
-    v412 = array_get v410, index u32 8 -> u8
-    v413 = xor v411, v412
-    v414 = array_set v410, index u32 8, value v413
-    store v414 at v369
-    v415 = load v369 -> [u8; 32]
-    v416 = array_get v12, index u32 9 -> u8
-    v417 = array_get v415, index u32 9 -> u8
-    v418 = xor v416, v417
-    v419 = array_set v415, index u32 9, value v418
-    store v419 at v369
-    v420 = load v369 -> [u8; 32]
-    v421 = array_get v12, index u32 10 -> u8
-    v422 = array_get v420, index u32 10 -> u8
-    v423 = xor v421, v422
-    v424 = array_set v420, index u32 10, value v423
-    store v424 at v369
-    v425 = load v369 -> [u8; 32]
-    v426 = array_get v12, index u32 11 -> u8
-    v427 = array_get v425, index u32 11 -> u8
-    v428 = xor v426, v427
-    v429 = array_set v425, index u32 11, value v428
-    store v429 at v369
-    v430 = load v369 -> [u8; 32]
-    v431 = array_get v12, index u32 12 -> u8
-    v432 = array_get v430, index u32 12 -> u8
-    v433 = xor v431, v432
-    v434 = array_set v430, index u32 12, value v433
-    store v434 at v369
-    v435 = load v369 -> [u8; 32]
-    v436 = array_get v12, index u32 13 -> u8
-    v437 = array_get v435, index u32 13 -> u8
-    v438 = xor v436, v437
-    v439 = array_set v435, index u32 13, value v438
-    store v439 at v369
-    v440 = load v369 -> [u8; 32]
-    v441 = array_get v12, index u32 14 -> u8
-    v442 = array_get v440, index u32 14 -> u8
-    v443 = xor v441, v442
-    v444 = array_set v440, index u32 14, value v443
-    store v444 at v369
-    v445 = load v369 -> [u8; 32]
-    v446 = array_get v12, index u32 15 -> u8
-    v447 = array_get v445, index u32 15 -> u8
-    v448 = xor v446, v447
-    v449 = array_set v445, index u32 15, value v448
-    store v449 at v369
-    v450 = load v369 -> [u8; 32]
-    v451 = array_get v12, index u32 16 -> u8
-    v452 = array_get v450, index u32 16 -> u8
-    v453 = xor v451, v452
-    v454 = array_set v450, index u32 16, value v453
-    store v454 at v369
-    v455 = load v369 -> [u8; 32]
-    v456 = array_get v12, index u32 17 -> u8
-    v457 = array_get v455, index u32 17 -> u8
-    v458 = xor v456, v457
-    v459 = array_set v455, index u32 17, value v458
-    store v459 at v369
-    v460 = load v369 -> [u8; 32]
-    v461 = array_get v12, index u32 18 -> u8
-    v462 = array_get v460, index u32 18 -> u8
-    v463 = xor v461, v462
-    v464 = array_set v460, index u32 18, value v463
-    store v464 at v369
-    v465 = load v369 -> [u8; 32]
-    v466 = array_get v12, index u32 19 -> u8
-    v467 = array_get v465, index u32 19 -> u8
-    v468 = xor v466, v467
-    v469 = array_set v465, index u32 19, value v468
-    store v469 at v369
-    v470 = load v369 -> [u8; 32]
-    v471 = array_get v12, index u32 20 -> u8
-    v472 = array_get v470, index u32 20 -> u8
-    v473 = xor v471, v472
-    v474 = array_set v470, index u32 20, value v473
-    store v474 at v369
-    v475 = load v369 -> [u8; 32]
-    v476 = array_get v12, index u32 21 -> u8
-    v477 = array_get v475, index u32 21 -> u8
-    v478 = xor v476, v477
-    v479 = array_set v475, index u32 21, value v478
-    store v479 at v369
-    v480 = load v369 -> [u8; 32]
-    v481 = array_get v12, index u32 22 -> u8
-    v482 = array_get v480, index u32 22 -> u8
-    v483 = xor v481, v482
-    v484 = array_set v480, index u32 22, value v483
-    store v484 at v369
-    v485 = load v369 -> [u8; 32]
-    v486 = array_get v12, index u32 23 -> u8
-    v487 = array_get v485, index u32 23 -> u8
-    v488 = xor v486, v487
-    v489 = array_set v485, index u32 23, value v488
-    store v489 at v369
-    v490 = load v369 -> [u8; 32]
-    v491 = array_get v12, index u32 24 -> u8
-    v492 = array_get v490, index u32 24 -> u8
-    v493 = xor v491, v492
-    v494 = array_set v490, index u32 24, value v493
-    store v494 at v369
-    v495 = load v369 -> [u8; 32]
-    v496 = array_get v12, index u32 25 -> u8
-    v497 = array_get v495, index u32 25 -> u8
-    v498 = xor v496, v497
-    v499 = array_set v495, index u32 25, value v498
-    store v499 at v369
-    v500 = load v369 -> [u8; 32]
-    v501 = array_get v12, index u32 26 -> u8
-    v502 = array_get v500, index u32 26 -> u8
-    v503 = xor v501, v502
-    v504 = array_set v500, index u32 26, value v503
-    store v504 at v369
-    v505 = load v369 -> [u8; 32]
-    v506 = array_get v12, index u32 27 -> u8
-    v507 = array_get v505, index u32 27 -> u8
-    v508 = xor v506, v507
-    v509 = array_set v505, index u32 27, value v508
-    store v509 at v369
-    v510 = load v369 -> [u8; 32]
-    v511 = array_get v12, index u32 28 -> u8
-    v512 = array_get v510, index u32 28 -> u8
-    v513 = xor v511, v512
-    v514 = array_set v510, index u32 28, value v513
-    store v514 at v369
-    v515 = load v369 -> [u8; 32]
-    v516 = array_get v12, index u32 29 -> u8
-    v517 = array_get v515, index u32 29 -> u8
-    v518 = xor v516, v517
-    v519 = array_set v515, index u32 29, value v518
-    store v519 at v369
-    v520 = load v369 -> [u8; 32]
-    v521 = array_get v12, index u32 30 -> u8
-    v522 = array_get v520, index u32 30 -> u8
-    v523 = xor v521, v522
-    v524 = array_set v520, index u32 30, value v523
-    store v524 at v369
-    v525 = load v369 -> [u8; 32]
-    v526 = array_get v12, index u32 31 -> u8
-    v527 = array_get v525, index u32 31 -> u8
-    v528 = xor v526, v527
-    v529 = array_set v525, index u32 31, value v528
-    store v529 at v369
-    v530 = load v369 -> [u8; 32]
-    v531 = allocate -> &mut Field
-    store Field 1 at v531
-    v533 = allocate -> &mut Field
-    store Field 0 at v533
-    v534 = allocate -> &mut Field
-    store Field 0 at v534
-    v535 = load v533 -> Field
-    v536 = array_get v530, index u32 15 -> u8
-    v537 = cast v536 as Field
-    v538 = load v531 -> Field
-    v539 = mul v537, v538
-    v540 = add v535, v539
-    store v540 at v533
-    v541 = load v534 -> Field
-    v542 = array_get v530, index u32 31 -> u8
-    v543 = cast v542 as Field
-    v544 = mul v543, v538
-    v545 = add v541, v544
-    store v545 at v534
-    v547 = mul v538, Field 256
-    store v547 at v531
-    v548 = load v533 -> Field
-    v549 = array_get v530, index u32 14 -> u8
-    v550 = cast v549 as Field
-    v551 = load v531 -> Field
-    v552 = mul v550, v551
-    v553 = add v548, v552
-    store v553 at v533
-    v554 = load v534 -> Field
-    v555 = array_get v530, index u32 30 -> u8
-    v556 = cast v555 as Field
-    v557 = mul v556, v551
-    v558 = add v554, v557
-    store v558 at v534
-    v559 = mul v551, Field 256
-    store v559 at v531
-    v560 = load v533 -> Field
-    v561 = array_get v530, index u32 13 -> u8
-    v562 = cast v561 as Field
-    v563 = load v531 -> Field
-    v564 = mul v562, v563
-    v565 = add v560, v564
-    store v565 at v533
-    v566 = load v534 -> Field
-    v567 = array_get v530, index u32 29 -> u8
-    v568 = cast v567 as Field
-    v569 = mul v568, v563
-    v570 = add v566, v569
-    store v570 at v534
-    v571 = mul v563, Field 256
-    store v571 at v531
-    v572 = load v533 -> Field
-    v573 = array_get v530, index u32 12 -> u8
-    v574 = cast v573 as Field
-    v575 = load v531 -> Field
-    v576 = mul v574, v575
-    v577 = add v572, v576
-    store v577 at v533
-    v578 = load v534 -> Field
-    v579 = array_get v530, index u32 28 -> u8
-    v580 = cast v579 as Field
-    v581 = mul v580, v575
-    v582 = add v578, v581
-    store v582 at v534
-    v583 = mul v575, Field 256
-    store v583 at v531
-    v584 = load v533 -> Field
-    v585 = array_get v530, index u32 11 -> u8
-    v586 = cast v585 as Field
-    v587 = load v531 -> Field
-    v588 = mul v586, v587
-    v589 = add v584, v588
-    store v589 at v533
-    v590 = load v534 -> Field
-    v591 = array_get v530, index u32 27 -> u8
-    v592 = cast v591 as Field
-    v593 = mul v592, v587
-    v594 = add v590, v593
-    store v594 at v534
-    v595 = mul v587, Field 256
-    store v595 at v531
-    v596 = load v533 -> Field
-    v597 = array_get v530, index u32 10 -> u8
-    v598 = cast v597 as Field
-    v599 = load v531 -> Field
-    v600 = mul v598, v599
-    v601 = add v596, v600
-    store v601 at v533
-    v602 = load v534 -> Field
-    v603 = array_get v530, index u32 26 -> u8
-    v604 = cast v603 as Field
-    v605 = mul v604, v599
-    v606 = add v602, v605
-    store v606 at v534
-    v607 = mul v599, Field 256
-    store v607 at v531
-    v608 = load v533 -> Field
-    v609 = array_get v530, index u32 9 -> u8
-    v610 = cast v609 as Field
-    v611 = load v531 -> Field
-    v612 = mul v610, v611
-    v613 = add v608, v612
-    store v613 at v533
-    v614 = load v534 -> Field
-    v615 = array_get v530, index u32 25 -> u8
-    v616 = cast v615 as Field
-    v617 = mul v616, v611
-    v618 = add v614, v617
-    store v618 at v534
-    v619 = mul v611, Field 256
-    store v619 at v531
-    v620 = load v533 -> Field
-    v621 = array_get v530, index u32 8 -> u8
-    v622 = cast v621 as Field
-    v623 = load v531 -> Field
-    v624 = mul v622, v623
-    v625 = add v620, v624
-    store v625 at v533
-    v626 = load v534 -> Field
-    v627 = array_get v530, index u32 24 -> u8
-    v628 = cast v627 as Field
-    v629 = mul v628, v623
-    v630 = add v626, v629
-    store v630 at v534
-    v631 = mul v623, Field 256
-    store v631 at v531
-    v632 = load v533 -> Field
-    v633 = array_get v530, index u32 7 -> u8
-    v634 = cast v633 as Field
-    v635 = load v531 -> Field
-    v636 = mul v634, v635
-    v637 = add v632, v636
-    store v637 at v533
-    v638 = load v534 -> Field
-    v639 = array_get v530, index u32 23 -> u8
-    v640 = cast v639 as Field
-    v641 = mul v640, v635
-    v642 = add v638, v641
-    store v642 at v534
-    v643 = mul v635, Field 256
-    store v643 at v531
-    v644 = load v533 -> Field
-    v645 = array_get v530, index u32 6 -> u8
-    v646 = cast v645 as Field
-    v647 = load v531 -> Field
-    v648 = mul v646, v647
-    v649 = add v644, v648
-    store v649 at v533
-    v650 = load v534 -> Field
-    v651 = array_get v530, index u32 22 -> u8
-    v652 = cast v651 as Field
-    v653 = mul v652, v647
-    v654 = add v650, v653
-    store v654 at v534
-    v655 = mul v647, Field 256
-    store v655 at v531
-    v656 = load v533 -> Field
-    v657 = array_get v530, index u32 5 -> u8
-    v658 = cast v657 as Field
-    v659 = load v531 -> Field
-    v660 = mul v658, v659
-    v661 = add v656, v660
-    store v661 at v533
-    v662 = load v534 -> Field
-    v663 = array_get v530, index u32 21 -> u8
-    v664 = cast v663 as Field
-    v665 = mul v664, v659
-    v666 = add v662, v665
-    store v666 at v534
-    v667 = mul v659, Field 256
-    store v667 at v531
-    v668 = load v533 -> Field
-    v669 = array_get v530, index u32 4 -> u8
-    v670 = cast v669 as Field
-    v671 = load v531 -> Field
-    v672 = mul v670, v671
-    v673 = add v668, v672
-    store v673 at v533
-    v674 = load v534 -> Field
-    v675 = array_get v530, index u32 20 -> u8
-    v676 = cast v675 as Field
-    v677 = mul v676, v671
-    v678 = add v674, v677
-    store v678 at v534
-    v679 = mul v671, Field 256
-    store v679 at v531
-    v680 = load v533 -> Field
-    v681 = array_get v530, index u32 3 -> u8
-    v682 = cast v681 as Field
-    v683 = load v531 -> Field
-    v684 = mul v682, v683
-    v685 = add v680, v684
-    store v685 at v533
-    v686 = load v534 -> Field
-    v687 = array_get v530, index u32 19 -> u8
-    v688 = cast v687 as Field
-    v689 = mul v688, v683
-    v690 = add v686, v689
-    store v690 at v534
-    v691 = mul v683, Field 256
-    store v691 at v531
-    v692 = load v533 -> Field
-    v693 = array_get v530, index u32 2 -> u8
-    v694 = cast v693 as Field
-    v695 = load v531 -> Field
-    v696 = mul v694, v695
-    v697 = add v692, v696
-    store v697 at v533
-    v698 = load v534 -> Field
-    v699 = array_get v530, index u32 18 -> u8
-    v700 = cast v699 as Field
-    v701 = mul v700, v695
-    v702 = add v698, v701
-    store v702 at v534
-    v703 = mul v695, Field 256
-    store v703 at v531
-    v704 = load v533 -> Field
-    v705 = array_get v530, index u32 1 -> u8
-    v706 = cast v705 as Field
-    v707 = load v531 -> Field
-    v708 = mul v706, v707
-    v709 = add v704, v708
-    store v709 at v533
-    v710 = load v534 -> Field
-    v711 = array_get v530, index u32 17 -> u8
-    v712 = cast v711 as Field
-    v713 = mul v712, v707
-    v714 = add v710, v713
-    store v714 at v534
-    v715 = mul v707, Field 256
-    store v715 at v531
-    v716 = load v533 -> Field
-    v717 = array_get v530, index u32 0 -> u8
-    v718 = cast v717 as Field
-    v719 = load v531 -> Field
-    v720 = mul v718, v719
-    v721 = add v716, v720
-    store v721 at v533
-    v722 = load v534 -> Field
-    v723 = array_get v530, index u32 16 -> u8
-    v724 = cast v723 as Field
-    v725 = mul v724, v719
-    v726 = add v722, v725
-    store v726 at v534
-    v727 = mul v719, Field 256
-    store v727 at v531
-    v728 = load v534 -> Field
-    v729 = load v533 -> Field
-    v730 = load v531 -> Field
-    v731 = mul v729, v730
-    v732 = add v728, v731
-    store v732 at v8
-    v733 = allocate -> &mut Field
-    store Field 0 at v733
-    v734 = eq v4, Field 0
-    jmpif v734 then: b197, else: b193
-  b193():
-    v736 = call f1(v4, Field 0) -> u1
-    jmpif v736 then: b195, else: b194
-  b194():
-    v738, v739 = call f3(v4) -> (Field, Field)
-    range_check v738 to 128 bits
-    range_check v739 to 128 bits
-    v741 = mul Field 340282366920938463463374607431768211456, v739
-    v742 = add v738, v741
-    v743 = eq v4, v742
-    constrain v4 == v742
-    v746 = call f2(Field 53438638232309528389504892708671455233, v738) -> u1
-    v747 = sub Field 53438638232309528389504892708671455233, v738
-    v748 = sub v747, Field 1
-    v749 = cast v746 as Field
-    v750 = mul v749, Field 340282366920938463463374607431768211456
-    v751 = add v748, v750
-    v753 = sub Field 64323764613183177041862057485226039389, v739
-    v754 = cast v746 as Field
-    v755 = sub v753, v754
-    range_check v751 to 128 bits
-    range_check v755 to 128 bits
-    v757, v758 = call f3(Field 0) -> (Field, Field)
-    range_check v757 to 128 bits
-    range_check v758 to 128 bits
-    v759 = mul Field 340282366920938463463374607431768211456, v758
-    v760 = add v757, v759
-    v761 = eq Field 0, v760
-    constrain Field 0 == v760
-    v763 = call f2(Field 53438638232309528389504892708671455233, v757) -> u1
-    v764 = sub Field 53438638232309528389504892708671455233, v757
-    v765 = sub v764, Field 1
-    v766 = cast v763 as Field
-    v767 = mul v766, Field 340282366920938463463374607431768211456
-    v768 = add v765, v767
-    v769 = sub Field 64323764613183177041862057485226039389, v758
-    v770 = cast v763 as Field
-    v771 = sub v769, v770
-    range_check v768 to 128 bits
-    range_check v771 to 128 bits
-    v773 = call f2(v738, v757) -> u1
-    v774 = sub v738, v757
-    v775 = sub v774, Field 1
-    v776 = cast v773 as Field
-    v777 = mul v776, Field 340282366920938463463374607431768211456
-    v778 = add v775, v777
-    v779 = sub v739, v758
-    v780 = cast v773 as Field
-    v781 = sub v779, v780
-    range_check v778 to 128 bits
-    range_check v781 to 128 bits
-    jmp b196(u1 1)
-  b195():
-    v783, v784 = call f3(Field 0) -> (Field, Field)
-    range_check v783 to 128 bits
-    range_check v784 to 128 bits
-    v785 = mul Field 340282366920938463463374607431768211456, v784
-    v786 = add v783, v785
-    v787 = eq Field 0, v786
-    constrain Field 0 == v786
-    v789 = call f2(Field 53438638232309528389504892708671455233, v783) -> u1
-    v790 = sub Field 53438638232309528389504892708671455233, v783
-    v791 = sub v790, Field 1
-    v792 = cast v789 as Field
-    v793 = mul v792, Field 340282366920938463463374607431768211456
-    v794 = add v791, v793
-    v795 = sub Field 64323764613183177041862057485226039389, v784
-    v796 = cast v789 as Field
-    v797 = sub v795, v796
-    range_check v794 to 128 bits
-    range_check v797 to 128 bits
-    v799, v800 = call f3(v4) -> (Field, Field)
-    range_check v799 to 128 bits
-    range_check v800 to 128 bits
-    v801 = mul Field 340282366920938463463374607431768211456, v800
-    v802 = add v799, v801
-    v803 = eq v4, v802
-    constrain v4 == v802
-    v805 = call f2(Field 53438638232309528389504892708671455233, v799) -> u1
-    v806 = sub Field 53438638232309528389504892708671455233, v799
-    v807 = sub v806, Field 1
-    v808 = cast v805 as Field
-    v809 = mul v808, Field 340282366920938463463374607431768211456
-    v810 = add v807, v809
-    v811 = sub Field 64323764613183177041862057485226039389, v800
-    v812 = cast v805 as Field
-    v813 = sub v811, v812
-    range_check v810 to 128 bits
-    range_check v813 to 128 bits
-    v815 = call f2(v783, v799) -> u1
-    v816 = sub v783, v799
-    v817 = sub v816, Field 1
-    v818 = cast v815 as Field
-    v819 = mul v818, Field 340282366920938463463374607431768211456
-    v820 = add v817, v819
-    v821 = sub v784, v800
-    v822 = cast v815 as Field
-    v823 = sub v821, v822
-    range_check v820 to 128 bits
-    range_check v823 to 128 bits
-    jmp b196(u1 0)
-  b196(v5: u1):
-    jmp b198(v5)
-  b197():
-    jmp b198(u1 0)
-  b198(v6: u1):
-    jmpif v6 then: b199, else: b200
-  b199():
-    store Field 1 at v733
-    jmp b200()
-  b200():
-    v824 = load v733 -> Field
-    v825 = load v8 -> Field
-    v826 = sub v824, v825
-    return v826
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Mem2Reg (2nd):
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v7 = allocate -> &mut Field
-    v8 = allocate -> &mut Field
-    v11 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v41 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v42 = allocate -> &mut u1
-    store u1 0 at v42
-    jmpif u1 1 then: b1, else: b4
-  b1():
-    v46 = array_get v11, index u32 0 -> u8
-    v47 = eq v46, u8 48
-    v48 = not v47
-    jmpif v48 then: b2, else: b3
-  b2():
-    v49 = array_get v11, index u32 0 -> u8
-    v50 = lt v49, u8 48
-    constrain v50 == u1 1
-    store u1 1 at v42
-    jmp b3()
-  b3():
-    jmp b4()
-  b4():
-    v51 = load v42 -> u1
-    v52 = not v51
-    jmpif v52 then: b5, else: b8
-  b5():
-    v54 = array_get v11, index u32 1 -> u8
-    v55 = eq v54, u8 100
-    v56 = not v55
-    jmpif v56 then: b6, else: b7
-  b6():
-    v57 = array_get v11, index u32 1 -> u8
-    v58 = lt v57, u8 100
-    constrain v58 == u1 1
-    store u1 1 at v42
-    jmp b7()
-  b7():
-    jmp b8()
-  b8():
-    v59 = load v42 -> u1
-    v60 = not v59
-    jmpif v60 then: b9, else: b12
-  b9():
-    v62 = array_get v11, index u32 2 -> u8
-    v63 = eq v62, u8 78
-    v64 = not v63
-    jmpif v64 then: b10, else: b11
-  b10():
-    v65 = array_get v11, index u32 2 -> u8
-    v66 = lt v65, u8 78
-    constrain v66 == u1 1
-    store u1 1 at v42
-    jmp b11()
-  b11():
-    jmp b12()
-  b12():
-    v67 = load v42 -> u1
-    v68 = not v67
-    jmpif v68 then: b13, else: b16
-  b13():
-    v70 = array_get v11, index u32 3 -> u8
-    v71 = eq v70, u8 114
-    v72 = not v71
-    jmpif v72 then: b14, else: b15
-  b14():
-    v73 = array_get v11, index u32 3 -> u8
-    v74 = lt v73, u8 114
-    constrain v74 == u1 1
-    store u1 1 at v42
-    jmp b15()
-  b15():
-    jmp b16()
-  b16():
-    v75 = load v42 -> u1
-    v76 = not v75
-    jmpif v76 then: b17, else: b20
-  b17():
-    v78 = array_get v11, index u32 4 -> u8
-    v79 = eq v78, u8 225
-    v80 = not v79
-    jmpif v80 then: b18, else: b19
-  b18():
-    v81 = array_get v11, index u32 4 -> u8
-    v82 = lt v81, u8 225
-    constrain v82 == u1 1
-    store u1 1 at v42
-    jmp b19()
-  b19():
-    jmp b20()
-  b20():
-    v83 = load v42 -> u1
-    v84 = not v83
-    jmpif v84 then: b21, else: b24
-  b21():
-    v86 = array_get v11, index u32 5 -> u8
-    v87 = eq v86, u8 49
-    v88 = not v87
-    jmpif v88 then: b22, else: b23
-  b22():
-    v89 = array_get v11, index u32 5 -> u8
-    v90 = lt v89, u8 49
-    constrain v90 == u1 1
-    store u1 1 at v42
-    jmp b23()
-  b23():
-    jmp b24()
-  b24():
-    v91 = load v42 -> u1
-    v92 = not v91
-    jmpif v92 then: b25, else: b28
-  b25():
-    v94 = array_get v11, index u32 6 -> u8
-    v95 = eq v94, u8 160
-    v96 = not v95
-    jmpif v96 then: b26, else: b27
-  b26():
-    v97 = array_get v11, index u32 6 -> u8
-    v98 = lt v97, u8 160
-    constrain v98 == u1 1
-    store u1 1 at v42
-    jmp b27()
-  b27():
-    jmp b28()
-  b28():
-    v99 = load v42 -> u1
-    v100 = not v99
-    jmpif v100 then: b29, else: b32
-  b29():
-    v102 = array_get v11, index u32 7 -> u8
-    v103 = eq v102, u8 41
-    v104 = not v103
-    jmpif v104 then: b30, else: b31
-  b30():
-    v105 = array_get v11, index u32 7 -> u8
-    v106 = lt v105, u8 41
-    constrain v106 == u1 1
-    store u1 1 at v42
-    jmp b31()
-  b31():
-    jmp b32()
-  b32():
-    v107 = load v42 -> u1
-    v108 = not v107
-    jmpif v108 then: b33, else: b36
-  b33():
-    v110 = array_get v11, index u32 8 -> u8
-    v111 = eq v110, u8 184
-    v112 = not v111
-    jmpif v112 then: b34, else: b35
-  b34():
-    v113 = array_get v11, index u32 8 -> u8
-    v114 = lt v113, u8 184
-    constrain v114 == u1 1
-    store u1 1 at v42
-    jmp b35()
-  b35():
-    jmp b36()
-  b36():
-    v115 = load v42 -> u1
-    v116 = not v115
-    jmpif v116 then: b37, else: b40
-  b37():
-    v118 = array_get v11, index u32 9 -> u8
-    v119 = eq v118, u8 80
-    v120 = not v119
-    jmpif v120 then: b38, else: b39
-  b38():
-    v121 = array_get v11, index u32 9 -> u8
-    v122 = lt v121, u8 80
-    constrain v122 == u1 1
-    store u1 1 at v42
-    jmp b39()
-  b39():
-    jmp b40()
-  b40():
-    v123 = load v42 -> u1
-    v124 = not v123
-    jmpif v124 then: b41, else: b44
-  b41():
-    v126 = array_get v11, index u32 10 -> u8
-    v127 = eq v126, u8 69
-    v128 = not v127
-    jmpif v128 then: b42, else: b43
-  b42():
-    v129 = array_get v11, index u32 10 -> u8
-    v130 = lt v129, u8 69
-    constrain v130 == u1 1
-    store u1 1 at v42
-    jmp b43()
-  b43():
-    jmp b44()
-  b44():
-    v131 = load v42 -> u1
-    v132 = not v131
-    jmpif v132 then: b45, else: b48
-  b45():
-    v134 = array_get v11, index u32 11 -> u8
-    v135 = eq v134, u8 182
-    v136 = not v135
-    jmpif v136 then: b46, else: b47
-  b46():
-    v137 = array_get v11, index u32 11 -> u8
-    v138 = lt v137, u8 182
-    constrain v138 == u1 1
-    store u1 1 at v42
-    jmp b47()
-  b47():
-    jmp b48()
-  b48():
-    v139 = load v42 -> u1
-    v140 = not v139
-    jmpif v140 then: b49, else: b52
-  b49():
-    v142 = array_get v11, index u32 12 -> u8
-    v143 = eq v142, u8 129
-    v144 = not v143
-    jmpif v144 then: b50, else: b51
-  b50():
-    v145 = array_get v11, index u32 12 -> u8
-    v146 = lt v145, u8 129
-    constrain v146 == u1 1
-    store u1 1 at v42
-    jmp b51()
-  b51():
-    jmp b52()
-  b52():
-    v147 = load v42 -> u1
-    v148 = not v147
-    jmpif v148 then: b53, else: b56
-  b53():
-    v150 = array_get v11, index u32 13 -> u8
-    v151 = eq v150, u8 129
-    v152 = not v151
-    jmpif v152 then: b54, else: b55
-  b54():
-    v153 = array_get v11, index u32 13 -> u8
-    v154 = lt v153, u8 129
-    constrain v154 == u1 1
-    store u1 1 at v42
-    jmp b55()
-  b55():
-    jmp b56()
-  b56():
-    v155 = load v42 -> u1
-    v156 = not v155
-    jmpif v156 then: b57, else: b60
-  b57():
-    v158 = array_get v11, index u32 14 -> u8
-    v159 = eq v158, u8 88
-    v160 = not v159
-    jmpif v160 then: b58, else: b59
-  b58():
-    v161 = array_get v11, index u32 14 -> u8
-    v162 = lt v161, u8 88
-    constrain v162 == u1 1
-    store u1 1 at v42
-    jmp b59()
-  b59():
-    jmp b60()
-  b60():
-    v163 = load v42 -> u1
-    v164 = not v163
-    jmpif v164 then: b61, else: b64
-  b61():
-    v166 = array_get v11, index u32 15 -> u8
-    v167 = eq v166, u8 93
-    v168 = not v167
-    jmpif v168 then: b62, else: b63
-  b62():
-    v169 = array_get v11, index u32 15 -> u8
-    v170 = lt v169, u8 93
-    constrain v170 == u1 1
-    store u1 1 at v42
-    jmp b63()
-  b63():
-    jmp b64()
-  b64():
-    v171 = load v42 -> u1
-    v172 = not v171
-    jmpif v172 then: b65, else: b68
-  b65():
-    v174 = array_get v11, index u32 16 -> u8
-    v175 = eq v174, u8 40
-    v176 = not v175
-    jmpif v176 then: b66, else: b67
-  b66():
-    v177 = array_get v11, index u32 16 -> u8
-    v178 = lt v177, u8 40
-    constrain v178 == u1 1
-    store u1 1 at v42
-    jmp b67()
-  b67():
-    jmp b68()
-  b68():
-    v179 = load v42 -> u1
-    v180 = not v179
-    jmpif v180 then: b69, else: b72
-  b69():
-    v182 = array_get v11, index u32 17 -> u8
-    v183 = eq v182, u8 51
-    v184 = not v183
-    jmpif v184 then: b70, else: b71
-  b70():
-    v185 = array_get v11, index u32 17 -> u8
-    v186 = lt v185, u8 51
-    constrain v186 == u1 1
-    store u1 1 at v42
-    jmp b71()
-  b71():
-    jmp b72()
-  b72():
-    v187 = load v42 -> u1
-    v188 = not v187
-    jmpif v188 then: b73, else: b76
-  b73():
-    v190 = array_get v11, index u32 18 -> u8
-    v191 = eq v190, u8 232
-    v192 = not v191
-    jmpif v192 then: b74, else: b75
-  b74():
-    v193 = array_get v11, index u32 18 -> u8
-    v194 = lt v193, u8 232
-    constrain v194 == u1 1
-    store u1 1 at v42
-    jmp b75()
-  b75():
-    jmp b76()
-  b76():
-    v195 = load v42 -> u1
-    v196 = not v195
-    jmpif v196 then: b77, else: b80
-  b77():
-    v198 = array_get v11, index u32 19 -> u8
-    v199 = eq v198, u8 72
-    v200 = not v199
-    jmpif v200 then: b78, else: b79
-  b78():
-    v201 = array_get v11, index u32 19 -> u8
-    v202 = lt v201, u8 72
-    constrain v202 == u1 1
-    store u1 1 at v42
-    jmp b79()
-  b79():
-    jmp b80()
-  b80():
-    v203 = load v42 -> u1
-    v204 = not v203
-    jmpif v204 then: b81, else: b84
-  b81():
-    v206 = array_get v11, index u32 20 -> u8
-    v207 = eq v206, u8 121
-    v208 = not v207
-    jmpif v208 then: b82, else: b83
-  b82():
-    v209 = array_get v11, index u32 20 -> u8
-    v210 = lt v209, u8 121
-    constrain v210 == u1 1
-    store u1 1 at v42
-    jmp b83()
-  b83():
-    jmp b84()
-  b84():
-    v211 = load v42 -> u1
-    v212 = not v211
-    jmpif v212 then: b85, else: b88
-  b85():
-    v214 = array_get v11, index u32 21 -> u8
-    v215 = eq v214, u8 185
-    v216 = not v215
-    jmpif v216 then: b86, else: b87
-  b86():
-    v217 = array_get v11, index u32 21 -> u8
-    v218 = lt v217, u8 185
-    constrain v218 == u1 1
-    store u1 1 at v42
-    jmp b87()
-  b87():
-    jmp b88()
-  b88():
-    v219 = load v42 -> u1
-    v220 = not v219
-    jmpif v220 then: b89, else: b92
-  b89():
-    v222 = array_get v11, index u32 22 -> u8
-    v223 = eq v222, u8 112
-    v224 = not v223
-    jmpif v224 then: b90, else: b91
-  b90():
-    v225 = array_get v11, index u32 22 -> u8
-    v226 = lt v225, u8 112
-    constrain v226 == u1 1
-    store u1 1 at v42
-    jmp b91()
-  b91():
-    jmp b92()
-  b92():
-    v227 = load v42 -> u1
-    v228 = not v227
-    jmpif v228 then: b93, else: b96
-  b93():
-    v230 = array_get v11, index u32 23 -> u8
-    v231 = eq v230, u8 145
-    v232 = not v231
-    jmpif v232 then: b94, else: b95
-  b94():
-    v233 = array_get v11, index u32 23 -> u8
-    v234 = lt v233, u8 145
-    constrain v234 == u1 1
-    store u1 1 at v42
-    jmp b95()
-  b95():
-    jmp b96()
-  b96():
-    v235 = load v42 -> u1
-    v236 = not v235
-    jmpif v236 then: b97, else: b100
-  b97():
-    v238 = array_get v11, index u32 24 -> u8
-    v239 = eq v238, u8 67
-    v240 = not v239
-    jmpif v240 then: b98, else: b99
-  b98():
-    v241 = array_get v11, index u32 24 -> u8
-    v242 = lt v241, u8 67
-    constrain v242 == u1 1
-    store u1 1 at v42
-    jmp b99()
-  b99():
-    jmp b100()
-  b100():
-    v243 = load v42 -> u1
-    v244 = not v243
-    jmpif v244 then: b101, else: b104
-  b101():
-    v246 = array_get v11, index u32 25 -> u8
-    v247 = eq v246, u8 225
-    v248 = not v247
-    jmpif v248 then: b102, else: b103
-  b102():
-    v249 = array_get v11, index u32 25 -> u8
-    v250 = lt v249, u8 225
-    constrain v250 == u1 1
-    store u1 1 at v42
-    jmp b103()
-  b103():
-    jmp b104()
-  b104():
-    v251 = load v42 -> u1
-    v252 = not v251
-    jmpif v252 then: b105, else: b108
-  b105():
-    v254 = array_get v11, index u32 26 -> u8
-    v255 = eq v254, u8 245
-    v256 = not v255
-    jmpif v256 then: b106, else: b107
-  b106():
-    v257 = array_get v11, index u32 26 -> u8
-    v258 = lt v257, u8 245
-    constrain v258 == u1 1
-    store u1 1 at v42
-    jmp b107()
-  b107():
-    jmp b108()
-  b108():
-    v259 = load v42 -> u1
-    v260 = not v259
-    jmpif v260 then: b109, else: b112
-  b109():
-    v262 = array_get v11, index u32 27 -> u8
-    v263 = eq v262, u8 147
-    v264 = not v263
-    jmpif v264 then: b110, else: b111
-  b110():
-    v265 = array_get v11, index u32 27 -> u8
-    v266 = lt v265, u8 147
-    constrain v266 == u1 1
-    store u1 1 at v42
-    jmp b111()
-  b111():
-    jmp b112()
-  b112():
-    v267 = load v42 -> u1
-    v268 = not v267
-    jmpif v268 then: b113, else: b116
-  b113():
-    v270 = array_get v11, index u32 28 -> u8
-    v271 = eq v270, u8 240
-    v272 = not v271
-    jmpif v272 then: b114, else: b115
-  b114():
-    v273 = array_get v11, index u32 28 -> u8
-    v274 = lt v273, u8 240
-    constrain v274 == u1 1
-    store u1 1 at v42
-    jmp b115()
-  b115():
-    jmp b116()
-  b116():
-    v275 = load v42 -> u1
-    v276 = not v275
-    jmpif v276 then: b117, else: b120
-  b117():
-    v278 = array_get v11, index u32 29 -> u8
-    v279 = eq v278, u8 0
-    v280 = not v279
-    jmpif v280 then: b118, else: b119
-  b118():
-    v281 = array_get v11, index u32 29 -> u8
-    constrain u1 0 == u1 1
-    store u1 1 at v42
-    jmp b119()
-  b119():
-    jmp b120()
-  b120():
-    v282 = load v42 -> u1
-    v283 = not v282
-    jmpif v283 then: b121, else: b124
-  b121():
-    v285 = array_get v11, index u32 30 -> u8
-    v286 = eq v285, u8 0
-    v287 = not v286
-    jmpif v287 then: b122, else: b123
-  b122():
-    v288 = array_get v11, index u32 30 -> u8
-    constrain u1 0 == u1 1
-    store u1 1 at v42
-    jmp b123()
-  b123():
-    jmp b124()
-  b124():
-    v289 = load v42 -> u1
-    v290 = not v289
-    jmpif v290 then: b125, else: b128
-  b125():
-    v292 = array_get v11, index u32 31 -> u8
-    v293 = eq v292, u8 1
-    v294 = not v293
-    jmpif v294 then: b126, else: b127
-  b126():
-    v295 = array_get v11, index u32 31 -> u8
-    v296 = eq v295, u8 0
-    constrain v295 == u8 0
-    store u1 1 at v42
-    jmp b127()
-  b127():
-    jmp b128()
-  b128():
-    v297 = load v42 -> u1
-    constrain v297 == u1 1
-    v298 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v299 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v300 = allocate -> &mut u1
-    store u1 0 at v300
-    jmpif u1 1 then: b129, else: b130
-  b129():
-    store u1 1 at v300
-    jmp b130()
-  b130():
-    v301 = load v300 -> u1
-    v302 = not v301
-    jmpif v302 then: b131, else: b132
-  b131():
-    store u1 1 at v300
-    jmp b132()
-  b132():
-    v303 = load v300 -> u1
-    v304 = not v303
-    jmpif v304 then: b133, else: b134
-  b133():
-    store u1 1 at v300
-    jmp b134()
-  b134():
-    v305 = load v300 -> u1
-    v306 = not v305
-    jmpif v306 then: b135, else: b136
-  b135():
-    store u1 1 at v300
-    jmp b136()
-  b136():
-    v307 = load v300 -> u1
-    v308 = not v307
-    jmpif v308 then: b137, else: b138
-  b137():
-    store u1 1 at v300
-    jmp b138()
-  b138():
-    v309 = load v300 -> u1
-    v310 = not v309
-    jmpif v310 then: b139, else: b140
-  b139():
-    store u1 1 at v300
-    jmp b140()
-  b140():
-    v311 = load v300 -> u1
-    v312 = not v311
-    jmpif v312 then: b141, else: b142
-  b141():
-    store u1 1 at v300
-    jmp b142()
-  b142():
-    v313 = load v300 -> u1
-    v314 = not v313
-    jmpif v314 then: b143, else: b144
-  b143():
-    store u1 1 at v300
-    jmp b144()
-  b144():
-    v315 = load v300 -> u1
-    v316 = not v315
-    jmpif v316 then: b145, else: b146
-  b145():
-    store u1 1 at v300
-    jmp b146()
-  b146():
-    v317 = load v300 -> u1
-    v318 = not v317
-    jmpif v318 then: b147, else: b148
-  b147():
-    store u1 1 at v300
-    jmp b148()
-  b148():
-    v319 = load v300 -> u1
-    v320 = not v319
-    jmpif v320 then: b149, else: b150
-  b149():
-    store u1 1 at v300
-    jmp b150()
-  b150():
-    v321 = load v300 -> u1
-    v322 = not v321
-    jmpif v322 then: b151, else: b152
-  b151():
-    store u1 1 at v300
-    jmp b152()
-  b152():
-    v323 = load v300 -> u1
-    v324 = not v323
-    jmpif v324 then: b153, else: b154
-  b153():
-    store u1 1 at v300
-    jmp b154()
-  b154():
-    v325 = load v300 -> u1
-    v326 = not v325
-    jmpif v326 then: b155, else: b156
-  b155():
-    store u1 1 at v300
-    jmp b156()
-  b156():
-    v327 = load v300 -> u1
-    v328 = not v327
-    jmpif v328 then: b157, else: b158
-  b157():
-    store u1 1 at v300
-    jmp b158()
-  b158():
-    v329 = load v300 -> u1
-    v330 = not v329
-    jmpif v330 then: b159, else: b160
-  b159():
-    store u1 1 at v300
-    jmp b160()
-  b160():
-    v331 = load v300 -> u1
-    v332 = not v331
-    jmpif v332 then: b161, else: b162
-  b161():
-    store u1 1 at v300
-    jmp b162()
-  b162():
-    v333 = load v300 -> u1
-    v334 = not v333
-    jmpif v334 then: b163, else: b164
-  b163():
-    store u1 1 at v300
-    jmp b164()
-  b164():
-    v335 = load v300 -> u1
-    v336 = not v335
-    jmpif v336 then: b165, else: b166
-  b165():
-    store u1 1 at v300
-    jmp b166()
-  b166():
-    v337 = load v300 -> u1
-    v338 = not v337
-    jmpif v338 then: b167, else: b168
-  b167():
-    store u1 1 at v300
-    jmp b168()
-  b168():
-    v339 = load v300 -> u1
-    v340 = not v339
-    jmpif v340 then: b169, else: b170
-  b169():
-    store u1 1 at v300
-    jmp b170()
-  b170():
-    v341 = load v300 -> u1
-    v342 = not v341
-    jmpif v342 then: b171, else: b172
-  b171():
-    store u1 1 at v300
-    jmp b172()
-  b172():
-    v343 = load v300 -> u1
-    v344 = not v343
-    jmpif v344 then: b173, else: b174
-  b173():
-    store u1 1 at v300
-    jmp b174()
-  b174():
-    v345 = load v300 -> u1
-    v346 = not v345
-    jmpif v346 then: b175, else: b176
-  b175():
-    store u1 1 at v300
-    jmp b176()
-  b176():
-    v347 = load v300 -> u1
-    v348 = not v347
-    jmpif v348 then: b177, else: b178
-  b177():
-    store u1 1 at v300
-    jmp b178()
-  b178():
-    v349 = load v300 -> u1
-    v350 = not v349
-    jmpif v350 then: b179, else: b180
-  b179():
-    store u1 1 at v300
-    jmp b180()
-  b180():
-    v351 = load v300 -> u1
-    v352 = not v351
-    jmpif v352 then: b181, else: b182
-  b181():
-    store u1 1 at v300
-    jmp b182()
-  b182():
-    v353 = load v300 -> u1
-    v354 = not v353
-    jmpif v354 then: b183, else: b184
-  b183():
-    store u1 1 at v300
-    jmp b184()
-  b184():
-    v355 = load v300 -> u1
-    v356 = not v355
-    jmpif v356 then: b185, else: b186
-  b185():
-    store u1 1 at v300
-    jmp b186()
-  b186():
-    v357 = load v300 -> u1
-    v358 = not v357
-    jmpif v358 then: b187, else: b188
-  b187():
-    jmp b188()
-  b188():
-    v359 = load v300 -> u1
-    v360 = not v359
-    jmpif v360 then: b189, else: b190
-  b189():
-    jmp b190()
-  b190():
-    v361 = load v300 -> u1
-    v362 = not v361
-    jmpif v362 then: b191, else: b192
-  b191():
-    store u1 1 at v300
-    jmp b192()
-  b192():
-    v363 = load v300 -> u1
-    constrain v363 == u1 1
-    v364 = allocate -> &mut [u8; 32]
-    v365 = array_get v11, index u32 0 -> u8
-    v366 = make_array [v365, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v367 = array_get v11, index u32 1 -> u8
-    v368 = make_array [v365, v367, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v369 = array_get v11, index u32 2 -> u8
-    v370 = make_array [v365, v367, v369, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v371 = array_get v11, index u32 3 -> u8
-    v372 = make_array [v365, v367, v369, v371, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v373 = array_get v11, index u32 4 -> u8
-    v374 = make_array [v365, v367, v369, v371, v373, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v375 = array_get v11, index u32 5 -> u8
-    v376 = make_array [v365, v367, v369, v371, v373, v375, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v377 = array_get v11, index u32 6 -> u8
-    v378 = make_array [v365, v367, v369, v371, v373, v375, v377, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v379 = array_get v11, index u32 7 -> u8
-    v380 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v381 = array_get v11, index u32 8 -> u8
-    v382 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v383 = array_get v11, index u32 9 -> u8
-    v384 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v385 = array_get v11, index u32 10 -> u8
-    v386 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v387 = array_get v11, index u32 11 -> u8
-    v388 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v389 = array_get v11, index u32 12 -> u8
-    v390 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v391 = array_get v11, index u32 13 -> u8
-    v392 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v393 = array_get v11, index u32 14 -> u8
-    v394 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v395 = array_get v11, index u32 15 -> u8
-    v396 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v397 = array_get v11, index u32 16 -> u8
-    v398 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v399 = array_get v11, index u32 17 -> u8
-    v400 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v401 = array_get v11, index u32 18 -> u8
-    v402 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v403 = array_get v11, index u32 19 -> u8
-    v404 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v405 = array_get v11, index u32 20 -> u8
-    v406 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v407 = array_get v11, index u32 21 -> u8
-    v408 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v409 = array_get v11, index u32 22 -> u8
-    v410 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v411 = array_get v11, index u32 23 -> u8
-    v412 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v413 = array_get v11, index u32 24 -> u8
-    v414 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v415 = array_get v11, index u32 25 -> u8
-    v416 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v417 = array_get v11, index u32 26 -> u8
-    v418 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, v417, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v419 = array_get v11, index u32 27 -> u8
-    v420 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, v417, v419, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v421 = array_get v11, index u32 28 -> u8
-    v422 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, v417, v419, v421, u8 0, u8 0, u8 0] : [u8; 32]
-    v423 = array_get v11, index u32 29 -> u8
-    v424 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, v417, v419, v421, v423, u8 0, u8 0] : [u8; 32]
-    v425 = array_get v11, index u32 30 -> u8
-    v426 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, v417, v419, v421, v423, v425, u8 0] : [u8; 32]
-    v427 = array_get v11, index u32 31 -> u8
-    v428 = make_array [v365, v367, v369, v371, v373, v375, v377, v379, v381, v383, v385, v387, v389, v391, v393, v395, v397, v399, v401, v403, v405, v407, v409, v411, v413, v415, v417, v419, v421, v423, v425, v427] : [u8; 32]
-    v429 = allocate -> &mut Field
-    v430 = allocate -> &mut Field
-    v431 = allocate -> &mut Field
-    v432 = cast v395 as Field
-    v433 = cast v427 as Field
-    v434 = cast v393 as Field
-    v436 = mul v434, Field 256
-    v437 = add v432, v436
-    v438 = cast v425 as Field
-    v439 = mul v438, Field 256
-    v440 = add v433, v439
-    v441 = cast v391 as Field
-    v443 = mul v441, Field 65536
-    v444 = add v437, v443
-    v445 = cast v423 as Field
-    v446 = mul v445, Field 65536
-    v447 = add v440, v446
-    v448 = cast v389 as Field
-    v450 = mul v448, Field 16777216
-    v451 = add v444, v450
-    v452 = cast v421 as Field
-    v453 = mul v452, Field 16777216
-    v454 = add v447, v453
-    v455 = cast v387 as Field
-    v457 = mul v455, Field 4294967296
-    v458 = add v451, v457
-    v459 = cast v419 as Field
-    v460 = mul v459, Field 4294967296
-    v461 = add v454, v460
-    v462 = cast v385 as Field
-    v464 = mul v462, Field 1099511627776
-    v465 = add v458, v464
-    v466 = cast v417 as Field
-    v467 = mul v466, Field 1099511627776
-    v468 = add v461, v467
-    v469 = cast v383 as Field
-    v471 = mul v469, Field 281474976710656
-    v472 = add v465, v471
-    v473 = cast v415 as Field
-    v474 = mul v473, Field 281474976710656
-    v475 = add v468, v474
-    v476 = cast v381 as Field
-    v478 = mul v476, Field 72057594037927936
-    v479 = add v472, v478
-    v480 = cast v413 as Field
-    v481 = mul v480, Field 72057594037927936
-    v482 = add v475, v481
-    v483 = cast v379 as Field
-    v485 = mul v483, Field 18446744073709551616
-    v486 = add v479, v485
-    v487 = cast v411 as Field
-    v488 = mul v487, Field 18446744073709551616
-    v489 = add v482, v488
-    v490 = cast v377 as Field
-    v492 = mul v490, Field 4722366482869645213696
-    v493 = add v486, v492
-    v494 = cast v409 as Field
-    v495 = mul v494, Field 4722366482869645213696
-    v496 = add v489, v495
-    v497 = cast v375 as Field
-    v499 = mul v497, Field 1208925819614629174706176
-    v500 = add v493, v499
-    v501 = cast v407 as Field
-    v502 = mul v501, Field 1208925819614629174706176
-    v503 = add v496, v502
-    v504 = cast v373 as Field
-    v506 = mul v504, Field 309485009821345068724781056
-    v507 = add v500, v506
-    v508 = cast v405 as Field
-    v509 = mul v508, Field 309485009821345068724781056
-    v510 = add v503, v509
-    v511 = cast v371 as Field
-    v513 = mul v511, Field 79228162514264337593543950336
-    v514 = add v507, v513
-    v515 = cast v403 as Field
-    v516 = mul v515, Field 79228162514264337593543950336
-    v517 = add v510, v516
-    v518 = cast v369 as Field
-    v520 = mul v518, Field 20282409603651670423947251286016
-    v521 = add v514, v520
-    v522 = cast v401 as Field
-    v523 = mul v522, Field 20282409603651670423947251286016
-    v524 = add v517, v523
-    v525 = cast v367 as Field
-    v527 = mul v525, Field 5192296858534827628530496329220096
-    v528 = add v521, v527
-    v529 = cast v399 as Field
-    v530 = mul v529, Field 5192296858534827628530496329220096
-    v531 = add v524, v530
-    v532 = cast v365 as Field
-    v534 = mul v532, Field 1329227995784915872903807060280344576
-    v535 = add v528, v534
-    v536 = cast v397 as Field
-    v537 = mul v536, Field 1329227995784915872903807060280344576
-    v538 = add v531, v537
-    v540 = mul v535, Field 340282366920938463463374607431768211456
-    v541 = add v538, v540
-    v542 = allocate -> &mut Field
-    store Field 0 at v542
-    v544 = eq v4, Field 0
-    jmpif v544 then: b197, else: b193
-  b193():
-    v546 = call f1(v4, Field 0) -> u1
-    jmpif v546 then: b195, else: b194
-  b194():
-    v548, v549 = call f3(v4) -> (Field, Field)
-    range_check v548 to 128 bits
-    range_check v549 to 128 bits
-    v550 = mul Field 340282366920938463463374607431768211456, v549
-    v551 = add v548, v550
-    v552 = eq v4, v551
-    constrain v4 == v551
-    v555 = call f2(Field 53438638232309528389504892708671455233, v548) -> u1
-    v556 = sub Field 53438638232309528389504892708671455233, v548
-    v558 = sub v556, Field 1
-    v559 = cast v555 as Field
-    v560 = mul v559, Field 340282366920938463463374607431768211456
-    v561 = add v558, v560
-    v563 = sub Field 64323764613183177041862057485226039389, v549
-    v564 = cast v555 as Field
-    v565 = sub v563, v564
-    range_check v561 to 128 bits
-    range_check v565 to 128 bits
-    v567, v568 = call f3(Field 0) -> (Field, Field)
-    range_check v567 to 128 bits
-    range_check v568 to 128 bits
-    v569 = mul Field 340282366920938463463374607431768211456, v568
-    v570 = add v567, v569
-    v571 = eq Field 0, v570
-    constrain Field 0 == v570
-    v573 = call f2(Field 53438638232309528389504892708671455233, v567) -> u1
-    v574 = sub Field 53438638232309528389504892708671455233, v567
-    v575 = sub v574, Field 1
-    v576 = cast v573 as Field
-    v577 = mul v576, Field 340282366920938463463374607431768211456
-    v578 = add v575, v577
-    v579 = sub Field 64323764613183177041862057485226039389, v568
-    v580 = cast v573 as Field
-    v581 = sub v579, v580
-    range_check v578 to 128 bits
-    range_check v581 to 128 bits
-    v583 = call f2(v548, v567) -> u1
-    v584 = sub v548, v567
-    v585 = sub v584, Field 1
-    v586 = cast v583 as Field
-    v587 = mul v586, Field 340282366920938463463374607431768211456
-    v588 = add v585, v587
-    v589 = sub v549, v568
-    v590 = cast v583 as Field
-    v591 = sub v589, v590
-    range_check v588 to 128 bits
-    range_check v591 to 128 bits
-    jmp b196(u1 1)
-  b195():
-    v593, v594 = call f3(Field 0) -> (Field, Field)
-    range_check v593 to 128 bits
-    range_check v594 to 128 bits
-    v595 = mul Field 340282366920938463463374607431768211456, v594
-    v596 = add v593, v595
-    v597 = eq Field 0, v596
-    constrain Field 0 == v596
-    v599 = call f2(Field 53438638232309528389504892708671455233, v593) -> u1
-    v600 = sub Field 53438638232309528389504892708671455233, v593
-    v601 = sub v600, Field 1
-    v602 = cast v599 as Field
-    v603 = mul v602, Field 340282366920938463463374607431768211456
-    v604 = add v601, v603
-    v605 = sub Field 64323764613183177041862057485226039389, v594
-    v606 = cast v599 as Field
-    v607 = sub v605, v606
-    range_check v604 to 128 bits
-    range_check v607 to 128 bits
-    v609, v610 = call f3(v4) -> (Field, Field)
-    range_check v609 to 128 bits
-    range_check v610 to 128 bits
-    v611 = mul Field 340282366920938463463374607431768211456, v610
-    v612 = add v609, v611
-    v613 = eq v4, v612
-    constrain v4 == v612
-    v615 = call f2(Field 53438638232309528389504892708671455233, v609) -> u1
-    v616 = sub Field 53438638232309528389504892708671455233, v609
-    v617 = sub v616, Field 1
-    v618 = cast v615 as Field
-    v619 = mul v618, Field 340282366920938463463374607431768211456
-    v620 = add v617, v619
-    v621 = sub Field 64323764613183177041862057485226039389, v610
-    v622 = cast v615 as Field
-    v623 = sub v621, v622
-    range_check v620 to 128 bits
-    range_check v623 to 128 bits
-    v625 = call f2(v593, v609) -> u1
-    v626 = sub v593, v609
-    v627 = sub v626, Field 1
-    v628 = cast v625 as Field
-    v629 = mul v628, Field 340282366920938463463374607431768211456
-    v630 = add v627, v629
-    v631 = sub v594, v610
-    v632 = cast v625 as Field
-    v633 = sub v631, v632
-    range_check v630 to 128 bits
-    range_check v633 to 128 bits
-    jmp b196(u1 0)
-  b196(v5: u1):
-    jmp b198(v5)
-  b197():
-    jmp b198(u1 0)
-  b198(v6: u1):
-    jmpif v6 then: b199, else: b200
-  b199():
-    store Field 1 at v542
-    jmp b200()
-  b200():
-    v634 = load v542 -> Field
-    v635 = sub v634, v541
-    return v635
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Flattening:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = allocate -> &mut Field
-    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v40 = allocate -> &mut u1
-    store u1 0 at v40
-    enable_side_effects u1 1
-    v44 = array_get v9, index u32 0 -> u8
-    v45 = eq v44, u8 48
-    v46 = not v45
-    v47 = unchecked_mul u1 1, v46
-    enable_side_effects v47
-    v48 = array_get v9, index u32 0 -> u8
-    v49 = lt v48, u8 48
-    v50 = mul v49, v47
-    constrain v50 == v47
-    v51 = load v40 -> u1
-    v52 = not v47
-    v53 = mul v52, v51
-    v54 = unchecked_add v47, v53
-    store v54 at v40
-    v55 = unchecked_mul u1 1, v45
-    enable_side_effects u1 1
-    v56 = load v40 -> u1
-    v57 = not v56
-    enable_side_effects v57
-    v59 = array_get v9, index u32 1 -> u8
-    v60 = eq v59, u8 100
-    v61 = not v60
-    v62 = unchecked_mul v57, v61
-    enable_side_effects v62
-    v63 = array_get v9, index u32 1 -> u8
-    v64 = lt v63, u8 100
-    v65 = mul v64, v62
-    constrain v65 == v62
-    v66 = load v40 -> u1
-    v67 = not v62
-    v68 = mul v67, v66
-    v69 = unchecked_add v62, v68
-    store v69 at v40
-    v70 = unchecked_mul v57, v60
-    enable_side_effects u1 1
-    v71 = load v40 -> u1
-    v72 = not v71
-    enable_side_effects v72
-    v74 = array_get v9, index u32 2 -> u8
-    v75 = eq v74, u8 78
-    v76 = not v75
-    v77 = unchecked_mul v72, v76
-    enable_side_effects v77
-    v78 = array_get v9, index u32 2 -> u8
-    v79 = lt v78, u8 78
-    v80 = mul v79, v77
-    constrain v80 == v77
-    v81 = load v40 -> u1
-    v82 = not v77
-    v83 = mul v82, v81
-    v84 = unchecked_add v77, v83
-    store v84 at v40
-    v85 = unchecked_mul v72, v75
-    enable_side_effects u1 1
-    v86 = load v40 -> u1
-    v87 = not v86
-    enable_side_effects v87
-    v89 = array_get v9, index u32 3 -> u8
-    v90 = eq v89, u8 114
-    v91 = not v90
-    v92 = unchecked_mul v87, v91
-    enable_side_effects v92
-    v93 = array_get v9, index u32 3 -> u8
-    v94 = lt v93, u8 114
-    v95 = mul v94, v92
-    constrain v95 == v92
-    v96 = load v40 -> u1
-    v97 = not v92
-    v98 = mul v97, v96
-    v99 = unchecked_add v92, v98
-    store v99 at v40
-    v100 = unchecked_mul v87, v90
-    enable_side_effects u1 1
-    v101 = load v40 -> u1
-    v102 = not v101
-    enable_side_effects v102
-    v104 = array_get v9, index u32 4 -> u8
-    v105 = eq v104, u8 225
-    v106 = not v105
-    v107 = unchecked_mul v102, v106
-    enable_side_effects v107
-    v108 = array_get v9, index u32 4 -> u8
-    v109 = lt v108, u8 225
-    v110 = mul v109, v107
-    constrain v110 == v107
-    v111 = load v40 -> u1
-    v112 = not v107
-    v113 = mul v112, v111
-    v114 = unchecked_add v107, v113
-    store v114 at v40
-    v115 = unchecked_mul v102, v105
-    enable_side_effects u1 1
-    v116 = load v40 -> u1
-    v117 = not v116
-    enable_side_effects v117
-    v119 = array_get v9, index u32 5 -> u8
-    v120 = eq v119, u8 49
-    v121 = not v120
-    v122 = unchecked_mul v117, v121
-    enable_side_effects v122
-    v123 = array_get v9, index u32 5 -> u8
-    v124 = lt v123, u8 49
-    v125 = mul v124, v122
-    constrain v125 == v122
-    v126 = load v40 -> u1
-    v127 = not v122
-    v128 = mul v127, v126
-    v129 = unchecked_add v122, v128
-    store v129 at v40
-    v130 = unchecked_mul v117, v120
-    enable_side_effects u1 1
-    v131 = load v40 -> u1
-    v132 = not v131
-    enable_side_effects v132
-    v134 = array_get v9, index u32 6 -> u8
-    v135 = eq v134, u8 160
-    v136 = not v135
-    v137 = unchecked_mul v132, v136
-    enable_side_effects v137
-    v138 = array_get v9, index u32 6 -> u8
-    v139 = lt v138, u8 160
-    v140 = mul v139, v137
-    constrain v140 == v137
-    v141 = load v40 -> u1
-    v142 = not v137
-    v143 = mul v142, v141
-    v144 = unchecked_add v137, v143
-    store v144 at v40
-    v145 = unchecked_mul v132, v135
-    enable_side_effects u1 1
-    v146 = load v40 -> u1
-    v147 = not v146
-    enable_side_effects v147
-    v149 = array_get v9, index u32 7 -> u8
-    v150 = eq v149, u8 41
-    v151 = not v150
-    v152 = unchecked_mul v147, v151
-    enable_side_effects v152
-    v153 = array_get v9, index u32 7 -> u8
-    v154 = lt v153, u8 41
-    v155 = mul v154, v152
-    constrain v155 == v152
-    v156 = load v40 -> u1
-    v157 = not v152
-    v158 = mul v157, v156
-    v159 = unchecked_add v152, v158
-    store v159 at v40
-    v160 = unchecked_mul v147, v150
-    enable_side_effects u1 1
-    v161 = load v40 -> u1
-    v162 = not v161
-    enable_side_effects v162
-    v164 = array_get v9, index u32 8 -> u8
-    v165 = eq v164, u8 184
-    v166 = not v165
-    v167 = unchecked_mul v162, v166
-    enable_side_effects v167
-    v168 = array_get v9, index u32 8 -> u8
-    v169 = lt v168, u8 184
-    v170 = mul v169, v167
-    constrain v170 == v167
-    v171 = load v40 -> u1
-    v172 = not v167
-    v173 = mul v172, v171
-    v174 = unchecked_add v167, v173
-    store v174 at v40
-    v175 = unchecked_mul v162, v165
-    enable_side_effects u1 1
-    v176 = load v40 -> u1
-    v177 = not v176
-    enable_side_effects v177
-    v179 = array_get v9, index u32 9 -> u8
-    v180 = eq v179, u8 80
-    v181 = not v180
-    v182 = unchecked_mul v177, v181
-    enable_side_effects v182
-    v183 = array_get v9, index u32 9 -> u8
-    v184 = lt v183, u8 80
-    v185 = mul v184, v182
-    constrain v185 == v182
-    v186 = load v40 -> u1
-    v187 = not v182
-    v188 = mul v187, v186
-    v189 = unchecked_add v182, v188
-    store v189 at v40
-    v190 = unchecked_mul v177, v180
-    enable_side_effects u1 1
-    v191 = load v40 -> u1
-    v192 = not v191
-    enable_side_effects v192
-    v194 = array_get v9, index u32 10 -> u8
-    v195 = eq v194, u8 69
-    v196 = not v195
-    v197 = unchecked_mul v192, v196
-    enable_side_effects v197
-    v198 = array_get v9, index u32 10 -> u8
-    v199 = lt v198, u8 69
-    v200 = mul v199, v197
-    constrain v200 == v197
-    v201 = load v40 -> u1
-    v202 = not v197
-    v203 = mul v202, v201
-    v204 = unchecked_add v197, v203
-    store v204 at v40
-    v205 = unchecked_mul v192, v195
-    enable_side_effects u1 1
-    v206 = load v40 -> u1
-    v207 = not v206
-    enable_side_effects v207
-    v209 = array_get v9, index u32 11 -> u8
-    v210 = eq v209, u8 182
-    v211 = not v210
-    v212 = unchecked_mul v207, v211
-    enable_side_effects v212
-    v213 = array_get v9, index u32 11 -> u8
-    v214 = lt v213, u8 182
-    v215 = mul v214, v212
-    constrain v215 == v212
-    v216 = load v40 -> u1
-    v217 = not v212
-    v218 = mul v217, v216
-    v219 = unchecked_add v212, v218
-    store v219 at v40
-    v220 = unchecked_mul v207, v210
-    enable_side_effects u1 1
-    v221 = load v40 -> u1
-    v222 = not v221
-    enable_side_effects v222
-    v224 = array_get v9, index u32 12 -> u8
-    v225 = eq v224, u8 129
-    v226 = not v225
-    v227 = unchecked_mul v222, v226
-    enable_side_effects v227
-    v228 = array_get v9, index u32 12 -> u8
-    v229 = lt v228, u8 129
-    v230 = mul v229, v227
-    constrain v230 == v227
-    v231 = load v40 -> u1
-    v232 = not v227
-    v233 = mul v232, v231
-    v234 = unchecked_add v227, v233
-    store v234 at v40
-    v235 = unchecked_mul v222, v225
-    enable_side_effects u1 1
-    v236 = load v40 -> u1
-    v237 = not v236
-    enable_side_effects v237
-    v239 = array_get v9, index u32 13 -> u8
-    v240 = eq v239, u8 129
-    v241 = not v240
-    v242 = unchecked_mul v237, v241
-    enable_side_effects v242
-    v243 = array_get v9, index u32 13 -> u8
-    v244 = lt v243, u8 129
-    v245 = mul v244, v242
-    constrain v245 == v242
-    v246 = load v40 -> u1
-    v247 = not v242
-    v248 = mul v247, v246
-    v249 = unchecked_add v242, v248
-    store v249 at v40
-    v250 = unchecked_mul v237, v240
-    enable_side_effects u1 1
-    v251 = load v40 -> u1
-    v252 = not v251
-    enable_side_effects v252
-    v254 = array_get v9, index u32 14 -> u8
-    v255 = eq v254, u8 88
-    v256 = not v255
-    v257 = unchecked_mul v252, v256
-    enable_side_effects v257
-    v258 = array_get v9, index u32 14 -> u8
-    v259 = lt v258, u8 88
-    v260 = mul v259, v257
-    constrain v260 == v257
-    v261 = load v40 -> u1
-    v262 = not v257
-    v263 = mul v262, v261
-    v264 = unchecked_add v257, v263
-    store v264 at v40
-    v265 = unchecked_mul v252, v255
-    enable_side_effects u1 1
-    v266 = load v40 -> u1
-    v267 = not v266
-    enable_side_effects v267
-    v269 = array_get v9, index u32 15 -> u8
-    v270 = eq v269, u8 93
-    v271 = not v270
-    v272 = unchecked_mul v267, v271
-    enable_side_effects v272
-    v273 = array_get v9, index u32 15 -> u8
-    v274 = lt v273, u8 93
-    v275 = mul v274, v272
-    constrain v275 == v272
-    v276 = load v40 -> u1
-    v277 = not v272
-    v278 = mul v277, v276
-    v279 = unchecked_add v272, v278
-    store v279 at v40
-    v280 = unchecked_mul v267, v270
-    enable_side_effects u1 1
-    v281 = load v40 -> u1
-    v282 = not v281
-    enable_side_effects v282
-    v284 = array_get v9, index u32 16 -> u8
-    v285 = eq v284, u8 40
-    v286 = not v285
-    v287 = unchecked_mul v282, v286
-    enable_side_effects v287
-    v288 = array_get v9, index u32 16 -> u8
-    v289 = lt v288, u8 40
-    v290 = mul v289, v287
-    constrain v290 == v287
-    v291 = load v40 -> u1
-    v292 = not v287
-    v293 = mul v292, v291
-    v294 = unchecked_add v287, v293
-    store v294 at v40
-    v295 = unchecked_mul v282, v285
-    enable_side_effects u1 1
-    v296 = load v40 -> u1
-    v297 = not v296
-    enable_side_effects v297
-    v299 = array_get v9, index u32 17 -> u8
-    v300 = eq v299, u8 51
-    v301 = not v300
-    v302 = unchecked_mul v297, v301
-    enable_side_effects v302
-    v303 = array_get v9, index u32 17 -> u8
-    v304 = lt v303, u8 51
-    v305 = mul v304, v302
-    constrain v305 == v302
-    v306 = load v40 -> u1
-    v307 = not v302
-    v308 = mul v307, v306
-    v309 = unchecked_add v302, v308
-    store v309 at v40
-    v310 = unchecked_mul v297, v300
-    enable_side_effects u1 1
-    v311 = load v40 -> u1
-    v312 = not v311
-    enable_side_effects v312
-    v314 = array_get v9, index u32 18 -> u8
-    v315 = eq v314, u8 232
-    v316 = not v315
-    v317 = unchecked_mul v312, v316
-    enable_side_effects v317
-    v318 = array_get v9, index u32 18 -> u8
-    v319 = lt v318, u8 232
-    v320 = mul v319, v317
-    constrain v320 == v317
-    v321 = load v40 -> u1
-    v322 = not v317
-    v323 = mul v322, v321
-    v324 = unchecked_add v317, v323
-    store v324 at v40
-    v325 = unchecked_mul v312, v315
-    enable_side_effects u1 1
-    v326 = load v40 -> u1
-    v327 = not v326
-    enable_side_effects v327
-    v329 = array_get v9, index u32 19 -> u8
-    v330 = eq v329, u8 72
-    v331 = not v330
-    v332 = unchecked_mul v327, v331
-    enable_side_effects v332
-    v333 = array_get v9, index u32 19 -> u8
-    v334 = lt v333, u8 72
-    v335 = mul v334, v332
-    constrain v335 == v332
-    v336 = load v40 -> u1
-    v337 = not v332
-    v338 = mul v337, v336
-    v339 = unchecked_add v332, v338
-    store v339 at v40
-    v340 = unchecked_mul v327, v330
-    enable_side_effects u1 1
-    v341 = load v40 -> u1
-    v342 = not v341
-    enable_side_effects v342
-    v344 = array_get v9, index u32 20 -> u8
-    v345 = eq v344, u8 121
-    v346 = not v345
-    v347 = unchecked_mul v342, v346
-    enable_side_effects v347
-    v348 = array_get v9, index u32 20 -> u8
-    v349 = lt v348, u8 121
-    v350 = mul v349, v347
-    constrain v350 == v347
-    v351 = load v40 -> u1
-    v352 = not v347
-    v353 = mul v352, v351
-    v354 = unchecked_add v347, v353
-    store v354 at v40
-    v355 = unchecked_mul v342, v345
-    enable_side_effects u1 1
-    v356 = load v40 -> u1
-    v357 = not v356
-    enable_side_effects v357
-    v359 = array_get v9, index u32 21 -> u8
-    v360 = eq v359, u8 185
-    v361 = not v360
-    v362 = unchecked_mul v357, v361
-    enable_side_effects v362
-    v363 = array_get v9, index u32 21 -> u8
-    v364 = lt v363, u8 185
-    v365 = mul v364, v362
-    constrain v365 == v362
-    v366 = load v40 -> u1
-    v367 = not v362
-    v368 = mul v367, v366
-    v369 = unchecked_add v362, v368
-    store v369 at v40
-    v370 = unchecked_mul v357, v360
-    enable_side_effects u1 1
-    v371 = load v40 -> u1
-    v372 = not v371
-    enable_side_effects v372
-    v374 = array_get v9, index u32 22 -> u8
-    v375 = eq v374, u8 112
-    v376 = not v375
-    v377 = unchecked_mul v372, v376
-    enable_side_effects v377
-    v378 = array_get v9, index u32 22 -> u8
-    v379 = lt v378, u8 112
-    v380 = mul v379, v377
-    constrain v380 == v377
-    v381 = load v40 -> u1
-    v382 = not v377
-    v383 = mul v382, v381
-    v384 = unchecked_add v377, v383
-    store v384 at v40
-    v385 = unchecked_mul v372, v375
-    enable_side_effects u1 1
-    v386 = load v40 -> u1
-    v387 = not v386
-    enable_side_effects v387
-    v389 = array_get v9, index u32 23 -> u8
-    v390 = eq v389, u8 145
-    v391 = not v390
-    v392 = unchecked_mul v387, v391
-    enable_side_effects v392
-    v393 = array_get v9, index u32 23 -> u8
-    v394 = lt v393, u8 145
-    v395 = mul v394, v392
-    constrain v395 == v392
-    v396 = load v40 -> u1
-    v397 = not v392
-    v398 = mul v397, v396
-    v399 = unchecked_add v392, v398
-    store v399 at v40
-    v400 = unchecked_mul v387, v390
-    enable_side_effects u1 1
-    v401 = load v40 -> u1
-    v402 = not v401
-    enable_side_effects v402
-    v404 = array_get v9, index u32 24 -> u8
-    v405 = eq v404, u8 67
-    v406 = not v405
-    v407 = unchecked_mul v402, v406
-    enable_side_effects v407
-    v408 = array_get v9, index u32 24 -> u8
-    v409 = lt v408, u8 67
-    v410 = mul v409, v407
-    constrain v410 == v407
-    v411 = load v40 -> u1
-    v412 = not v407
-    v413 = mul v412, v411
-    v414 = unchecked_add v407, v413
-    store v414 at v40
-    v415 = unchecked_mul v402, v405
-    enable_side_effects u1 1
-    v416 = load v40 -> u1
-    v417 = not v416
-    enable_side_effects v417
-    v419 = array_get v9, index u32 25 -> u8
-    v420 = eq v419, u8 225
-    v421 = not v420
-    v422 = unchecked_mul v417, v421
-    enable_side_effects v422
-    v423 = array_get v9, index u32 25 -> u8
-    v424 = lt v423, u8 225
-    v425 = mul v424, v422
-    constrain v425 == v422
-    v426 = load v40 -> u1
-    v427 = not v422
-    v428 = mul v427, v426
-    v429 = unchecked_add v422, v428
-    store v429 at v40
-    v430 = unchecked_mul v417, v420
-    enable_side_effects u1 1
-    v431 = load v40 -> u1
-    v432 = not v431
-    enable_side_effects v432
-    v434 = array_get v9, index u32 26 -> u8
-    v435 = eq v434, u8 245
-    v436 = not v435
-    v437 = unchecked_mul v432, v436
-    enable_side_effects v437
-    v438 = array_get v9, index u32 26 -> u8
-    v439 = lt v438, u8 245
-    v440 = mul v439, v437
-    constrain v440 == v437
-    v441 = load v40 -> u1
-    v442 = not v437
-    v443 = mul v442, v441
-    v444 = unchecked_add v437, v443
-    store v444 at v40
-    v445 = unchecked_mul v432, v435
-    enable_side_effects u1 1
-    v446 = load v40 -> u1
-    v447 = not v446
-    enable_side_effects v447
-    v449 = array_get v9, index u32 27 -> u8
-    v450 = eq v449, u8 147
-    v451 = not v450
-    v452 = unchecked_mul v447, v451
-    enable_side_effects v452
-    v453 = array_get v9, index u32 27 -> u8
-    v454 = lt v453, u8 147
-    v455 = mul v454, v452
-    constrain v455 == v452
-    v456 = load v40 -> u1
-    v457 = not v452
-    v458 = mul v457, v456
-    v459 = unchecked_add v452, v458
-    store v459 at v40
-    v460 = unchecked_mul v447, v450
-    enable_side_effects u1 1
-    v461 = load v40 -> u1
-    v462 = not v461
-    enable_side_effects v462
-    v464 = array_get v9, index u32 28 -> u8
-    v465 = eq v464, u8 240
-    v466 = not v465
-    v467 = unchecked_mul v462, v466
-    enable_side_effects v467
-    v468 = array_get v9, index u32 28 -> u8
-    v469 = lt v468, u8 240
-    v470 = mul v469, v467
-    constrain v470 == v467
-    v471 = load v40 -> u1
-    v472 = not v467
-    v473 = mul v472, v471
-    v474 = unchecked_add v467, v473
-    store v474 at v40
-    v475 = unchecked_mul v462, v465
-    enable_side_effects u1 1
-    v476 = load v40 -> u1
-    v477 = not v476
-    enable_side_effects v477
-    v479 = array_get v9, index u32 29 -> u8
-    v480 = eq v479, u8 0
-    v481 = not v480
-    v482 = unchecked_mul v477, v481
-    enable_side_effects v482
-    v483 = array_get v9, index u32 29 -> u8
-    constrain u1 0 == v482
-    v484 = load v40 -> u1
-    v485 = not v482
-    v486 = mul v485, v484
-    v487 = unchecked_add v482, v486
-    store v487 at v40
-    v488 = unchecked_mul v477, v480
-    enable_side_effects u1 1
-    v489 = load v40 -> u1
-    v490 = not v489
-    enable_side_effects v490
-    v492 = array_get v9, index u32 30 -> u8
-    v493 = eq v492, u8 0
-    v494 = not v493
-    v495 = unchecked_mul v490, v494
-    enable_side_effects v495
-    v496 = array_get v9, index u32 30 -> u8
-    constrain u1 0 == v495
-    v497 = load v40 -> u1
-    v498 = not v495
-    v499 = mul v498, v497
-    v500 = unchecked_add v495, v499
-    store v500 at v40
-    v501 = unchecked_mul v490, v493
-    enable_side_effects u1 1
-    v502 = load v40 -> u1
-    v503 = not v502
-    enable_side_effects v503
-    v505 = array_get v9, index u32 31 -> u8
-    v506 = eq v505, u8 1
-    v507 = not v506
-    v508 = unchecked_mul v503, v507
-    enable_side_effects v508
-    v509 = array_get v9, index u32 31 -> u8
-    v510 = eq v509, u8 0
-    v511 = cast v508 as u8
-    v512 = unchecked_mul v509, v511
-    constrain v512 == u8 0
-    v513 = load v40 -> u1
-    v514 = not v508
-    v515 = mul v514, v513
-    v516 = unchecked_add v508, v515
-    store v516 at v40
-    v517 = unchecked_mul v503, v506
-    enable_side_effects u1 1
-    v518 = load v40 -> u1
-    constrain v518 == u1 1
-    v519 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v520 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v521 = allocate -> &mut u1
-    store u1 0 at v521
-    enable_side_effects u1 1
-    v522 = load v521 -> u1
-    store u1 1 at v521
-    enable_side_effects u1 1
-    v523 = load v521 -> u1
-    v524 = not v523
-    enable_side_effects v524
-    v525 = load v521 -> u1
-    v526 = mul v523, v525
-    v527 = unchecked_add v524, v526
-    store v527 at v521
-    enable_side_effects u1 1
-    v528 = load v521 -> u1
-    v529 = not v528
-    enable_side_effects v529
-    v530 = load v521 -> u1
-    v531 = mul v528, v530
-    v532 = unchecked_add v529, v531
-    store v532 at v521
-    enable_side_effects u1 1
-    v533 = load v521 -> u1
-    v534 = not v533
-    enable_side_effects v534
-    v535 = load v521 -> u1
-    v536 = mul v533, v535
-    v537 = unchecked_add v534, v536
-    store v537 at v521
-    enable_side_effects u1 1
-    v538 = load v521 -> u1
-    v539 = not v538
-    enable_side_effects v539
-    v540 = load v521 -> u1
-    v541 = mul v538, v540
-    v542 = unchecked_add v539, v541
-    store v542 at v521
-    enable_side_effects u1 1
-    v543 = load v521 -> u1
-    v544 = not v543
-    enable_side_effects v544
-    v545 = load v521 -> u1
-    v546 = mul v543, v545
-    v547 = unchecked_add v544, v546
-    store v547 at v521
-    enable_side_effects u1 1
-    v548 = load v521 -> u1
-    v549 = not v548
-    enable_side_effects v549
-    v550 = load v521 -> u1
-    v551 = mul v548, v550
-    v552 = unchecked_add v549, v551
-    store v552 at v521
-    enable_side_effects u1 1
-    v553 = load v521 -> u1
-    v554 = not v553
-    enable_side_effects v554
-    v555 = load v521 -> u1
-    v556 = mul v553, v555
-    v557 = unchecked_add v554, v556
-    store v557 at v521
-    enable_side_effects u1 1
-    v558 = load v521 -> u1
-    v559 = not v558
-    enable_side_effects v559
-    v560 = load v521 -> u1
-    v561 = mul v558, v560
-    v562 = unchecked_add v559, v561
-    store v562 at v521
-    enable_side_effects u1 1
-    v563 = load v521 -> u1
-    v564 = not v563
-    enable_side_effects v564
-    v565 = load v521 -> u1
-    v566 = mul v563, v565
-    v567 = unchecked_add v564, v566
-    store v567 at v521
-    enable_side_effects u1 1
-    v568 = load v521 -> u1
-    v569 = not v568
-    enable_side_effects v569
-    v570 = load v521 -> u1
-    v571 = mul v568, v570
-    v572 = unchecked_add v569, v571
-    store v572 at v521
-    enable_side_effects u1 1
-    v573 = load v521 -> u1
-    v574 = not v573
-    enable_side_effects v574
-    v575 = load v521 -> u1
-    v576 = mul v573, v575
-    v577 = unchecked_add v574, v576
-    store v577 at v521
-    enable_side_effects u1 1
-    v578 = load v521 -> u1
-    v579 = not v578
-    enable_side_effects v579
-    v580 = load v521 -> u1
-    v581 = mul v578, v580
-    v582 = unchecked_add v579, v581
-    store v582 at v521
-    enable_side_effects u1 1
-    v583 = load v521 -> u1
-    v584 = not v583
-    enable_side_effects v584
-    v585 = load v521 -> u1
-    v586 = mul v583, v585
-    v587 = unchecked_add v584, v586
-    store v587 at v521
-    enable_side_effects u1 1
-    v588 = load v521 -> u1
-    v589 = not v588
-    enable_side_effects v589
-    v590 = load v521 -> u1
-    v591 = mul v588, v590
-    v592 = unchecked_add v589, v591
-    store v592 at v521
-    enable_side_effects u1 1
-    v593 = load v521 -> u1
-    v594 = not v593
-    enable_side_effects v594
-    v595 = load v521 -> u1
-    v596 = mul v593, v595
-    v597 = unchecked_add v594, v596
-    store v597 at v521
-    enable_side_effects u1 1
-    v598 = load v521 -> u1
-    v599 = not v598
-    enable_side_effects v599
-    v600 = load v521 -> u1
-    v601 = mul v598, v600
-    v602 = unchecked_add v599, v601
-    store v602 at v521
-    enable_side_effects u1 1
-    v603 = load v521 -> u1
-    v604 = not v603
-    enable_side_effects v604
-    v605 = load v521 -> u1
-    v606 = mul v603, v605
-    v607 = unchecked_add v604, v606
-    store v607 at v521
-    enable_side_effects u1 1
-    v608 = load v521 -> u1
-    v609 = not v608
-    enable_side_effects v609
-    v610 = load v521 -> u1
-    v611 = mul v608, v610
-    v612 = unchecked_add v609, v611
-    store v612 at v521
-    enable_side_effects u1 1
-    v613 = load v521 -> u1
-    v614 = not v613
-    enable_side_effects v614
-    v615 = load v521 -> u1
-    v616 = mul v613, v615
-    v617 = unchecked_add v614, v616
-    store v617 at v521
-    enable_side_effects u1 1
-    v618 = load v521 -> u1
-    v619 = not v618
-    enable_side_effects v619
-    v620 = load v521 -> u1
-    v621 = mul v618, v620
-    v622 = unchecked_add v619, v621
-    store v622 at v521
-    enable_side_effects u1 1
-    v623 = load v521 -> u1
-    v624 = not v623
-    enable_side_effects v624
-    v625 = load v521 -> u1
-    v626 = mul v623, v625
-    v627 = unchecked_add v624, v626
-    store v627 at v521
-    enable_side_effects u1 1
-    v628 = load v521 -> u1
-    v629 = not v628
-    enable_side_effects v629
-    v630 = load v521 -> u1
-    v631 = mul v628, v630
-    v632 = unchecked_add v629, v631
-    store v632 at v521
-    enable_side_effects u1 1
-    v633 = load v521 -> u1
-    v634 = not v633
-    enable_side_effects v634
-    v635 = load v521 -> u1
-    v636 = mul v633, v635
-    v637 = unchecked_add v634, v636
-    store v637 at v521
-    enable_side_effects u1 1
-    v638 = load v521 -> u1
-    v639 = not v638
-    enable_side_effects v639
-    v640 = load v521 -> u1
-    v641 = mul v638, v640
-    v642 = unchecked_add v639, v641
-    store v642 at v521
-    enable_side_effects u1 1
-    v643 = load v521 -> u1
-    v644 = not v643
-    enable_side_effects v644
-    v645 = load v521 -> u1
-    v646 = mul v643, v645
-    v647 = unchecked_add v644, v646
-    store v647 at v521
-    enable_side_effects u1 1
-    v648 = load v521 -> u1
-    v649 = not v648
-    enable_side_effects v649
-    v650 = load v521 -> u1
-    v651 = mul v648, v650
-    v652 = unchecked_add v649, v651
-    store v652 at v521
-    enable_side_effects u1 1
-    v653 = load v521 -> u1
-    v654 = not v653
-    enable_side_effects v654
-    v655 = load v521 -> u1
-    v656 = mul v653, v655
-    v657 = unchecked_add v654, v656
-    store v657 at v521
-    enable_side_effects u1 1
-    v658 = load v521 -> u1
-    v659 = not v658
-    enable_side_effects v659
-    v660 = load v521 -> u1
-    v661 = mul v658, v660
-    v662 = unchecked_add v659, v661
-    store v662 at v521
-    enable_side_effects u1 1
-    v663 = load v521 -> u1
-    v664 = not v663
-    enable_side_effects u1 1
-    v665 = load v521 -> u1
-    v666 = not v665
-    enable_side_effects u1 1
-    v667 = load v521 -> u1
-    v668 = not v667
-    enable_side_effects v668
-    v669 = load v521 -> u1
-    v670 = mul v667, v669
-    v671 = unchecked_add v668, v670
-    store v671 at v521
-    enable_side_effects u1 1
-    v672 = load v521 -> u1
-    constrain v672 == u1 1
-    v673 = allocate -> &mut [u8; 32]
-    v674 = array_get v9, index u32 0 -> u8
-    v675 = make_array [v674, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v676 = array_get v9, index u32 1 -> u8
-    v677 = make_array [v674, v676, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v678 = array_get v9, index u32 2 -> u8
-    v679 = make_array [v674, v676, v678, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v680 = array_get v9, index u32 3 -> u8
-    v681 = make_array [v674, v676, v678, v680, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v682 = array_get v9, index u32 4 -> u8
-    v683 = make_array [v674, v676, v678, v680, v682, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v684 = array_get v9, index u32 5 -> u8
-    v685 = make_array [v674, v676, v678, v680, v682, v684, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v686 = array_get v9, index u32 6 -> u8
-    v687 = make_array [v674, v676, v678, v680, v682, v684, v686, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v688 = array_get v9, index u32 7 -> u8
-    v689 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v690 = array_get v9, index u32 8 -> u8
-    v691 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v692 = array_get v9, index u32 9 -> u8
-    v693 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v694 = array_get v9, index u32 10 -> u8
-    v695 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v696 = array_get v9, index u32 11 -> u8
-    v697 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v698 = array_get v9, index u32 12 -> u8
-    v699 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v700 = array_get v9, index u32 13 -> u8
-    v701 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v702 = array_get v9, index u32 14 -> u8
-    v703 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v704 = array_get v9, index u32 15 -> u8
-    v705 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v706 = array_get v9, index u32 16 -> u8
-    v707 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v708 = array_get v9, index u32 17 -> u8
-    v709 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v710 = array_get v9, index u32 18 -> u8
-    v711 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v712 = array_get v9, index u32 19 -> u8
-    v713 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v714 = array_get v9, index u32 20 -> u8
-    v715 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v716 = array_get v9, index u32 21 -> u8
-    v717 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v718 = array_get v9, index u32 22 -> u8
-    v719 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v720 = array_get v9, index u32 23 -> u8
-    v721 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v722 = array_get v9, index u32 24 -> u8
-    v723 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v724 = array_get v9, index u32 25 -> u8
-    v725 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v726 = array_get v9, index u32 26 -> u8
-    v727 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v728 = array_get v9, index u32 27 -> u8
-    v729 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v730 = array_get v9, index u32 28 -> u8
-    v731 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, u8 0, u8 0, u8 0] : [u8; 32]
-    v732 = array_get v9, index u32 29 -> u8
-    v733 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, v732, u8 0, u8 0] : [u8; 32]
-    v734 = array_get v9, index u32 30 -> u8
-    v735 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, v732, v734, u8 0] : [u8; 32]
-    v736 = array_get v9, index u32 31 -> u8
-    v737 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, v732, v734, v736] : [u8; 32]
-    v738 = allocate -> &mut Field
-    v739 = allocate -> &mut Field
-    v740 = allocate -> &mut Field
-    v741 = cast v704 as Field
-    v742 = cast v736 as Field
-    v743 = cast v702 as Field
-    v745 = mul v743, Field 256
-    v746 = add v741, v745
-    v747 = cast v734 as Field
-    v748 = mul v747, Field 256
-    v749 = add v742, v748
-    v750 = cast v700 as Field
-    v752 = mul v750, Field 65536
-    v753 = add v746, v752
-    v754 = cast v732 as Field
-    v755 = mul v754, Field 65536
-    v756 = add v749, v755
-    v757 = cast v698 as Field
-    v759 = mul v757, Field 16777216
-    v760 = add v753, v759
-    v761 = cast v730 as Field
-    v762 = mul v761, Field 16777216
-    v763 = add v756, v762
-    v764 = cast v696 as Field
-    v766 = mul v764, Field 4294967296
-    v767 = add v760, v766
-    v768 = cast v728 as Field
-    v769 = mul v768, Field 4294967296
-    v770 = add v763, v769
-    v771 = cast v694 as Field
-    v773 = mul v771, Field 1099511627776
-    v774 = add v767, v773
-    v775 = cast v726 as Field
-    v776 = mul v775, Field 1099511627776
-    v777 = add v770, v776
-    v778 = cast v692 as Field
-    v780 = mul v778, Field 281474976710656
-    v781 = add v774, v780
-    v782 = cast v724 as Field
-    v783 = mul v782, Field 281474976710656
-    v784 = add v777, v783
-    v785 = cast v690 as Field
-    v787 = mul v785, Field 72057594037927936
-    v788 = add v781, v787
-    v789 = cast v722 as Field
-    v790 = mul v789, Field 72057594037927936
-    v791 = add v784, v790
-    v792 = cast v688 as Field
-    v794 = mul v792, Field 18446744073709551616
-    v795 = add v788, v794
-    v796 = cast v720 as Field
-    v797 = mul v796, Field 18446744073709551616
-    v798 = add v791, v797
-    v799 = cast v686 as Field
-    v801 = mul v799, Field 4722366482869645213696
-    v802 = add v795, v801
-    v803 = cast v718 as Field
-    v804 = mul v803, Field 4722366482869645213696
-    v805 = add v798, v804
-    v806 = cast v684 as Field
-    v808 = mul v806, Field 1208925819614629174706176
-    v809 = add v802, v808
-    v810 = cast v716 as Field
-    v811 = mul v810, Field 1208925819614629174706176
-    v812 = add v805, v811
-    v813 = cast v682 as Field
-    v815 = mul v813, Field 309485009821345068724781056
-    v816 = add v809, v815
-    v817 = cast v714 as Field
-    v818 = mul v817, Field 309485009821345068724781056
-    v819 = add v812, v818
-    v820 = cast v680 as Field
-    v822 = mul v820, Field 79228162514264337593543950336
-    v823 = add v816, v822
-    v824 = cast v712 as Field
-    v825 = mul v824, Field 79228162514264337593543950336
-    v826 = add v819, v825
-    v827 = cast v678 as Field
-    v829 = mul v827, Field 20282409603651670423947251286016
-    v830 = add v823, v829
-    v831 = cast v710 as Field
-    v832 = mul v831, Field 20282409603651670423947251286016
-    v833 = add v826, v832
-    v834 = cast v676 as Field
-    v836 = mul v834, Field 5192296858534827628530496329220096
-    v837 = add v830, v836
-    v838 = cast v708 as Field
-    v839 = mul v838, Field 5192296858534827628530496329220096
-    v840 = add v833, v839
-    v841 = cast v674 as Field
-    v843 = mul v841, Field 1329227995784915872903807060280344576
-    v844 = add v837, v843
-    v845 = cast v706 as Field
-    v846 = mul v845, Field 1329227995784915872903807060280344576
-    v847 = add v840, v846
-    v849 = mul v844, Field 340282366920938463463374607431768211456
-    v850 = add v847, v849
-    v851 = allocate -> &mut Field
-    store Field 0 at v851
-    v853 = eq v4, Field 0
-    enable_side_effects v853
-    v854 = not v853
-    enable_side_effects v854
-    v856 = call f1(v4, Field 0) -> u1
-    v857 = unchecked_mul v854, v856
-    enable_side_effects v857
-    v859, v860 = call f3(Field 0) -> (Field, Field)
-    v861 = cast v857 as Field
-    v862 = mul v859, v861
-    range_check v862 to 128 bits
-    v863 = cast v857 as Field
-    v864 = mul v860, v863
-    range_check v864 to 128 bits
-    v865 = mul Field 340282366920938463463374607431768211456, v860
-    v866 = add v859, v865
-    v867 = eq Field 0, v866
-    v868 = cast v857 as Field
-    v869 = mul v866, v868
-    constrain Field 0 == v869
-    v872 = call f2(Field 53438638232309528389504892708671455233, v859) -> u1
-    v873 = sub Field 53438638232309528389504892708671455233, v859
-    v875 = sub v873, Field 1
-    v876 = cast v872 as Field
-    v877 = mul v876, Field 340282366920938463463374607431768211456
-    v878 = add v875, v877
-    v880 = sub Field 64323764613183177041862057485226039389, v860
-    v881 = cast v872 as Field
-    v882 = sub v880, v881
-    v883 = cast v857 as Field
-    v884 = mul v878, v883
-    range_check v884 to 128 bits
-    v885 = cast v857 as Field
-    v886 = mul v882, v885
-    range_check v886 to 128 bits
-    v888, v889 = call f3(v4) -> (Field, Field)
-    v890 = cast v857 as Field
-    v891 = mul v888, v890
-    range_check v891 to 128 bits
-    v892 = cast v857 as Field
-    v893 = mul v889, v892
-    range_check v893 to 128 bits
-    v894 = mul Field 340282366920938463463374607431768211456, v889
-    v895 = add v888, v894
-    v896 = eq v4, v895
-    v897 = cast v857 as Field
-    v898 = mul v4, v897
-    v899 = mul v895, v897
-    constrain v898 == v899
-    v901 = call f2(Field 53438638232309528389504892708671455233, v888) -> u1
-    v902 = sub Field 53438638232309528389504892708671455233, v888
-    v903 = sub v902, Field 1
-    v904 = cast v901 as Field
-    v905 = mul v904, Field 340282366920938463463374607431768211456
-    v906 = add v903, v905
-    v907 = sub Field 64323764613183177041862057485226039389, v889
-    v908 = cast v901 as Field
-    v909 = sub v907, v908
-    v910 = cast v857 as Field
-    v911 = mul v906, v910
-    range_check v911 to 128 bits
-    v912 = cast v857 as Field
-    v913 = mul v909, v912
-    range_check v913 to 128 bits
-    v915 = call f2(v859, v888) -> u1
-    v916 = sub v859, v888
-    v917 = sub v916, Field 1
-    v918 = cast v915 as Field
-    v919 = mul v918, Field 340282366920938463463374607431768211456
-    v920 = add v917, v919
-    v921 = sub v860, v889
-    v922 = cast v915 as Field
-    v923 = sub v921, v922
-    v924 = cast v857 as Field
-    v925 = mul v920, v924
-    range_check v925 to 128 bits
-    v926 = cast v857 as Field
-    v927 = mul v923, v926
-    range_check v927 to 128 bits
-    v928 = not v856
-    v929 = unchecked_mul v854, v928
-    enable_side_effects v929
-    v931, v932 = call f3(v4) -> (Field, Field)
-    v933 = cast v929 as Field
-    v934 = mul v931, v933
-    range_check v934 to 128 bits
-    v935 = cast v929 as Field
-    v936 = mul v932, v935
-    range_check v936 to 128 bits
-    v937 = mul Field 340282366920938463463374607431768211456, v932
-    v938 = add v931, v937
-    v939 = eq v4, v938
-    v940 = cast v929 as Field
-    v941 = mul v4, v940
-    v942 = mul v938, v940
-    constrain v941 == v942
-    v944 = call f2(Field 53438638232309528389504892708671455233, v931) -> u1
-    v945 = sub Field 53438638232309528389504892708671455233, v931
-    v946 = sub v945, Field 1
-    v947 = cast v944 as Field
-    v948 = mul v947, Field 340282366920938463463374607431768211456
-    v949 = add v946, v948
-    v950 = sub Field 64323764613183177041862057485226039389, v932
-    v951 = cast v944 as Field
-    v952 = sub v950, v951
-    v953 = cast v929 as Field
-    v954 = mul v949, v953
-    range_check v954 to 128 bits
-    v955 = cast v929 as Field
-    v956 = mul v952, v955
-    range_check v956 to 128 bits
-    v958, v959 = call f3(Field 0) -> (Field, Field)
-    v960 = cast v929 as Field
-    v961 = mul v958, v960
-    range_check v961 to 128 bits
-    v962 = cast v929 as Field
-    v963 = mul v959, v962
-    range_check v963 to 128 bits
-    v964 = mul Field 340282366920938463463374607431768211456, v959
-    v965 = add v958, v964
-    v966 = eq Field 0, v965
-    v967 = cast v929 as Field
-    v968 = mul v965, v967
-    constrain Field 0 == v968
-    v970 = call f2(Field 53438638232309528389504892708671455233, v958) -> u1
-    v971 = sub Field 53438638232309528389504892708671455233, v958
-    v972 = sub v971, Field 1
-    v973 = cast v970 as Field
-    v974 = mul v973, Field 340282366920938463463374607431768211456
-    v975 = add v972, v974
-    v976 = sub Field 64323764613183177041862057485226039389, v959
-    v977 = cast v970 as Field
-    v978 = sub v976, v977
-    v979 = cast v929 as Field
-    v980 = mul v975, v979
-    range_check v980 to 128 bits
-    v981 = cast v929 as Field
-    v982 = mul v978, v981
-    range_check v982 to 128 bits
-    v984 = call f2(v931, v958) -> u1
-    v985 = sub v931, v958
-    v986 = sub v985, Field 1
-    v987 = cast v984 as Field
-    v988 = mul v987, Field 340282366920938463463374607431768211456
-    v989 = add v986, v988
-    v990 = sub v932, v959
-    v991 = cast v984 as Field
-    v992 = sub v990, v991
-    v993 = cast v929 as Field
-    v994 = mul v989, v993
-    range_check v994 to 128 bits
-    v995 = cast v929 as Field
-    v996 = mul v992, v995
-    range_check v996 to 128 bits
-    enable_side_effects v929
-    v997 = load v851 -> Field
-    v998 = not v929
-    v999 = cast v929 as Field
-    v1000 = cast v998 as Field
-    v1001 = mul v1000, v997
-    v1002 = add v999, v1001
-    store v1002 at v851
-    enable_side_effects u1 1
-    v1003 = load v851 -> Field
-    v1004 = sub v1003, v850
-    return v1004
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Removing Bit Shifts:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = allocate -> &mut Field
-    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v40 = allocate -> &mut u1
-    store u1 0 at v40
-    enable_side_effects u1 1
-    v44 = array_get v9, index u32 0 -> u8
-    v45 = eq v44, u8 48
-    v46 = not v45
-    v47 = unchecked_mul u1 1, v46
-    enable_side_effects v47
-    v48 = array_get v9, index u32 0 -> u8
-    v49 = lt v48, u8 48
-    v50 = mul v49, v47
-    constrain v50 == v47
-    v51 = load v40 -> u1
-    v52 = not v47
-    v53 = mul v52, v51
-    v54 = unchecked_add v47, v53
-    store v54 at v40
-    v55 = unchecked_mul u1 1, v45
-    enable_side_effects u1 1
-    v56 = load v40 -> u1
-    v57 = not v56
-    enable_side_effects v57
-    v59 = array_get v9, index u32 1 -> u8
-    v60 = eq v59, u8 100
-    v61 = not v60
-    v62 = unchecked_mul v57, v61
-    enable_side_effects v62
-    v63 = array_get v9, index u32 1 -> u8
-    v64 = lt v63, u8 100
-    v65 = mul v64, v62
-    constrain v65 == v62
-    v66 = load v40 -> u1
-    v67 = not v62
-    v68 = mul v67, v66
-    v69 = unchecked_add v62, v68
-    store v69 at v40
-    v70 = unchecked_mul v57, v60
-    enable_side_effects u1 1
-    v71 = load v40 -> u1
-    v72 = not v71
-    enable_side_effects v72
-    v74 = array_get v9, index u32 2 -> u8
-    v75 = eq v74, u8 78
-    v76 = not v75
-    v77 = unchecked_mul v72, v76
-    enable_side_effects v77
-    v78 = array_get v9, index u32 2 -> u8
-    v79 = lt v78, u8 78
-    v80 = mul v79, v77
-    constrain v80 == v77
-    v81 = load v40 -> u1
-    v82 = not v77
-    v83 = mul v82, v81
-    v84 = unchecked_add v77, v83
-    store v84 at v40
-    v85 = unchecked_mul v72, v75
-    enable_side_effects u1 1
-    v86 = load v40 -> u1
-    v87 = not v86
-    enable_side_effects v87
-    v89 = array_get v9, index u32 3 -> u8
-    v90 = eq v89, u8 114
-    v91 = not v90
-    v92 = unchecked_mul v87, v91
-    enable_side_effects v92
-    v93 = array_get v9, index u32 3 -> u8
-    v94 = lt v93, u8 114
-    v95 = mul v94, v92
-    constrain v95 == v92
-    v96 = load v40 -> u1
-    v97 = not v92
-    v98 = mul v97, v96
-    v99 = unchecked_add v92, v98
-    store v99 at v40
-    v100 = unchecked_mul v87, v90
-    enable_side_effects u1 1
-    v101 = load v40 -> u1
-    v102 = not v101
-    enable_side_effects v102
-    v104 = array_get v9, index u32 4 -> u8
-    v105 = eq v104, u8 225
-    v106 = not v105
-    v107 = unchecked_mul v102, v106
-    enable_side_effects v107
-    v108 = array_get v9, index u32 4 -> u8
-    v109 = lt v108, u8 225
-    v110 = mul v109, v107
-    constrain v110 == v107
-    v111 = load v40 -> u1
-    v112 = not v107
-    v113 = mul v112, v111
-    v114 = unchecked_add v107, v113
-    store v114 at v40
-    v115 = unchecked_mul v102, v105
-    enable_side_effects u1 1
-    v116 = load v40 -> u1
-    v117 = not v116
-    enable_side_effects v117
-    v119 = array_get v9, index u32 5 -> u8
-    v120 = eq v119, u8 49
-    v121 = not v120
-    v122 = unchecked_mul v117, v121
-    enable_side_effects v122
-    v123 = array_get v9, index u32 5 -> u8
-    v124 = lt v123, u8 49
-    v125 = mul v124, v122
-    constrain v125 == v122
-    v126 = load v40 -> u1
-    v127 = not v122
-    v128 = mul v127, v126
-    v129 = unchecked_add v122, v128
-    store v129 at v40
-    v130 = unchecked_mul v117, v120
-    enable_side_effects u1 1
-    v131 = load v40 -> u1
-    v132 = not v131
-    enable_side_effects v132
-    v134 = array_get v9, index u32 6 -> u8
-    v135 = eq v134, u8 160
-    v136 = not v135
-    v137 = unchecked_mul v132, v136
-    enable_side_effects v137
-    v138 = array_get v9, index u32 6 -> u8
-    v139 = lt v138, u8 160
-    v140 = mul v139, v137
-    constrain v140 == v137
-    v141 = load v40 -> u1
-    v142 = not v137
-    v143 = mul v142, v141
-    v144 = unchecked_add v137, v143
-    store v144 at v40
-    v145 = unchecked_mul v132, v135
-    enable_side_effects u1 1
-    v146 = load v40 -> u1
-    v147 = not v146
-    enable_side_effects v147
-    v149 = array_get v9, index u32 7 -> u8
-    v150 = eq v149, u8 41
-    v151 = not v150
-    v152 = unchecked_mul v147, v151
-    enable_side_effects v152
-    v153 = array_get v9, index u32 7 -> u8
-    v154 = lt v153, u8 41
-    v155 = mul v154, v152
-    constrain v155 == v152
-    v156 = load v40 -> u1
-    v157 = not v152
-    v158 = mul v157, v156
-    v159 = unchecked_add v152, v158
-    store v159 at v40
-    v160 = unchecked_mul v147, v150
-    enable_side_effects u1 1
-    v161 = load v40 -> u1
-    v162 = not v161
-    enable_side_effects v162
-    v164 = array_get v9, index u32 8 -> u8
-    v165 = eq v164, u8 184
-    v166 = not v165
-    v167 = unchecked_mul v162, v166
-    enable_side_effects v167
-    v168 = array_get v9, index u32 8 -> u8
-    v169 = lt v168, u8 184
-    v170 = mul v169, v167
-    constrain v170 == v167
-    v171 = load v40 -> u1
-    v172 = not v167
-    v173 = mul v172, v171
-    v174 = unchecked_add v167, v173
-    store v174 at v40
-    v175 = unchecked_mul v162, v165
-    enable_side_effects u1 1
-    v176 = load v40 -> u1
-    v177 = not v176
-    enable_side_effects v177
-    v179 = array_get v9, index u32 9 -> u8
-    v180 = eq v179, u8 80
-    v181 = not v180
-    v182 = unchecked_mul v177, v181
-    enable_side_effects v182
-    v183 = array_get v9, index u32 9 -> u8
-    v184 = lt v183, u8 80
-    v185 = mul v184, v182
-    constrain v185 == v182
-    v186 = load v40 -> u1
-    v187 = not v182
-    v188 = mul v187, v186
-    v189 = unchecked_add v182, v188
-    store v189 at v40
-    v190 = unchecked_mul v177, v180
-    enable_side_effects u1 1
-    v191 = load v40 -> u1
-    v192 = not v191
-    enable_side_effects v192
-    v194 = array_get v9, index u32 10 -> u8
-    v195 = eq v194, u8 69
-    v196 = not v195
-    v197 = unchecked_mul v192, v196
-    enable_side_effects v197
-    v198 = array_get v9, index u32 10 -> u8
-    v199 = lt v198, u8 69
-    v200 = mul v199, v197
-    constrain v200 == v197
-    v201 = load v40 -> u1
-    v202 = not v197
-    v203 = mul v202, v201
-    v204 = unchecked_add v197, v203
-    store v204 at v40
-    v205 = unchecked_mul v192, v195
-    enable_side_effects u1 1
-    v206 = load v40 -> u1
-    v207 = not v206
-    enable_side_effects v207
-    v209 = array_get v9, index u32 11 -> u8
-    v210 = eq v209, u8 182
-    v211 = not v210
-    v212 = unchecked_mul v207, v211
-    enable_side_effects v212
-    v213 = array_get v9, index u32 11 -> u8
-    v214 = lt v213, u8 182
-    v215 = mul v214, v212
-    constrain v215 == v212
-    v216 = load v40 -> u1
-    v217 = not v212
-    v218 = mul v217, v216
-    v219 = unchecked_add v212, v218
-    store v219 at v40
-    v220 = unchecked_mul v207, v210
-    enable_side_effects u1 1
-    v221 = load v40 -> u1
-    v222 = not v221
-    enable_side_effects v222
-    v224 = array_get v9, index u32 12 -> u8
-    v225 = eq v224, u8 129
-    v226 = not v225
-    v227 = unchecked_mul v222, v226
-    enable_side_effects v227
-    v228 = array_get v9, index u32 12 -> u8
-    v229 = lt v228, u8 129
-    v230 = mul v229, v227
-    constrain v230 == v227
-    v231 = load v40 -> u1
-    v232 = not v227
-    v233 = mul v232, v231
-    v234 = unchecked_add v227, v233
-    store v234 at v40
-    v235 = unchecked_mul v222, v225
-    enable_side_effects u1 1
-    v236 = load v40 -> u1
-    v237 = not v236
-    enable_side_effects v237
-    v239 = array_get v9, index u32 13 -> u8
-    v240 = eq v239, u8 129
-    v241 = not v240
-    v242 = unchecked_mul v237, v241
-    enable_side_effects v242
-    v243 = array_get v9, index u32 13 -> u8
-    v244 = lt v243, u8 129
-    v245 = mul v244, v242
-    constrain v245 == v242
-    v246 = load v40 -> u1
-    v247 = not v242
-    v248 = mul v247, v246
-    v249 = unchecked_add v242, v248
-    store v249 at v40
-    v250 = unchecked_mul v237, v240
-    enable_side_effects u1 1
-    v251 = load v40 -> u1
-    v252 = not v251
-    enable_side_effects v252
-    v254 = array_get v9, index u32 14 -> u8
-    v255 = eq v254, u8 88
-    v256 = not v255
-    v257 = unchecked_mul v252, v256
-    enable_side_effects v257
-    v258 = array_get v9, index u32 14 -> u8
-    v259 = lt v258, u8 88
-    v260 = mul v259, v257
-    constrain v260 == v257
-    v261 = load v40 -> u1
-    v262 = not v257
-    v263 = mul v262, v261
-    v264 = unchecked_add v257, v263
-    store v264 at v40
-    v265 = unchecked_mul v252, v255
-    enable_side_effects u1 1
-    v266 = load v40 -> u1
-    v267 = not v266
-    enable_side_effects v267
-    v269 = array_get v9, index u32 15 -> u8
-    v270 = eq v269, u8 93
-    v271 = not v270
-    v272 = unchecked_mul v267, v271
-    enable_side_effects v272
-    v273 = array_get v9, index u32 15 -> u8
-    v274 = lt v273, u8 93
-    v275 = mul v274, v272
-    constrain v275 == v272
-    v276 = load v40 -> u1
-    v277 = not v272
-    v278 = mul v277, v276
-    v279 = unchecked_add v272, v278
-    store v279 at v40
-    v280 = unchecked_mul v267, v270
-    enable_side_effects u1 1
-    v281 = load v40 -> u1
-    v282 = not v281
-    enable_side_effects v282
-    v284 = array_get v9, index u32 16 -> u8
-    v285 = eq v284, u8 40
-    v286 = not v285
-    v287 = unchecked_mul v282, v286
-    enable_side_effects v287
-    v288 = array_get v9, index u32 16 -> u8
-    v289 = lt v288, u8 40
-    v290 = mul v289, v287
-    constrain v290 == v287
-    v291 = load v40 -> u1
-    v292 = not v287
-    v293 = mul v292, v291
-    v294 = unchecked_add v287, v293
-    store v294 at v40
-    v295 = unchecked_mul v282, v285
-    enable_side_effects u1 1
-    v296 = load v40 -> u1
-    v297 = not v296
-    enable_side_effects v297
-    v299 = array_get v9, index u32 17 -> u8
-    v300 = eq v299, u8 51
-    v301 = not v300
-    v302 = unchecked_mul v297, v301
-    enable_side_effects v302
-    v303 = array_get v9, index u32 17 -> u8
-    v304 = lt v303, u8 51
-    v305 = mul v304, v302
-    constrain v305 == v302
-    v306 = load v40 -> u1
-    v307 = not v302
-    v308 = mul v307, v306
-    v309 = unchecked_add v302, v308
-    store v309 at v40
-    v310 = unchecked_mul v297, v300
-    enable_side_effects u1 1
-    v311 = load v40 -> u1
-    v312 = not v311
-    enable_side_effects v312
-    v314 = array_get v9, index u32 18 -> u8
-    v315 = eq v314, u8 232
-    v316 = not v315
-    v317 = unchecked_mul v312, v316
-    enable_side_effects v317
-    v318 = array_get v9, index u32 18 -> u8
-    v319 = lt v318, u8 232
-    v320 = mul v319, v317
-    constrain v320 == v317
-    v321 = load v40 -> u1
-    v322 = not v317
-    v323 = mul v322, v321
-    v324 = unchecked_add v317, v323
-    store v324 at v40
-    v325 = unchecked_mul v312, v315
-    enable_side_effects u1 1
-    v326 = load v40 -> u1
-    v327 = not v326
-    enable_side_effects v327
-    v329 = array_get v9, index u32 19 -> u8
-    v330 = eq v329, u8 72
-    v331 = not v330
-    v332 = unchecked_mul v327, v331
-    enable_side_effects v332
-    v333 = array_get v9, index u32 19 -> u8
-    v334 = lt v333, u8 72
-    v335 = mul v334, v332
-    constrain v335 == v332
-    v336 = load v40 -> u1
-    v337 = not v332
-    v338 = mul v337, v336
-    v339 = unchecked_add v332, v338
-    store v339 at v40
-    v340 = unchecked_mul v327, v330
-    enable_side_effects u1 1
-    v341 = load v40 -> u1
-    v342 = not v341
-    enable_side_effects v342
-    v344 = array_get v9, index u32 20 -> u8
-    v345 = eq v344, u8 121
-    v346 = not v345
-    v347 = unchecked_mul v342, v346
-    enable_side_effects v347
-    v348 = array_get v9, index u32 20 -> u8
-    v349 = lt v348, u8 121
-    v350 = mul v349, v347
-    constrain v350 == v347
-    v351 = load v40 -> u1
-    v352 = not v347
-    v353 = mul v352, v351
-    v354 = unchecked_add v347, v353
-    store v354 at v40
-    v355 = unchecked_mul v342, v345
-    enable_side_effects u1 1
-    v356 = load v40 -> u1
-    v357 = not v356
-    enable_side_effects v357
-    v359 = array_get v9, index u32 21 -> u8
-    v360 = eq v359, u8 185
-    v361 = not v360
-    v362 = unchecked_mul v357, v361
-    enable_side_effects v362
-    v363 = array_get v9, index u32 21 -> u8
-    v364 = lt v363, u8 185
-    v365 = mul v364, v362
-    constrain v365 == v362
-    v366 = load v40 -> u1
-    v367 = not v362
-    v368 = mul v367, v366
-    v369 = unchecked_add v362, v368
-    store v369 at v40
-    v370 = unchecked_mul v357, v360
-    enable_side_effects u1 1
-    v371 = load v40 -> u1
-    v372 = not v371
-    enable_side_effects v372
-    v374 = array_get v9, index u32 22 -> u8
-    v375 = eq v374, u8 112
-    v376 = not v375
-    v377 = unchecked_mul v372, v376
-    enable_side_effects v377
-    v378 = array_get v9, index u32 22 -> u8
-    v379 = lt v378, u8 112
-    v380 = mul v379, v377
-    constrain v380 == v377
-    v381 = load v40 -> u1
-    v382 = not v377
-    v383 = mul v382, v381
-    v384 = unchecked_add v377, v383
-    store v384 at v40
-    v385 = unchecked_mul v372, v375
-    enable_side_effects u1 1
-    v386 = load v40 -> u1
-    v387 = not v386
-    enable_side_effects v387
-    v389 = array_get v9, index u32 23 -> u8
-    v390 = eq v389, u8 145
-    v391 = not v390
-    v392 = unchecked_mul v387, v391
-    enable_side_effects v392
-    v393 = array_get v9, index u32 23 -> u8
-    v394 = lt v393, u8 145
-    v395 = mul v394, v392
-    constrain v395 == v392
-    v396 = load v40 -> u1
-    v397 = not v392
-    v398 = mul v397, v396
-    v399 = unchecked_add v392, v398
-    store v399 at v40
-    v400 = unchecked_mul v387, v390
-    enable_side_effects u1 1
-    v401 = load v40 -> u1
-    v402 = not v401
-    enable_side_effects v402
-    v404 = array_get v9, index u32 24 -> u8
-    v405 = eq v404, u8 67
-    v406 = not v405
-    v407 = unchecked_mul v402, v406
-    enable_side_effects v407
-    v408 = array_get v9, index u32 24 -> u8
-    v409 = lt v408, u8 67
-    v410 = mul v409, v407
-    constrain v410 == v407
-    v411 = load v40 -> u1
-    v412 = not v407
-    v413 = mul v412, v411
-    v414 = unchecked_add v407, v413
-    store v414 at v40
-    v415 = unchecked_mul v402, v405
-    enable_side_effects u1 1
-    v416 = load v40 -> u1
-    v417 = not v416
-    enable_side_effects v417
-    v419 = array_get v9, index u32 25 -> u8
-    v420 = eq v419, u8 225
-    v421 = not v420
-    v422 = unchecked_mul v417, v421
-    enable_side_effects v422
-    v423 = array_get v9, index u32 25 -> u8
-    v424 = lt v423, u8 225
-    v425 = mul v424, v422
-    constrain v425 == v422
-    v426 = load v40 -> u1
-    v427 = not v422
-    v428 = mul v427, v426
-    v429 = unchecked_add v422, v428
-    store v429 at v40
-    v430 = unchecked_mul v417, v420
-    enable_side_effects u1 1
-    v431 = load v40 -> u1
-    v432 = not v431
-    enable_side_effects v432
-    v434 = array_get v9, index u32 26 -> u8
-    v435 = eq v434, u8 245
-    v436 = not v435
-    v437 = unchecked_mul v432, v436
-    enable_side_effects v437
-    v438 = array_get v9, index u32 26 -> u8
-    v439 = lt v438, u8 245
-    v440 = mul v439, v437
-    constrain v440 == v437
-    v441 = load v40 -> u1
-    v442 = not v437
-    v443 = mul v442, v441
-    v444 = unchecked_add v437, v443
-    store v444 at v40
-    v445 = unchecked_mul v432, v435
-    enable_side_effects u1 1
-    v446 = load v40 -> u1
-    v447 = not v446
-    enable_side_effects v447
-    v449 = array_get v9, index u32 27 -> u8
-    v450 = eq v449, u8 147
-    v451 = not v450
-    v452 = unchecked_mul v447, v451
-    enable_side_effects v452
-    v453 = array_get v9, index u32 27 -> u8
-    v454 = lt v453, u8 147
-    v455 = mul v454, v452
-    constrain v455 == v452
-    v456 = load v40 -> u1
-    v457 = not v452
-    v458 = mul v457, v456
-    v459 = unchecked_add v452, v458
-    store v459 at v40
-    v460 = unchecked_mul v447, v450
-    enable_side_effects u1 1
-    v461 = load v40 -> u1
-    v462 = not v461
-    enable_side_effects v462
-    v464 = array_get v9, index u32 28 -> u8
-    v465 = eq v464, u8 240
-    v466 = not v465
-    v467 = unchecked_mul v462, v466
-    enable_side_effects v467
-    v468 = array_get v9, index u32 28 -> u8
-    v469 = lt v468, u8 240
-    v470 = mul v469, v467
-    constrain v470 == v467
-    v471 = load v40 -> u1
-    v472 = not v467
-    v473 = mul v472, v471
-    v474 = unchecked_add v467, v473
-    store v474 at v40
-    v475 = unchecked_mul v462, v465
-    enable_side_effects u1 1
-    v476 = load v40 -> u1
-    v477 = not v476
-    enable_side_effects v477
-    v479 = array_get v9, index u32 29 -> u8
-    v480 = eq v479, u8 0
-    v481 = not v480
-    v482 = unchecked_mul v477, v481
-    enable_side_effects v482
-    v483 = array_get v9, index u32 29 -> u8
-    constrain u1 0 == v482
-    v484 = load v40 -> u1
-    v485 = not v482
-    v486 = mul v485, v484
-    v487 = unchecked_add v482, v486
-    store v487 at v40
-    v488 = unchecked_mul v477, v480
-    enable_side_effects u1 1
-    v489 = load v40 -> u1
-    v490 = not v489
-    enable_side_effects v490
-    v492 = array_get v9, index u32 30 -> u8
-    v493 = eq v492, u8 0
-    v494 = not v493
-    v495 = unchecked_mul v490, v494
-    enable_side_effects v495
-    v496 = array_get v9, index u32 30 -> u8
-    constrain u1 0 == v495
-    v497 = load v40 -> u1
-    v498 = not v495
-    v499 = mul v498, v497
-    v500 = unchecked_add v495, v499
-    store v500 at v40
-    v501 = unchecked_mul v490, v493
-    enable_side_effects u1 1
-    v502 = load v40 -> u1
-    v503 = not v502
-    enable_side_effects v503
-    v505 = array_get v9, index u32 31 -> u8
-    v506 = eq v505, u8 1
-    v507 = not v506
-    v508 = unchecked_mul v503, v507
-    enable_side_effects v508
-    v509 = array_get v9, index u32 31 -> u8
-    v510 = eq v509, u8 0
-    v511 = cast v508 as u8
-    v512 = unchecked_mul v509, v511
-    constrain v512 == u8 0
-    v513 = load v40 -> u1
-    v514 = not v508
-    v515 = mul v514, v513
-    v516 = unchecked_add v508, v515
-    store v516 at v40
-    v517 = unchecked_mul v503, v506
-    enable_side_effects u1 1
-    v518 = load v40 -> u1
-    constrain v518 == u1 1
-    v519 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v520 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v521 = allocate -> &mut u1
-    store u1 0 at v521
-    enable_side_effects u1 1
-    v522 = load v521 -> u1
-    store u1 1 at v521
-    enable_side_effects u1 1
-    v523 = load v521 -> u1
-    v524 = not v523
-    enable_side_effects v524
-    v525 = load v521 -> u1
-    v526 = mul v523, v525
-    v527 = unchecked_add v524, v526
-    store v527 at v521
-    enable_side_effects u1 1
-    v528 = load v521 -> u1
-    v529 = not v528
-    enable_side_effects v529
-    v530 = load v521 -> u1
-    v531 = mul v528, v530
-    v532 = unchecked_add v529, v531
-    store v532 at v521
-    enable_side_effects u1 1
-    v533 = load v521 -> u1
-    v534 = not v533
-    enable_side_effects v534
-    v535 = load v521 -> u1
-    v536 = mul v533, v535
-    v537 = unchecked_add v534, v536
-    store v537 at v521
-    enable_side_effects u1 1
-    v538 = load v521 -> u1
-    v539 = not v538
-    enable_side_effects v539
-    v540 = load v521 -> u1
-    v541 = mul v538, v540
-    v542 = unchecked_add v539, v541
-    store v542 at v521
-    enable_side_effects u1 1
-    v543 = load v521 -> u1
-    v544 = not v543
-    enable_side_effects v544
-    v545 = load v521 -> u1
-    v546 = mul v543, v545
-    v547 = unchecked_add v544, v546
-    store v547 at v521
-    enable_side_effects u1 1
-    v548 = load v521 -> u1
-    v549 = not v548
-    enable_side_effects v549
-    v550 = load v521 -> u1
-    v551 = mul v548, v550
-    v552 = unchecked_add v549, v551
-    store v552 at v521
-    enable_side_effects u1 1
-    v553 = load v521 -> u1
-    v554 = not v553
-    enable_side_effects v554
-    v555 = load v521 -> u1
-    v556 = mul v553, v555
-    v557 = unchecked_add v554, v556
-    store v557 at v521
-    enable_side_effects u1 1
-    v558 = load v521 -> u1
-    v559 = not v558
-    enable_side_effects v559
-    v560 = load v521 -> u1
-    v561 = mul v558, v560
-    v562 = unchecked_add v559, v561
-    store v562 at v521
-    enable_side_effects u1 1
-    v563 = load v521 -> u1
-    v564 = not v563
-    enable_side_effects v564
-    v565 = load v521 -> u1
-    v566 = mul v563, v565
-    v567 = unchecked_add v564, v566
-    store v567 at v521
-    enable_side_effects u1 1
-    v568 = load v521 -> u1
-    v569 = not v568
-    enable_side_effects v569
-    v570 = load v521 -> u1
-    v571 = mul v568, v570
-    v572 = unchecked_add v569, v571
-    store v572 at v521
-    enable_side_effects u1 1
-    v573 = load v521 -> u1
-    v574 = not v573
-    enable_side_effects v574
-    v575 = load v521 -> u1
-    v576 = mul v573, v575
-    v577 = unchecked_add v574, v576
-    store v577 at v521
-    enable_side_effects u1 1
-    v578 = load v521 -> u1
-    v579 = not v578
-    enable_side_effects v579
-    v580 = load v521 -> u1
-    v581 = mul v578, v580
-    v582 = unchecked_add v579, v581
-    store v582 at v521
-    enable_side_effects u1 1
-    v583 = load v521 -> u1
-    v584 = not v583
-    enable_side_effects v584
-    v585 = load v521 -> u1
-    v586 = mul v583, v585
-    v587 = unchecked_add v584, v586
-    store v587 at v521
-    enable_side_effects u1 1
-    v588 = load v521 -> u1
-    v589 = not v588
-    enable_side_effects v589
-    v590 = load v521 -> u1
-    v591 = mul v588, v590
-    v592 = unchecked_add v589, v591
-    store v592 at v521
-    enable_side_effects u1 1
-    v593 = load v521 -> u1
-    v594 = not v593
-    enable_side_effects v594
-    v595 = load v521 -> u1
-    v596 = mul v593, v595
-    v597 = unchecked_add v594, v596
-    store v597 at v521
-    enable_side_effects u1 1
-    v598 = load v521 -> u1
-    v599 = not v598
-    enable_side_effects v599
-    v600 = load v521 -> u1
-    v601 = mul v598, v600
-    v602 = unchecked_add v599, v601
-    store v602 at v521
-    enable_side_effects u1 1
-    v603 = load v521 -> u1
-    v604 = not v603
-    enable_side_effects v604
-    v605 = load v521 -> u1
-    v606 = mul v603, v605
-    v607 = unchecked_add v604, v606
-    store v607 at v521
-    enable_side_effects u1 1
-    v608 = load v521 -> u1
-    v609 = not v608
-    enable_side_effects v609
-    v610 = load v521 -> u1
-    v611 = mul v608, v610
-    v612 = unchecked_add v609, v611
-    store v612 at v521
-    enable_side_effects u1 1
-    v613 = load v521 -> u1
-    v614 = not v613
-    enable_side_effects v614
-    v615 = load v521 -> u1
-    v616 = mul v613, v615
-    v617 = unchecked_add v614, v616
-    store v617 at v521
-    enable_side_effects u1 1
-    v618 = load v521 -> u1
-    v619 = not v618
-    enable_side_effects v619
-    v620 = load v521 -> u1
-    v621 = mul v618, v620
-    v622 = unchecked_add v619, v621
-    store v622 at v521
-    enable_side_effects u1 1
-    v623 = load v521 -> u1
-    v624 = not v623
-    enable_side_effects v624
-    v625 = load v521 -> u1
-    v626 = mul v623, v625
-    v627 = unchecked_add v624, v626
-    store v627 at v521
-    enable_side_effects u1 1
-    v628 = load v521 -> u1
-    v629 = not v628
-    enable_side_effects v629
-    v630 = load v521 -> u1
-    v631 = mul v628, v630
-    v632 = unchecked_add v629, v631
-    store v632 at v521
-    enable_side_effects u1 1
-    v633 = load v521 -> u1
-    v634 = not v633
-    enable_side_effects v634
-    v635 = load v521 -> u1
-    v636 = mul v633, v635
-    v637 = unchecked_add v634, v636
-    store v637 at v521
-    enable_side_effects u1 1
-    v638 = load v521 -> u1
-    v639 = not v638
-    enable_side_effects v639
-    v640 = load v521 -> u1
-    v641 = mul v638, v640
-    v642 = unchecked_add v639, v641
-    store v642 at v521
-    enable_side_effects u1 1
-    v643 = load v521 -> u1
-    v644 = not v643
-    enable_side_effects v644
-    v645 = load v521 -> u1
-    v646 = mul v643, v645
-    v647 = unchecked_add v644, v646
-    store v647 at v521
-    enable_side_effects u1 1
-    v648 = load v521 -> u1
-    v649 = not v648
-    enable_side_effects v649
-    v650 = load v521 -> u1
-    v651 = mul v648, v650
-    v652 = unchecked_add v649, v651
-    store v652 at v521
-    enable_side_effects u1 1
-    v653 = load v521 -> u1
-    v654 = not v653
-    enable_side_effects v654
-    v655 = load v521 -> u1
-    v656 = mul v653, v655
-    v657 = unchecked_add v654, v656
-    store v657 at v521
-    enable_side_effects u1 1
-    v658 = load v521 -> u1
-    v659 = not v658
-    enable_side_effects v659
-    v660 = load v521 -> u1
-    v661 = mul v658, v660
-    v662 = unchecked_add v659, v661
-    store v662 at v521
-    enable_side_effects u1 1
-    v663 = load v521 -> u1
-    v664 = not v663
-    enable_side_effects u1 1
-    v665 = load v521 -> u1
-    v666 = not v665
-    enable_side_effects u1 1
-    v667 = load v521 -> u1
-    v668 = not v667
-    enable_side_effects v668
-    v669 = load v521 -> u1
-    v670 = mul v667, v669
-    v671 = unchecked_add v668, v670
-    store v671 at v521
-    enable_side_effects u1 1
-    v672 = load v521 -> u1
-    constrain v672 == u1 1
-    v673 = allocate -> &mut [u8; 32]
-    v674 = array_get v9, index u32 0 -> u8
-    v675 = make_array [v674, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v676 = array_get v9, index u32 1 -> u8
-    v677 = make_array [v674, v676, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v678 = array_get v9, index u32 2 -> u8
-    v679 = make_array [v674, v676, v678, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v680 = array_get v9, index u32 3 -> u8
-    v681 = make_array [v674, v676, v678, v680, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v682 = array_get v9, index u32 4 -> u8
-    v683 = make_array [v674, v676, v678, v680, v682, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v684 = array_get v9, index u32 5 -> u8
-    v685 = make_array [v674, v676, v678, v680, v682, v684, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v686 = array_get v9, index u32 6 -> u8
-    v687 = make_array [v674, v676, v678, v680, v682, v684, v686, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v688 = array_get v9, index u32 7 -> u8
-    v689 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v690 = array_get v9, index u32 8 -> u8
-    v691 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v692 = array_get v9, index u32 9 -> u8
-    v693 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v694 = array_get v9, index u32 10 -> u8
-    v695 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v696 = array_get v9, index u32 11 -> u8
-    v697 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v698 = array_get v9, index u32 12 -> u8
-    v699 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v700 = array_get v9, index u32 13 -> u8
-    v701 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v702 = array_get v9, index u32 14 -> u8
-    v703 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v704 = array_get v9, index u32 15 -> u8
-    v705 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v706 = array_get v9, index u32 16 -> u8
-    v707 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v708 = array_get v9, index u32 17 -> u8
-    v709 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v710 = array_get v9, index u32 18 -> u8
-    v711 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v712 = array_get v9, index u32 19 -> u8
-    v713 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v714 = array_get v9, index u32 20 -> u8
-    v715 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v716 = array_get v9, index u32 21 -> u8
-    v717 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v718 = array_get v9, index u32 22 -> u8
-    v719 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v720 = array_get v9, index u32 23 -> u8
-    v721 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v722 = array_get v9, index u32 24 -> u8
-    v723 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v724 = array_get v9, index u32 25 -> u8
-    v725 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v726 = array_get v9, index u32 26 -> u8
-    v727 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v728 = array_get v9, index u32 27 -> u8
-    v729 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v730 = array_get v9, index u32 28 -> u8
-    v731 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, u8 0, u8 0, u8 0] : [u8; 32]
-    v732 = array_get v9, index u32 29 -> u8
-    v733 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, v732, u8 0, u8 0] : [u8; 32]
-    v734 = array_get v9, index u32 30 -> u8
-    v735 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, v732, v734, u8 0] : [u8; 32]
-    v736 = array_get v9, index u32 31 -> u8
-    v737 = make_array [v674, v676, v678, v680, v682, v684, v686, v688, v690, v692, v694, v696, v698, v700, v702, v704, v706, v708, v710, v712, v714, v716, v718, v720, v722, v724, v726, v728, v730, v732, v734, v736] : [u8; 32]
-    v738 = allocate -> &mut Field
-    v739 = allocate -> &mut Field
-    v740 = allocate -> &mut Field
-    v741 = cast v704 as Field
-    v742 = cast v736 as Field
-    v743 = cast v702 as Field
-    v745 = mul v743, Field 256
-    v746 = add v741, v745
-    v747 = cast v734 as Field
-    v748 = mul v747, Field 256
-    v749 = add v742, v748
-    v750 = cast v700 as Field
-    v752 = mul v750, Field 65536
-    v753 = add v746, v752
-    v754 = cast v732 as Field
-    v755 = mul v754, Field 65536
-    v756 = add v749, v755
-    v757 = cast v698 as Field
-    v759 = mul v757, Field 16777216
-    v760 = add v753, v759
-    v761 = cast v730 as Field
-    v762 = mul v761, Field 16777216
-    v763 = add v756, v762
-    v764 = cast v696 as Field
-    v766 = mul v764, Field 4294967296
-    v767 = add v760, v766
-    v768 = cast v728 as Field
-    v769 = mul v768, Field 4294967296
-    v770 = add v763, v769
-    v771 = cast v694 as Field
-    v773 = mul v771, Field 1099511627776
-    v774 = add v767, v773
-    v775 = cast v726 as Field
-    v776 = mul v775, Field 1099511627776
-    v777 = add v770, v776
-    v778 = cast v692 as Field
-    v780 = mul v778, Field 281474976710656
-    v781 = add v774, v780
-    v782 = cast v724 as Field
-    v783 = mul v782, Field 281474976710656
-    v784 = add v777, v783
-    v785 = cast v690 as Field
-    v787 = mul v785, Field 72057594037927936
-    v788 = add v781, v787
-    v789 = cast v722 as Field
-    v790 = mul v789, Field 72057594037927936
-    v791 = add v784, v790
-    v792 = cast v688 as Field
-    v794 = mul v792, Field 18446744073709551616
-    v795 = add v788, v794
-    v796 = cast v720 as Field
-    v797 = mul v796, Field 18446744073709551616
-    v798 = add v791, v797
-    v799 = cast v686 as Field
-    v801 = mul v799, Field 4722366482869645213696
-    v802 = add v795, v801
-    v803 = cast v718 as Field
-    v804 = mul v803, Field 4722366482869645213696
-    v805 = add v798, v804
-    v806 = cast v684 as Field
-    v808 = mul v806, Field 1208925819614629174706176
-    v809 = add v802, v808
-    v810 = cast v716 as Field
-    v811 = mul v810, Field 1208925819614629174706176
-    v812 = add v805, v811
-    v813 = cast v682 as Field
-    v815 = mul v813, Field 309485009821345068724781056
-    v816 = add v809, v815
-    v817 = cast v714 as Field
-    v818 = mul v817, Field 309485009821345068724781056
-    v819 = add v812, v818
-    v820 = cast v680 as Field
-    v822 = mul v820, Field 79228162514264337593543950336
-    v823 = add v816, v822
-    v824 = cast v712 as Field
-    v825 = mul v824, Field 79228162514264337593543950336
-    v826 = add v819, v825
-    v827 = cast v678 as Field
-    v829 = mul v827, Field 20282409603651670423947251286016
-    v830 = add v823, v829
-    v831 = cast v710 as Field
-    v832 = mul v831, Field 20282409603651670423947251286016
-    v833 = add v826, v832
-    v834 = cast v676 as Field
-    v836 = mul v834, Field 5192296858534827628530496329220096
-    v837 = add v830, v836
-    v838 = cast v708 as Field
-    v839 = mul v838, Field 5192296858534827628530496329220096
-    v840 = add v833, v839
-    v841 = cast v674 as Field
-    v843 = mul v841, Field 1329227995784915872903807060280344576
-    v844 = add v837, v843
-    v845 = cast v706 as Field
-    v846 = mul v845, Field 1329227995784915872903807060280344576
-    v847 = add v840, v846
-    v849 = mul v844, Field 340282366920938463463374607431768211456
-    v850 = add v847, v849
-    v851 = allocate -> &mut Field
-    store Field 0 at v851
-    v853 = eq v4, Field 0
-    enable_side_effects v853
-    v854 = not v853
-    enable_side_effects v854
-    v856 = call f1(v4, Field 0) -> u1
-    v857 = unchecked_mul v854, v856
-    enable_side_effects v857
-    v859, v860 = call f3(Field 0) -> (Field, Field)
-    v861 = cast v857 as Field
-    v862 = mul v859, v861
-    range_check v862 to 128 bits
-    v863 = cast v857 as Field
-    v864 = mul v860, v863
-    range_check v864 to 128 bits
-    v865 = mul Field 340282366920938463463374607431768211456, v860
-    v866 = add v859, v865
-    v867 = eq Field 0, v866
-    v868 = cast v857 as Field
-    v869 = mul v866, v868
-    constrain Field 0 == v869
-    v872 = call f2(Field 53438638232309528389504892708671455233, v859) -> u1
-    v873 = sub Field 53438638232309528389504892708671455233, v859
-    v875 = sub v873, Field 1
-    v876 = cast v872 as Field
-    v877 = mul v876, Field 340282366920938463463374607431768211456
-    v878 = add v875, v877
-    v880 = sub Field 64323764613183177041862057485226039389, v860
-    v881 = cast v872 as Field
-    v882 = sub v880, v881
-    v883 = cast v857 as Field
-    v884 = mul v878, v883
-    range_check v884 to 128 bits
-    v885 = cast v857 as Field
-    v886 = mul v882, v885
-    range_check v886 to 128 bits
-    v888, v889 = call f3(v4) -> (Field, Field)
-    v890 = cast v857 as Field
-    v891 = mul v888, v890
-    range_check v891 to 128 bits
-    v892 = cast v857 as Field
-    v893 = mul v889, v892
-    range_check v893 to 128 bits
-    v894 = mul Field 340282366920938463463374607431768211456, v889
-    v895 = add v888, v894
-    v896 = eq v4, v895
-    v897 = cast v857 as Field
-    v898 = mul v4, v897
-    v899 = mul v895, v897
-    constrain v898 == v899
-    v901 = call f2(Field 53438638232309528389504892708671455233, v888) -> u1
-    v902 = sub Field 53438638232309528389504892708671455233, v888
-    v903 = sub v902, Field 1
-    v904 = cast v901 as Field
-    v905 = mul v904, Field 340282366920938463463374607431768211456
-    v906 = add v903, v905
-    v907 = sub Field 64323764613183177041862057485226039389, v889
-    v908 = cast v901 as Field
-    v909 = sub v907, v908
-    v910 = cast v857 as Field
-    v911 = mul v906, v910
-    range_check v911 to 128 bits
-    v912 = cast v857 as Field
-    v913 = mul v909, v912
-    range_check v913 to 128 bits
-    v915 = call f2(v859, v888) -> u1
-    v916 = sub v859, v888
-    v917 = sub v916, Field 1
-    v918 = cast v915 as Field
-    v919 = mul v918, Field 340282366920938463463374607431768211456
-    v920 = add v917, v919
-    v921 = sub v860, v889
-    v922 = cast v915 as Field
-    v923 = sub v921, v922
-    v924 = cast v857 as Field
-    v925 = mul v920, v924
-    range_check v925 to 128 bits
-    v926 = cast v857 as Field
-    v927 = mul v923, v926
-    range_check v927 to 128 bits
-    v928 = not v856
-    v929 = unchecked_mul v854, v928
-    enable_side_effects v929
-    v931, v932 = call f3(v4) -> (Field, Field)
-    v933 = cast v929 as Field
-    v934 = mul v931, v933
-    range_check v934 to 128 bits
-    v935 = cast v929 as Field
-    v936 = mul v932, v935
-    range_check v936 to 128 bits
-    v937 = mul Field 340282366920938463463374607431768211456, v932
-    v938 = add v931, v937
-    v939 = eq v4, v938
-    v940 = cast v929 as Field
-    v941 = mul v4, v940
-    v942 = mul v938, v940
-    constrain v941 == v942
-    v944 = call f2(Field 53438638232309528389504892708671455233, v931) -> u1
-    v945 = sub Field 53438638232309528389504892708671455233, v931
-    v946 = sub v945, Field 1
-    v947 = cast v944 as Field
-    v948 = mul v947, Field 340282366920938463463374607431768211456
-    v949 = add v946, v948
-    v950 = sub Field 64323764613183177041862057485226039389, v932
-    v951 = cast v944 as Field
-    v952 = sub v950, v951
-    v953 = cast v929 as Field
-    v954 = mul v949, v953
-    range_check v954 to 128 bits
-    v955 = cast v929 as Field
-    v956 = mul v952, v955
-    range_check v956 to 128 bits
-    v958, v959 = call f3(Field 0) -> (Field, Field)
-    v960 = cast v929 as Field
-    v961 = mul v958, v960
-    range_check v961 to 128 bits
-    v962 = cast v929 as Field
-    v963 = mul v959, v962
-    range_check v963 to 128 bits
-    v964 = mul Field 340282366920938463463374607431768211456, v959
-    v965 = add v958, v964
-    v966 = eq Field 0, v965
-    v967 = cast v929 as Field
-    v968 = mul v965, v967
-    constrain Field 0 == v968
-    v970 = call f2(Field 53438638232309528389504892708671455233, v958) -> u1
-    v971 = sub Field 53438638232309528389504892708671455233, v958
-    v972 = sub v971, Field 1
-    v973 = cast v970 as Field
-    v974 = mul v973, Field 340282366920938463463374607431768211456
-    v975 = add v972, v974
-    v976 = sub Field 64323764613183177041862057485226039389, v959
-    v977 = cast v970 as Field
-    v978 = sub v976, v977
-    v979 = cast v929 as Field
-    v980 = mul v975, v979
-    range_check v980 to 128 bits
-    v981 = cast v929 as Field
-    v982 = mul v978, v981
-    range_check v982 to 128 bits
-    v984 = call f2(v931, v958) -> u1
-    v985 = sub v931, v958
-    v986 = sub v985, Field 1
-    v987 = cast v984 as Field
-    v988 = mul v987, Field 340282366920938463463374607431768211456
-    v989 = add v986, v988
-    v990 = sub v932, v959
-    v991 = cast v984 as Field
-    v992 = sub v990, v991
-    v993 = cast v929 as Field
-    v994 = mul v989, v993
-    range_check v994 to 128 bits
-    v995 = cast v929 as Field
-    v996 = mul v992, v995
-    range_check v996 to 128 bits
-    enable_side_effects v929
-    v997 = load v851 -> Field
-    v998 = not v929
-    v999 = cast v929 as Field
-    v1000 = cast v998 as Field
-    v1001 = mul v1000, v997
-    v1002 = add v999, v1001
-    store v1002 at v851
-    enable_side_effects u1 1
-    v1003 = load v851 -> Field
-    v1004 = sub v1003, v850
-    return v1004
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Mem2Reg (3rd):
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = allocate -> &mut Field
-    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v40 = allocate -> &mut u1
-    enable_side_effects u1 1
-    v43 = array_get v9, index u32 0 -> u8
-    v44 = eq v43, u8 48
-    v45 = not v44
-    enable_side_effects v45
-    v46 = array_get v9, index u32 0 -> u8
-    v47 = lt v46, u8 48
-    v48 = mul v47, v45
-    constrain v48 == v45
-    enable_side_effects u1 1
-    enable_side_effects v44
-    v50 = array_get v9, index u32 1 -> u8
-    v51 = eq v50, u8 100
-    v52 = not v51
-    v53 = mul v44, v52
-    enable_side_effects v53
-    v54 = array_get v9, index u32 1 -> u8
-    v55 = lt v54, u8 100
-    v56 = mul v55, v53
-    constrain v56 == v53
-    v57 = not v53
-    v58 = mul v57, v45
-    v59 = unchecked_add v53, v58
-    v60 = mul v44, v51
-    enable_side_effects u1 1
-    v61 = not v59
-    enable_side_effects v61
-    v63 = array_get v9, index u32 2 -> u8
-    v64 = eq v63, u8 78
-    v65 = not v64
-    v66 = mul v61, v65
-    enable_side_effects v66
-    v67 = array_get v9, index u32 2 -> u8
-    v68 = lt v67, u8 78
-    v69 = mul v68, v66
-    constrain v69 == v66
-    v70 = not v66
-    v71 = mul v70, v59
-    v72 = unchecked_add v66, v71
-    v73 = mul v61, v64
-    enable_side_effects u1 1
-    v74 = not v72
-    enable_side_effects v74
-    v76 = array_get v9, index u32 3 -> u8
-    v77 = eq v76, u8 114
-    v78 = not v77
-    v79 = mul v74, v78
-    enable_side_effects v79
-    v80 = array_get v9, index u32 3 -> u8
-    v81 = lt v80, u8 114
-    v82 = mul v81, v79
-    constrain v82 == v79
-    v83 = not v79
-    v84 = mul v83, v72
-    v85 = unchecked_add v79, v84
-    v86 = mul v74, v77
-    enable_side_effects u1 1
-    v87 = not v85
-    enable_side_effects v87
-    v89 = array_get v9, index u32 4 -> u8
-    v90 = eq v89, u8 225
-    v91 = not v90
-    v92 = mul v87, v91
-    enable_side_effects v92
-    v93 = array_get v9, index u32 4 -> u8
-    v94 = lt v93, u8 225
-    v95 = mul v94, v92
-    constrain v95 == v92
-    v96 = not v92
-    v97 = mul v96, v85
-    v98 = unchecked_add v92, v97
-    v99 = mul v87, v90
-    enable_side_effects u1 1
-    v100 = not v98
-    enable_side_effects v100
-    v102 = array_get v9, index u32 5 -> u8
-    v103 = eq v102, u8 49
-    v104 = not v103
-    v105 = mul v100, v104
-    enable_side_effects v105
-    v106 = array_get v9, index u32 5 -> u8
-    v107 = lt v106, u8 49
-    v108 = mul v107, v105
-    constrain v108 == v105
-    v109 = not v105
-    v110 = mul v109, v98
-    v111 = unchecked_add v105, v110
-    v112 = mul v100, v103
-    enable_side_effects u1 1
-    v113 = not v111
-    enable_side_effects v113
-    v115 = array_get v9, index u32 6 -> u8
-    v116 = eq v115, u8 160
-    v117 = not v116
-    v118 = mul v113, v117
-    enable_side_effects v118
-    v119 = array_get v9, index u32 6 -> u8
-    v120 = lt v119, u8 160
-    v121 = mul v120, v118
-    constrain v121 == v118
-    v122 = not v118
-    v123 = mul v122, v111
-    v124 = unchecked_add v118, v123
-    v125 = mul v113, v116
-    enable_side_effects u1 1
-    v126 = not v124
-    enable_side_effects v126
-    v128 = array_get v9, index u32 7 -> u8
-    v129 = eq v128, u8 41
-    v130 = not v129
-    v131 = mul v126, v130
-    enable_side_effects v131
-    v132 = array_get v9, index u32 7 -> u8
-    v133 = lt v132, u8 41
-    v134 = mul v133, v131
-    constrain v134 == v131
-    v135 = not v131
-    v136 = mul v135, v124
-    v137 = unchecked_add v131, v136
-    v138 = mul v126, v129
-    enable_side_effects u1 1
-    v139 = not v137
-    enable_side_effects v139
-    v141 = array_get v9, index u32 8 -> u8
-    v142 = eq v141, u8 184
-    v143 = not v142
-    v144 = mul v139, v143
-    enable_side_effects v144
-    v145 = array_get v9, index u32 8 -> u8
-    v146 = lt v145, u8 184
-    v147 = mul v146, v144
-    constrain v147 == v144
-    v148 = not v144
-    v149 = mul v148, v137
-    v150 = unchecked_add v144, v149
-    v151 = mul v139, v142
-    enable_side_effects u1 1
-    v152 = not v150
-    enable_side_effects v152
-    v154 = array_get v9, index u32 9 -> u8
-    v155 = eq v154, u8 80
-    v156 = not v155
-    v157 = mul v152, v156
-    enable_side_effects v157
-    v158 = array_get v9, index u32 9 -> u8
-    v159 = lt v158, u8 80
-    v160 = mul v159, v157
-    constrain v160 == v157
-    v161 = not v157
-    v162 = mul v161, v150
-    v163 = unchecked_add v157, v162
-    v164 = mul v152, v155
-    enable_side_effects u1 1
-    v165 = not v163
-    enable_side_effects v165
-    v167 = array_get v9, index u32 10 -> u8
-    v168 = eq v167, u8 69
-    v169 = not v168
-    v170 = mul v165, v169
-    enable_side_effects v170
-    v171 = array_get v9, index u32 10 -> u8
-    v172 = lt v171, u8 69
-    v173 = mul v172, v170
-    constrain v173 == v170
-    v174 = not v170
-    v175 = mul v174, v163
-    v176 = unchecked_add v170, v175
-    v177 = mul v165, v168
-    enable_side_effects u1 1
-    v178 = not v176
-    enable_side_effects v178
-    v180 = array_get v9, index u32 11 -> u8
-    v181 = eq v180, u8 182
-    v182 = not v181
-    v183 = mul v178, v182
-    enable_side_effects v183
-    v184 = array_get v9, index u32 11 -> u8
-    v185 = lt v184, u8 182
-    v186 = mul v185, v183
-    constrain v186 == v183
-    v187 = not v183
-    v188 = mul v187, v176
-    v189 = unchecked_add v183, v188
-    v190 = mul v178, v181
-    enable_side_effects u1 1
-    v191 = not v189
-    enable_side_effects v191
-    v193 = array_get v9, index u32 12 -> u8
-    v194 = eq v193, u8 129
-    v195 = not v194
-    v196 = mul v191, v195
-    enable_side_effects v196
-    v197 = array_get v9, index u32 12 -> u8
-    v198 = lt v197, u8 129
-    v199 = mul v198, v196
-    constrain v199 == v196
-    v200 = not v196
-    v201 = mul v200, v189
-    v202 = unchecked_add v196, v201
-    v203 = mul v191, v194
-    enable_side_effects u1 1
-    v204 = not v202
-    enable_side_effects v204
-    v206 = array_get v9, index u32 13 -> u8
-    v207 = eq v206, u8 129
-    v208 = not v207
-    v209 = mul v204, v208
-    enable_side_effects v209
-    v210 = array_get v9, index u32 13 -> u8
-    v211 = lt v210, u8 129
-    v212 = mul v211, v209
-    constrain v212 == v209
-    v213 = not v209
-    v214 = mul v213, v202
-    v215 = unchecked_add v209, v214
-    v216 = mul v204, v207
-    enable_side_effects u1 1
-    v217 = not v215
-    enable_side_effects v217
-    v219 = array_get v9, index u32 14 -> u8
-    v220 = eq v219, u8 88
-    v221 = not v220
-    v222 = mul v217, v221
-    enable_side_effects v222
-    v223 = array_get v9, index u32 14 -> u8
-    v224 = lt v223, u8 88
-    v225 = mul v224, v222
-    constrain v225 == v222
-    v226 = not v222
-    v227 = mul v226, v215
-    v228 = unchecked_add v222, v227
-    v229 = mul v217, v220
-    enable_side_effects u1 1
-    v230 = not v228
-    enable_side_effects v230
-    v232 = array_get v9, index u32 15 -> u8
-    v233 = eq v232, u8 93
-    v234 = not v233
-    v235 = mul v230, v234
-    enable_side_effects v235
-    v236 = array_get v9, index u32 15 -> u8
-    v237 = lt v236, u8 93
-    v238 = mul v237, v235
-    constrain v238 == v235
-    v239 = not v235
-    v240 = mul v239, v228
-    v241 = unchecked_add v235, v240
-    v242 = mul v230, v233
-    enable_side_effects u1 1
-    v243 = not v241
-    enable_side_effects v243
-    v245 = array_get v9, index u32 16 -> u8
-    v246 = eq v245, u8 40
-    v247 = not v246
-    v248 = mul v243, v247
-    enable_side_effects v248
-    v249 = array_get v9, index u32 16 -> u8
-    v250 = lt v249, u8 40
-    v251 = mul v250, v248
-    constrain v251 == v248
-    v252 = not v248
-    v253 = mul v252, v241
-    v254 = unchecked_add v248, v253
-    v255 = mul v243, v246
-    enable_side_effects u1 1
-    v256 = not v254
-    enable_side_effects v256
-    v258 = array_get v9, index u32 17 -> u8
-    v259 = eq v258, u8 51
-    v260 = not v259
-    v261 = mul v256, v260
-    enable_side_effects v261
-    v262 = array_get v9, index u32 17 -> u8
-    v263 = lt v262, u8 51
-    v264 = mul v263, v261
-    constrain v264 == v261
-    v265 = not v261
-    v266 = mul v265, v254
-    v267 = unchecked_add v261, v266
-    v268 = mul v256, v259
-    enable_side_effects u1 1
-    v269 = not v267
-    enable_side_effects v269
-    v271 = array_get v9, index u32 18 -> u8
-    v272 = eq v271, u8 232
-    v273 = not v272
-    v274 = mul v269, v273
-    enable_side_effects v274
-    v275 = array_get v9, index u32 18 -> u8
-    v276 = lt v275, u8 232
-    v277 = mul v276, v274
-    constrain v277 == v274
-    v278 = not v274
-    v279 = mul v278, v267
-    v280 = unchecked_add v274, v279
-    v281 = mul v269, v272
-    enable_side_effects u1 1
-    v282 = not v280
-    enable_side_effects v282
-    v284 = array_get v9, index u32 19 -> u8
-    v285 = eq v284, u8 72
-    v286 = not v285
-    v287 = mul v282, v286
-    enable_side_effects v287
-    v288 = array_get v9, index u32 19 -> u8
-    v289 = lt v288, u8 72
-    v290 = mul v289, v287
-    constrain v290 == v287
-    v291 = not v287
-    v292 = mul v291, v280
-    v293 = unchecked_add v287, v292
-    v294 = mul v282, v285
-    enable_side_effects u1 1
-    v295 = not v293
-    enable_side_effects v295
-    v297 = array_get v9, index u32 20 -> u8
-    v298 = eq v297, u8 121
-    v299 = not v298
-    v300 = mul v295, v299
-    enable_side_effects v300
-    v301 = array_get v9, index u32 20 -> u8
-    v302 = lt v301, u8 121
-    v303 = mul v302, v300
-    constrain v303 == v300
-    v304 = not v300
-    v305 = mul v304, v293
-    v306 = unchecked_add v300, v305
-    v307 = mul v295, v298
-    enable_side_effects u1 1
-    v308 = not v306
-    enable_side_effects v308
-    v310 = array_get v9, index u32 21 -> u8
-    v311 = eq v310, u8 185
-    v312 = not v311
-    v313 = mul v308, v312
-    enable_side_effects v313
-    v314 = array_get v9, index u32 21 -> u8
-    v315 = lt v314, u8 185
-    v316 = mul v315, v313
-    constrain v316 == v313
-    v317 = not v313
-    v318 = mul v317, v306
-    v319 = unchecked_add v313, v318
-    v320 = mul v308, v311
-    enable_side_effects u1 1
-    v321 = not v319
-    enable_side_effects v321
-    v323 = array_get v9, index u32 22 -> u8
-    v324 = eq v323, u8 112
-    v325 = not v324
-    v326 = mul v321, v325
-    enable_side_effects v326
-    v327 = array_get v9, index u32 22 -> u8
-    v328 = lt v327, u8 112
-    v329 = mul v328, v326
-    constrain v329 == v326
-    v330 = not v326
-    v331 = mul v330, v319
-    v332 = unchecked_add v326, v331
-    v333 = mul v321, v324
-    enable_side_effects u1 1
-    v334 = not v332
-    enable_side_effects v334
-    v336 = array_get v9, index u32 23 -> u8
-    v337 = eq v336, u8 145
-    v338 = not v337
-    v339 = mul v334, v338
-    enable_side_effects v339
-    v340 = array_get v9, index u32 23 -> u8
-    v341 = lt v340, u8 145
-    v342 = mul v341, v339
-    constrain v342 == v339
-    v343 = not v339
-    v344 = mul v343, v332
-    v345 = unchecked_add v339, v344
-    v346 = mul v334, v337
-    enable_side_effects u1 1
-    v347 = not v345
-    enable_side_effects v347
-    v349 = array_get v9, index u32 24 -> u8
-    v350 = eq v349, u8 67
-    v351 = not v350
-    v352 = mul v347, v351
-    enable_side_effects v352
-    v353 = array_get v9, index u32 24 -> u8
-    v354 = lt v353, u8 67
-    v355 = mul v354, v352
-    constrain v355 == v352
-    v356 = not v352
-    v357 = mul v356, v345
-    v358 = unchecked_add v352, v357
-    v359 = mul v347, v350
-    enable_side_effects u1 1
-    v360 = not v358
-    enable_side_effects v360
-    v362 = array_get v9, index u32 25 -> u8
-    v363 = eq v362, u8 225
-    v364 = not v363
-    v365 = mul v360, v364
-    enable_side_effects v365
-    v366 = array_get v9, index u32 25 -> u8
-    v367 = lt v366, u8 225
-    v368 = mul v367, v365
-    constrain v368 == v365
-    v369 = not v365
-    v370 = mul v369, v358
-    v371 = unchecked_add v365, v370
-    v372 = mul v360, v363
-    enable_side_effects u1 1
-    v373 = not v371
-    enable_side_effects v373
-    v375 = array_get v9, index u32 26 -> u8
-    v376 = eq v375, u8 245
-    v377 = not v376
-    v378 = mul v373, v377
-    enable_side_effects v378
-    v379 = array_get v9, index u32 26 -> u8
-    v380 = lt v379, u8 245
-    v381 = mul v380, v378
-    constrain v381 == v378
-    v382 = not v378
-    v383 = mul v382, v371
-    v384 = unchecked_add v378, v383
-    v385 = mul v373, v376
-    enable_side_effects u1 1
-    v386 = not v384
-    enable_side_effects v386
-    v388 = array_get v9, index u32 27 -> u8
-    v389 = eq v388, u8 147
-    v390 = not v389
-    v391 = mul v386, v390
-    enable_side_effects v391
-    v392 = array_get v9, index u32 27 -> u8
-    v393 = lt v392, u8 147
-    v394 = mul v393, v391
-    constrain v394 == v391
-    v395 = not v391
-    v396 = mul v395, v384
-    v397 = unchecked_add v391, v396
-    v398 = mul v386, v389
-    enable_side_effects u1 1
-    v399 = not v397
-    enable_side_effects v399
-    v401 = array_get v9, index u32 28 -> u8
-    v402 = eq v401, u8 240
-    v403 = not v402
-    v404 = mul v399, v403
-    enable_side_effects v404
-    v405 = array_get v9, index u32 28 -> u8
-    v406 = lt v405, u8 240
-    v407 = mul v406, v404
-    constrain v407 == v404
-    v408 = not v404
-    v409 = mul v408, v397
-    v410 = unchecked_add v404, v409
-    v411 = mul v399, v402
-    enable_side_effects u1 1
-    v412 = not v410
-    enable_side_effects v412
-    v414 = array_get v9, index u32 29 -> u8
-    v415 = eq v414, u8 0
-    v416 = not v415
-    v417 = mul v412, v416
-    enable_side_effects v417
-    v418 = array_get v9, index u32 29 -> u8
-    constrain u1 0 == v417
-    v420 = not v417
-    v421 = mul v420, v410
-    v422 = unchecked_add v417, v421
-    v423 = mul v412, v415
-    enable_side_effects u1 1
-    v424 = not v422
-    enable_side_effects v424
-    v426 = array_get v9, index u32 30 -> u8
-    v427 = eq v426, u8 0
-    v428 = not v427
-    v429 = mul v424, v428
-    enable_side_effects v429
-    v430 = array_get v9, index u32 30 -> u8
-    constrain u1 0 == v429
-    v431 = not v429
-    v432 = mul v431, v422
-    v433 = unchecked_add v429, v432
-    v434 = mul v424, v427
-    enable_side_effects u1 1
-    v435 = not v433
-    enable_side_effects v435
-    v437 = array_get v9, index u32 31 -> u8
-    v438 = eq v437, u8 1
-    v439 = not v438
-    v440 = mul v435, v439
-    enable_side_effects v440
-    v441 = array_get v9, index u32 31 -> u8
-    v442 = eq v441, u8 0
-    v443 = cast v440 as u8
-    v444 = unchecked_mul v441, v443
-    constrain v444 == u8 0
-    v445 = not v440
-    v446 = mul v445, v433
-    v447 = unchecked_add v440, v446
-    v448 = mul v435, v438
-    enable_side_effects u1 1
-    constrain v447 == u1 1
-    v449 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v450 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v451 = allocate -> &mut u1
-    enable_side_effects u1 1
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    enable_side_effects u1 1
-    enable_side_effects u1 1
-    enable_side_effects u1 0
-    enable_side_effects u1 1
-    v452 = allocate -> &mut [u8; 32]
-    v453 = array_get v9, index u32 0 -> u8
-    v454 = make_array [v453, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v455 = array_get v9, index u32 1 -> u8
-    v456 = make_array [v453, v455, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v457 = array_get v9, index u32 2 -> u8
-    v458 = make_array [v453, v455, v457, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v459 = array_get v9, index u32 3 -> u8
-    v460 = make_array [v453, v455, v457, v459, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v461 = array_get v9, index u32 4 -> u8
-    v462 = make_array [v453, v455, v457, v459, v461, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v463 = array_get v9, index u32 5 -> u8
-    v464 = make_array [v453, v455, v457, v459, v461, v463, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v465 = array_get v9, index u32 6 -> u8
-    v466 = make_array [v453, v455, v457, v459, v461, v463, v465, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v467 = array_get v9, index u32 7 -> u8
-    v468 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v469 = array_get v9, index u32 8 -> u8
-    v470 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v471 = array_get v9, index u32 9 -> u8
-    v472 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v473 = array_get v9, index u32 10 -> u8
-    v474 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v475 = array_get v9, index u32 11 -> u8
-    v476 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v477 = array_get v9, index u32 12 -> u8
-    v478 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v479 = array_get v9, index u32 13 -> u8
-    v480 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v481 = array_get v9, index u32 14 -> u8
-    v482 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v483 = array_get v9, index u32 15 -> u8
-    v484 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v485 = array_get v9, index u32 16 -> u8
-    v486 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v487 = array_get v9, index u32 17 -> u8
-    v488 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v489 = array_get v9, index u32 18 -> u8
-    v490 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v491 = array_get v9, index u32 19 -> u8
-    v492 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v493 = array_get v9, index u32 20 -> u8
-    v494 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v495 = array_get v9, index u32 21 -> u8
-    v496 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v497 = array_get v9, index u32 22 -> u8
-    v498 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v499 = array_get v9, index u32 23 -> u8
-    v500 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v501 = array_get v9, index u32 24 -> u8
-    v502 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v503 = array_get v9, index u32 25 -> u8
-    v504 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v505 = array_get v9, index u32 26 -> u8
-    v506 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v507 = array_get v9, index u32 27 -> u8
-    v508 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v509 = array_get v9, index u32 28 -> u8
-    v510 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, u8 0, u8 0, u8 0] : [u8; 32]
-    v511 = array_get v9, index u32 29 -> u8
-    v512 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, u8 0, u8 0] : [u8; 32]
-    v513 = array_get v9, index u32 30 -> u8
-    v514 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, v513, u8 0] : [u8; 32]
-    v515 = array_get v9, index u32 31 -> u8
-    v516 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, v513, v515] : [u8; 32]
-    v517 = allocate -> &mut Field
-    v518 = allocate -> &mut Field
-    v519 = allocate -> &mut Field
-    v520 = cast v483 as Field
-    v521 = cast v515 as Field
-    v522 = cast v481 as Field
-    v524 = mul v522, Field 256
-    v525 = add v520, v524
-    v526 = cast v513 as Field
-    v527 = mul v526, Field 256
-    v528 = add v521, v527
-    v529 = cast v479 as Field
-    v531 = mul v529, Field 65536
-    v532 = add v525, v531
-    v533 = cast v511 as Field
-    v534 = mul v533, Field 65536
-    v535 = add v528, v534
-    v536 = cast v477 as Field
-    v538 = mul v536, Field 16777216
-    v539 = add v532, v538
-    v540 = cast v509 as Field
-    v541 = mul v540, Field 16777216
-    v542 = add v535, v541
-    v543 = cast v475 as Field
-    v545 = mul v543, Field 4294967296
-    v546 = add v539, v545
-    v547 = cast v507 as Field
-    v548 = mul v547, Field 4294967296
-    v549 = add v542, v548
-    v550 = cast v473 as Field
-    v552 = mul v550, Field 1099511627776
-    v553 = add v546, v552
-    v554 = cast v505 as Field
-    v555 = mul v554, Field 1099511627776
-    v556 = add v549, v555
-    v557 = cast v471 as Field
-    v559 = mul v557, Field 281474976710656
-    v560 = add v553, v559
-    v561 = cast v503 as Field
-    v562 = mul v561, Field 281474976710656
-    v563 = add v556, v562
-    v564 = cast v469 as Field
-    v566 = mul v564, Field 72057594037927936
-    v567 = add v560, v566
-    v568 = cast v501 as Field
-    v569 = mul v568, Field 72057594037927936
-    v570 = add v563, v569
-    v571 = cast v467 as Field
-    v573 = mul v571, Field 18446744073709551616
-    v574 = add v567, v573
-    v575 = cast v499 as Field
-    v576 = mul v575, Field 18446744073709551616
-    v577 = add v570, v576
-    v578 = cast v465 as Field
-    v580 = mul v578, Field 4722366482869645213696
-    v581 = add v574, v580
-    v582 = cast v497 as Field
-    v583 = mul v582, Field 4722366482869645213696
-    v584 = add v577, v583
-    v585 = cast v463 as Field
-    v587 = mul v585, Field 1208925819614629174706176
-    v588 = add v581, v587
-    v589 = cast v495 as Field
-    v590 = mul v589, Field 1208925819614629174706176
-    v591 = add v584, v590
-    v592 = cast v461 as Field
-    v594 = mul v592, Field 309485009821345068724781056
-    v595 = add v588, v594
-    v596 = cast v493 as Field
-    v597 = mul v596, Field 309485009821345068724781056
-    v598 = add v591, v597
-    v599 = cast v459 as Field
-    v601 = mul v599, Field 79228162514264337593543950336
-    v602 = add v595, v601
-    v603 = cast v491 as Field
-    v604 = mul v603, Field 79228162514264337593543950336
-    v605 = add v598, v604
-    v606 = cast v457 as Field
-    v608 = mul v606, Field 20282409603651670423947251286016
-    v609 = add v602, v608
-    v610 = cast v489 as Field
-    v611 = mul v610, Field 20282409603651670423947251286016
-    v612 = add v605, v611
-    v613 = cast v455 as Field
-    v615 = mul v613, Field 5192296858534827628530496329220096
-    v616 = add v609, v615
-    v617 = cast v487 as Field
-    v618 = mul v617, Field 5192296858534827628530496329220096
-    v619 = add v612, v618
-    v620 = cast v453 as Field
-    v622 = mul v620, Field 1329227995784915872903807060280344576
-    v623 = add v616, v622
-    v624 = cast v485 as Field
-    v625 = mul v624, Field 1329227995784915872903807060280344576
-    v626 = add v619, v625
-    v628 = mul v623, Field 340282366920938463463374607431768211456
-    v629 = add v626, v628
-    v630 = allocate -> &mut Field
-    v632 = eq v4, Field 0
-    enable_side_effects v632
-    v633 = not v632
-    enable_side_effects v633
-    v635 = call f1(v4, Field 0) -> u1
-    v636 = mul v633, v635
-    enable_side_effects v636
-    v638, v639 = call f3(Field 0) -> (Field, Field)
-    v640 = cast v636 as Field
-    v641 = mul v638, v640
-    range_check v641 to 128 bits
-    v642 = cast v636 as Field
-    v643 = mul v639, v642
-    range_check v643 to 128 bits
-    v644 = mul Field 340282366920938463463374607431768211456, v639
-    v645 = add v638, v644
-    v646 = eq Field 0, v645
-    v647 = cast v636 as Field
-    v648 = mul v645, v647
-    constrain Field 0 == v648
-    v651 = call f2(Field 53438638232309528389504892708671455233, v638) -> u1
-    v652 = sub Field 53438638232309528389504892708671455233, v638
-    v654 = sub v652, Field 1
-    v655 = cast v651 as Field
-    v656 = mul v655, Field 340282366920938463463374607431768211456
-    v657 = add v654, v656
-    v659 = sub Field 64323764613183177041862057485226039389, v639
-    v660 = cast v651 as Field
-    v661 = sub v659, v660
-    v662 = cast v636 as Field
-    v663 = mul v657, v662
-    range_check v663 to 128 bits
-    v664 = cast v636 as Field
-    v665 = mul v661, v664
-    range_check v665 to 128 bits
-    v667, v668 = call f3(v4) -> (Field, Field)
-    v669 = cast v636 as Field
-    v670 = mul v667, v669
-    range_check v670 to 128 bits
-    v671 = cast v636 as Field
-    v672 = mul v668, v671
-    range_check v672 to 128 bits
-    v673 = mul Field 340282366920938463463374607431768211456, v668
-    v674 = add v667, v673
-    v675 = eq v4, v674
-    v676 = cast v636 as Field
-    v677 = mul v4, v676
-    v678 = mul v674, v676
-    constrain v677 == v678
-    v680 = call f2(Field 53438638232309528389504892708671455233, v667) -> u1
-    v681 = sub Field 53438638232309528389504892708671455233, v667
-    v682 = sub v681, Field 1
-    v683 = cast v680 as Field
-    v684 = mul v683, Field 340282366920938463463374607431768211456
-    v685 = add v682, v684
-    v686 = sub Field 64323764613183177041862057485226039389, v668
-    v687 = cast v680 as Field
-    v688 = sub v686, v687
-    v689 = cast v636 as Field
-    v690 = mul v685, v689
-    range_check v690 to 128 bits
-    v691 = cast v636 as Field
-    v692 = mul v688, v691
-    range_check v692 to 128 bits
-    v694 = call f2(v638, v667) -> u1
-    v695 = sub v638, v667
-    v696 = sub v695, Field 1
-    v697 = cast v694 as Field
-    v698 = mul v697, Field 340282366920938463463374607431768211456
-    v699 = add v696, v698
-    v700 = sub v639, v668
-    v701 = cast v694 as Field
-    v702 = sub v700, v701
-    v703 = cast v636 as Field
-    v704 = mul v699, v703
-    range_check v704 to 128 bits
-    v705 = cast v636 as Field
-    v706 = mul v702, v705
-    range_check v706 to 128 bits
-    v707 = not v635
-    v708 = mul v633, v707
-    enable_side_effects v708
-    v710, v711 = call f3(v4) -> (Field, Field)
-    v712 = cast v708 as Field
-    v713 = mul v710, v712
-    range_check v713 to 128 bits
-    v714 = cast v708 as Field
-    v715 = mul v711, v714
-    range_check v715 to 128 bits
-    v716 = mul Field 340282366920938463463374607431768211456, v711
-    v717 = add v710, v716
-    v718 = eq v4, v717
-    v719 = cast v708 as Field
-    v720 = mul v4, v719
-    v721 = mul v717, v719
-    constrain v720 == v721
-    v723 = call f2(Field 53438638232309528389504892708671455233, v710) -> u1
-    v724 = sub Field 53438638232309528389504892708671455233, v710
-    v725 = sub v724, Field 1
-    v726 = cast v723 as Field
-    v727 = mul v726, Field 340282366920938463463374607431768211456
-    v728 = add v725, v727
-    v729 = sub Field 64323764613183177041862057485226039389, v711
-    v730 = cast v723 as Field
-    v731 = sub v729, v730
-    v732 = cast v708 as Field
-    v733 = mul v728, v732
-    range_check v733 to 128 bits
-    v734 = cast v708 as Field
-    v735 = mul v731, v734
-    range_check v735 to 128 bits
-    v737, v738 = call f3(Field 0) -> (Field, Field)
-    v739 = cast v708 as Field
-    v740 = mul v737, v739
-    range_check v740 to 128 bits
-    v741 = cast v708 as Field
-    v742 = mul v738, v741
-    range_check v742 to 128 bits
-    v743 = mul Field 340282366920938463463374607431768211456, v738
-    v744 = add v737, v743
-    v745 = eq Field 0, v744
-    v746 = cast v708 as Field
-    v747 = mul v744, v746
-    constrain Field 0 == v747
-    v749 = call f2(Field 53438638232309528389504892708671455233, v737) -> u1
-    v750 = sub Field 53438638232309528389504892708671455233, v737
-    v751 = sub v750, Field 1
-    v752 = cast v749 as Field
-    v753 = mul v752, Field 340282366920938463463374607431768211456
-    v754 = add v751, v753
-    v755 = sub Field 64323764613183177041862057485226039389, v738
-    v756 = cast v749 as Field
-    v757 = sub v755, v756
-    v758 = cast v708 as Field
-    v759 = mul v754, v758
-    range_check v759 to 128 bits
-    v760 = cast v708 as Field
-    v761 = mul v757, v760
-    range_check v761 to 128 bits
-    v763 = call f2(v710, v737) -> u1
-    v764 = sub v710, v737
-    v765 = sub v764, Field 1
-    v766 = cast v763 as Field
-    v767 = mul v766, Field 340282366920938463463374607431768211456
-    v768 = add v765, v767
-    v769 = sub v711, v738
-    v770 = cast v763 as Field
-    v771 = sub v769, v770
-    v772 = cast v708 as Field
-    v773 = mul v768, v772
-    range_check v773 to 128 bits
-    v774 = cast v708 as Field
-    v775 = mul v771, v774
-    range_check v775 to 128 bits
-    enable_side_effects v708
-    v776 = not v708
-    v777 = cast v708 as Field
-    v778 = cast v776 as Field
-    enable_side_effects u1 1
-    v779 = sub v777, v629
-    return v779
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Inlining (2nd):
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = allocate -> &mut Field
-    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v40 = allocate -> &mut u1
-    enable_side_effects u1 1
-    v43 = array_get v9, index u32 0 -> u8
-    v44 = eq v43, u8 48
-    v45 = not v44
-    enable_side_effects v45
-    v46 = array_get v9, index u32 0 -> u8
-    v47 = lt v46, u8 48
-    v48 = mul v47, v45
-    constrain v48 == v45
-    enable_side_effects v44
-    v50 = array_get v9, index u32 1 -> u8
-    v51 = eq v50, u8 100
-    v52 = not v51
-    v53 = mul v44, v52
-    enable_side_effects v53
-    v54 = array_get v9, index u32 1 -> u8
-    v55 = lt v54, u8 100
-    v56 = mul v55, v53
-    constrain v56 == v53
-    v57 = not v53
-    v58 = mul v57, v45
-    v59 = unchecked_add v53, v58
-    v60 = mul v44, v51
-    enable_side_effects u1 1
-    v61 = not v59
-    enable_side_effects v61
-    v63 = array_get v9, index u32 2 -> u8
-    v64 = eq v63, u8 78
-    v65 = not v64
-    v66 = mul v61, v65
-    enable_side_effects v66
-    v67 = array_get v9, index u32 2 -> u8
-    v68 = lt v67, u8 78
-    v69 = mul v68, v66
-    constrain v69 == v66
-    v70 = not v66
-    v71 = mul v70, v59
-    v72 = unchecked_add v66, v71
-    v73 = mul v61, v64
-    enable_side_effects u1 1
-    v74 = not v72
-    enable_side_effects v74
-    v76 = array_get v9, index u32 3 -> u8
-    v77 = eq v76, u8 114
-    v78 = not v77
-    v79 = mul v74, v78
-    enable_side_effects v79
-    v80 = array_get v9, index u32 3 -> u8
-    v81 = lt v80, u8 114
-    v82 = mul v81, v79
-    constrain v82 == v79
-    v83 = not v79
-    v84 = mul v83, v72
-    v85 = unchecked_add v79, v84
-    v86 = mul v74, v77
-    enable_side_effects u1 1
-    v87 = not v85
-    enable_side_effects v87
-    v89 = array_get v9, index u32 4 -> u8
-    v90 = eq v89, u8 225
-    v91 = not v90
-    v92 = mul v87, v91
-    enable_side_effects v92
-    v93 = array_get v9, index u32 4 -> u8
-    v94 = lt v93, u8 225
-    v95 = mul v94, v92
-    constrain v95 == v92
-    v96 = not v92
-    v97 = mul v96, v85
-    v98 = unchecked_add v92, v97
-    v99 = mul v87, v90
-    enable_side_effects u1 1
-    v100 = not v98
-    enable_side_effects v100
-    v102 = array_get v9, index u32 5 -> u8
-    v103 = eq v102, u8 49
-    v104 = not v103
-    v105 = mul v100, v104
-    enable_side_effects v105
-    v106 = array_get v9, index u32 5 -> u8
-    v107 = lt v106, u8 49
-    v108 = mul v107, v105
-    constrain v108 == v105
-    v109 = not v105
-    v110 = mul v109, v98
-    v111 = unchecked_add v105, v110
-    v112 = mul v100, v103
-    enable_side_effects u1 1
-    v113 = not v111
-    enable_side_effects v113
-    v115 = array_get v9, index u32 6 -> u8
-    v116 = eq v115, u8 160
-    v117 = not v116
-    v118 = mul v113, v117
-    enable_side_effects v118
-    v119 = array_get v9, index u32 6 -> u8
-    v120 = lt v119, u8 160
-    v121 = mul v120, v118
-    constrain v121 == v118
-    v122 = not v118
-    v123 = mul v122, v111
-    v124 = unchecked_add v118, v123
-    v125 = mul v113, v116
-    enable_side_effects u1 1
-    v126 = not v124
-    enable_side_effects v126
-    v128 = array_get v9, index u32 7 -> u8
-    v129 = eq v128, u8 41
-    v130 = not v129
-    v131 = mul v126, v130
-    enable_side_effects v131
-    v132 = array_get v9, index u32 7 -> u8
-    v133 = lt v132, u8 41
-    v134 = mul v133, v131
-    constrain v134 == v131
-    v135 = not v131
-    v136 = mul v135, v124
-    v137 = unchecked_add v131, v136
-    v138 = mul v126, v129
-    enable_side_effects u1 1
-    v139 = not v137
-    enable_side_effects v139
-    v141 = array_get v9, index u32 8 -> u8
-    v142 = eq v141, u8 184
-    v143 = not v142
-    v144 = mul v139, v143
-    enable_side_effects v144
-    v145 = array_get v9, index u32 8 -> u8
-    v146 = lt v145, u8 184
-    v147 = mul v146, v144
-    constrain v147 == v144
-    v148 = not v144
-    v149 = mul v148, v137
-    v150 = unchecked_add v144, v149
-    v151 = mul v139, v142
-    enable_side_effects u1 1
-    v152 = not v150
-    enable_side_effects v152
-    v154 = array_get v9, index u32 9 -> u8
-    v155 = eq v154, u8 80
-    v156 = not v155
-    v157 = mul v152, v156
-    enable_side_effects v157
-    v158 = array_get v9, index u32 9 -> u8
-    v159 = lt v158, u8 80
-    v160 = mul v159, v157
-    constrain v160 == v157
-    v161 = not v157
-    v162 = mul v161, v150
-    v163 = unchecked_add v157, v162
-    v164 = mul v152, v155
-    enable_side_effects u1 1
-    v165 = not v163
-    enable_side_effects v165
-    v167 = array_get v9, index u32 10 -> u8
-    v168 = eq v167, u8 69
-    v169 = not v168
-    v170 = mul v165, v169
-    enable_side_effects v170
-    v171 = array_get v9, index u32 10 -> u8
-    v172 = lt v171, u8 69
-    v173 = mul v172, v170
-    constrain v173 == v170
-    v174 = not v170
-    v175 = mul v174, v163
-    v176 = unchecked_add v170, v175
-    v177 = mul v165, v168
-    enable_side_effects u1 1
-    v178 = not v176
-    enable_side_effects v178
-    v180 = array_get v9, index u32 11 -> u8
-    v181 = eq v180, u8 182
-    v182 = not v181
-    v183 = mul v178, v182
-    enable_side_effects v183
-    v184 = array_get v9, index u32 11 -> u8
-    v185 = lt v184, u8 182
-    v186 = mul v185, v183
-    constrain v186 == v183
-    v187 = not v183
-    v188 = mul v187, v176
-    v189 = unchecked_add v183, v188
-    v190 = mul v178, v181
-    enable_side_effects u1 1
-    v191 = not v189
-    enable_side_effects v191
-    v193 = array_get v9, index u32 12 -> u8
-    v194 = eq v193, u8 129
-    v195 = not v194
-    v196 = mul v191, v195
-    enable_side_effects v196
-    v197 = array_get v9, index u32 12 -> u8
-    v198 = lt v197, u8 129
-    v199 = mul v198, v196
-    constrain v199 == v196
-    v200 = not v196
-    v201 = mul v200, v189
-    v202 = unchecked_add v196, v201
-    v203 = mul v191, v194
-    enable_side_effects u1 1
-    v204 = not v202
-    enable_side_effects v204
-    v206 = array_get v9, index u32 13 -> u8
-    v207 = eq v206, u8 129
-    v208 = not v207
-    v209 = mul v204, v208
-    enable_side_effects v209
-    v210 = array_get v9, index u32 13 -> u8
-    v211 = lt v210, u8 129
-    v212 = mul v211, v209
-    constrain v212 == v209
-    v213 = not v209
-    v214 = mul v213, v202
-    v215 = unchecked_add v209, v214
-    v216 = mul v204, v207
-    enable_side_effects u1 1
-    v217 = not v215
-    enable_side_effects v217
-    v219 = array_get v9, index u32 14 -> u8
-    v220 = eq v219, u8 88
-    v221 = not v220
-    v222 = mul v217, v221
-    enable_side_effects v222
-    v223 = array_get v9, index u32 14 -> u8
-    v224 = lt v223, u8 88
-    v225 = mul v224, v222
-    constrain v225 == v222
-    v226 = not v222
-    v227 = mul v226, v215
-    v228 = unchecked_add v222, v227
-    v229 = mul v217, v220
-    enable_side_effects u1 1
-    v230 = not v228
-    enable_side_effects v230
-    v232 = array_get v9, index u32 15 -> u8
-    v233 = eq v232, u8 93
-    v234 = not v233
-    v235 = mul v230, v234
-    enable_side_effects v235
-    v236 = array_get v9, index u32 15 -> u8
-    v237 = lt v236, u8 93
-    v238 = mul v237, v235
-    constrain v238 == v235
-    v239 = not v235
-    v240 = mul v239, v228
-    v241 = unchecked_add v235, v240
-    v242 = mul v230, v233
-    enable_side_effects u1 1
-    v243 = not v241
-    enable_side_effects v243
-    v245 = array_get v9, index u32 16 -> u8
-    v246 = eq v245, u8 40
-    v247 = not v246
-    v248 = mul v243, v247
-    enable_side_effects v248
-    v249 = array_get v9, index u32 16 -> u8
-    v250 = lt v249, u8 40
-    v251 = mul v250, v248
-    constrain v251 == v248
-    v252 = not v248
-    v253 = mul v252, v241
-    v254 = unchecked_add v248, v253
-    v255 = mul v243, v246
-    enable_side_effects u1 1
-    v256 = not v254
-    enable_side_effects v256
-    v258 = array_get v9, index u32 17 -> u8
-    v259 = eq v258, u8 51
-    v260 = not v259
-    v261 = mul v256, v260
-    enable_side_effects v261
-    v262 = array_get v9, index u32 17 -> u8
-    v263 = lt v262, u8 51
-    v264 = mul v263, v261
-    constrain v264 == v261
-    v265 = not v261
-    v266 = mul v265, v254
-    v267 = unchecked_add v261, v266
-    v268 = mul v256, v259
-    enable_side_effects u1 1
-    v269 = not v267
-    enable_side_effects v269
-    v271 = array_get v9, index u32 18 -> u8
-    v272 = eq v271, u8 232
-    v273 = not v272
-    v274 = mul v269, v273
-    enable_side_effects v274
-    v275 = array_get v9, index u32 18 -> u8
-    v276 = lt v275, u8 232
-    v277 = mul v276, v274
-    constrain v277 == v274
-    v278 = not v274
-    v279 = mul v278, v267
-    v280 = unchecked_add v274, v279
-    v281 = mul v269, v272
-    enable_side_effects u1 1
-    v282 = not v280
-    enable_side_effects v282
-    v284 = array_get v9, index u32 19 -> u8
-    v285 = eq v284, u8 72
-    v286 = not v285
-    v287 = mul v282, v286
-    enable_side_effects v287
-    v288 = array_get v9, index u32 19 -> u8
-    v289 = lt v288, u8 72
-    v290 = mul v289, v287
-    constrain v290 == v287
-    v291 = not v287
-    v292 = mul v291, v280
-    v293 = unchecked_add v287, v292
-    v294 = mul v282, v285
-    enable_side_effects u1 1
-    v295 = not v293
-    enable_side_effects v295
-    v297 = array_get v9, index u32 20 -> u8
-    v298 = eq v297, u8 121
-    v299 = not v298
-    v300 = mul v295, v299
-    enable_side_effects v300
-    v301 = array_get v9, index u32 20 -> u8
-    v302 = lt v301, u8 121
-    v303 = mul v302, v300
-    constrain v303 == v300
-    v304 = not v300
-    v305 = mul v304, v293
-    v306 = unchecked_add v300, v305
-    v307 = mul v295, v298
-    enable_side_effects u1 1
-    v308 = not v306
-    enable_side_effects v308
-    v310 = array_get v9, index u32 21 -> u8
-    v311 = eq v310, u8 185
-    v312 = not v311
-    v313 = mul v308, v312
-    enable_side_effects v313
-    v314 = array_get v9, index u32 21 -> u8
-    v315 = lt v314, u8 185
-    v316 = mul v315, v313
-    constrain v316 == v313
-    v317 = not v313
-    v318 = mul v317, v306
-    v319 = unchecked_add v313, v318
-    v320 = mul v308, v311
-    enable_side_effects u1 1
-    v321 = not v319
-    enable_side_effects v321
-    v323 = array_get v9, index u32 22 -> u8
-    v324 = eq v323, u8 112
-    v325 = not v324
-    v326 = mul v321, v325
-    enable_side_effects v326
-    v327 = array_get v9, index u32 22 -> u8
-    v328 = lt v327, u8 112
-    v329 = mul v328, v326
-    constrain v329 == v326
-    v330 = not v326
-    v331 = mul v330, v319
-    v332 = unchecked_add v326, v331
-    v333 = mul v321, v324
-    enable_side_effects u1 1
-    v334 = not v332
-    enable_side_effects v334
-    v336 = array_get v9, index u32 23 -> u8
-    v337 = eq v336, u8 145
-    v338 = not v337
-    v339 = mul v334, v338
-    enable_side_effects v339
-    v340 = array_get v9, index u32 23 -> u8
-    v341 = lt v340, u8 145
-    v342 = mul v341, v339
-    constrain v342 == v339
-    v343 = not v339
-    v344 = mul v343, v332
-    v345 = unchecked_add v339, v344
-    v346 = mul v334, v337
-    enable_side_effects u1 1
-    v347 = not v345
-    enable_side_effects v347
-    v349 = array_get v9, index u32 24 -> u8
-    v350 = eq v349, u8 67
-    v351 = not v350
-    v352 = mul v347, v351
-    enable_side_effects v352
-    v353 = array_get v9, index u32 24 -> u8
-    v354 = lt v353, u8 67
-    v355 = mul v354, v352
-    constrain v355 == v352
-    v356 = not v352
-    v357 = mul v356, v345
-    v358 = unchecked_add v352, v357
-    v359 = mul v347, v350
-    enable_side_effects u1 1
-    v360 = not v358
-    enable_side_effects v360
-    v362 = array_get v9, index u32 25 -> u8
-    v363 = eq v362, u8 225
-    v364 = not v363
-    v365 = mul v360, v364
-    enable_side_effects v365
-    v366 = array_get v9, index u32 25 -> u8
-    v367 = lt v366, u8 225
-    v368 = mul v367, v365
-    constrain v368 == v365
-    v369 = not v365
-    v370 = mul v369, v358
-    v371 = unchecked_add v365, v370
-    v372 = mul v360, v363
-    enable_side_effects u1 1
-    v373 = not v371
-    enable_side_effects v373
-    v375 = array_get v9, index u32 26 -> u8
-    v376 = eq v375, u8 245
-    v377 = not v376
-    v378 = mul v373, v377
-    enable_side_effects v378
-    v379 = array_get v9, index u32 26 -> u8
-    v380 = lt v379, u8 245
-    v381 = mul v380, v378
-    constrain v381 == v378
-    v382 = not v378
-    v383 = mul v382, v371
-    v384 = unchecked_add v378, v383
-    v385 = mul v373, v376
-    enable_side_effects u1 1
-    v386 = not v384
-    enable_side_effects v386
-    v388 = array_get v9, index u32 27 -> u8
-    v389 = eq v388, u8 147
-    v390 = not v389
-    v391 = mul v386, v390
-    enable_side_effects v391
-    v392 = array_get v9, index u32 27 -> u8
-    v393 = lt v392, u8 147
-    v394 = mul v393, v391
-    constrain v394 == v391
-    v395 = not v391
-    v396 = mul v395, v384
-    v397 = unchecked_add v391, v396
-    v398 = mul v386, v389
-    enable_side_effects u1 1
-    v399 = not v397
-    enable_side_effects v399
-    v401 = array_get v9, index u32 28 -> u8
-    v402 = eq v401, u8 240
-    v403 = not v402
-    v404 = mul v399, v403
-    enable_side_effects v404
-    v405 = array_get v9, index u32 28 -> u8
-    v406 = lt v405, u8 240
-    v407 = mul v406, v404
-    constrain v407 == v404
-    v408 = not v404
-    v409 = mul v408, v397
-    v410 = unchecked_add v404, v409
-    v411 = mul v399, v402
-    enable_side_effects u1 1
-    v412 = not v410
-    enable_side_effects v412
-    v414 = array_get v9, index u32 29 -> u8
-    v415 = eq v414, u8 0
-    v416 = not v415
-    v417 = mul v412, v416
-    enable_side_effects v417
-    v418 = array_get v9, index u32 29 -> u8
-    constrain u1 0 == v417
-    v420 = not v417
-    v421 = mul v420, v410
-    v422 = unchecked_add v417, v421
-    v423 = mul v412, v415
-    enable_side_effects u1 1
-    v424 = not v422
-    enable_side_effects v424
-    v426 = array_get v9, index u32 30 -> u8
-    v427 = eq v426, u8 0
-    v428 = not v427
-    v429 = mul v424, v428
-    enable_side_effects v429
-    v430 = array_get v9, index u32 30 -> u8
-    constrain u1 0 == v429
-    v431 = not v429
-    v432 = mul v431, v422
-    v433 = unchecked_add v429, v432
-    v434 = mul v424, v427
-    enable_side_effects u1 1
-    v435 = not v433
-    enable_side_effects v435
-    v437 = array_get v9, index u32 31 -> u8
-    v438 = eq v437, u8 1
-    v439 = not v438
-    v440 = mul v435, v439
-    enable_side_effects v440
-    v441 = array_get v9, index u32 31 -> u8
-    v442 = eq v441, u8 0
-    v443 = cast v440 as u8
-    v444 = unchecked_mul v441, v443
-    constrain v444 == u8 0
-    v445 = not v440
-    v446 = mul v445, v433
-    v447 = unchecked_add v440, v446
-    v448 = mul v435, v438
-    enable_side_effects u1 1
-    constrain v447 == u1 1
-    v449 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v450 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v451 = allocate -> &mut u1
-    enable_side_effects u1 1
-    v452 = allocate -> &mut [u8; 32]
-    v453 = array_get v9, index u32 0 -> u8
-    v454 = make_array [v453, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v455 = array_get v9, index u32 1 -> u8
-    v456 = make_array [v453, v455, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v457 = array_get v9, index u32 2 -> u8
-    v458 = make_array [v453, v455, v457, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v459 = array_get v9, index u32 3 -> u8
-    v460 = make_array [v453, v455, v457, v459, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v461 = array_get v9, index u32 4 -> u8
-    v462 = make_array [v453, v455, v457, v459, v461, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v463 = array_get v9, index u32 5 -> u8
-    v464 = make_array [v453, v455, v457, v459, v461, v463, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v465 = array_get v9, index u32 6 -> u8
-    v466 = make_array [v453, v455, v457, v459, v461, v463, v465, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v467 = array_get v9, index u32 7 -> u8
-    v468 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v469 = array_get v9, index u32 8 -> u8
-    v470 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v471 = array_get v9, index u32 9 -> u8
-    v472 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v473 = array_get v9, index u32 10 -> u8
-    v474 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v475 = array_get v9, index u32 11 -> u8
-    v476 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v477 = array_get v9, index u32 12 -> u8
-    v478 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v479 = array_get v9, index u32 13 -> u8
-    v480 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v481 = array_get v9, index u32 14 -> u8
-    v482 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v483 = array_get v9, index u32 15 -> u8
-    v484 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v485 = array_get v9, index u32 16 -> u8
-    v486 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v487 = array_get v9, index u32 17 -> u8
-    v488 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v489 = array_get v9, index u32 18 -> u8
-    v490 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v491 = array_get v9, index u32 19 -> u8
-    v492 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v493 = array_get v9, index u32 20 -> u8
-    v494 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v495 = array_get v9, index u32 21 -> u8
-    v496 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v497 = array_get v9, index u32 22 -> u8
-    v498 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v499 = array_get v9, index u32 23 -> u8
-    v500 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v501 = array_get v9, index u32 24 -> u8
-    v502 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v503 = array_get v9, index u32 25 -> u8
-    v504 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v505 = array_get v9, index u32 26 -> u8
-    v506 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v507 = array_get v9, index u32 27 -> u8
-    v508 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v509 = array_get v9, index u32 28 -> u8
-    v510 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, u8 0, u8 0, u8 0] : [u8; 32]
-    v511 = array_get v9, index u32 29 -> u8
-    v512 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, u8 0, u8 0] : [u8; 32]
-    v513 = array_get v9, index u32 30 -> u8
-    v514 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, v513, u8 0] : [u8; 32]
-    v515 = array_get v9, index u32 31 -> u8
-    v516 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, v513, v515] : [u8; 32]
-    v517 = allocate -> &mut Field
-    v518 = allocate -> &mut Field
-    v519 = allocate -> &mut Field
-    v520 = cast v483 as Field
-    v521 = cast v515 as Field
-    v522 = cast v481 as Field
-    v524 = mul v522, Field 256
-    v525 = add v520, v524
-    v526 = cast v513 as Field
-    v527 = mul v526, Field 256
-    v528 = add v521, v527
-    v529 = cast v479 as Field
-    v531 = mul v529, Field 65536
-    v532 = add v525, v531
-    v533 = cast v511 as Field
-    v534 = mul v533, Field 65536
-    v535 = add v528, v534
-    v536 = cast v477 as Field
-    v538 = mul v536, Field 16777216
-    v539 = add v532, v538
-    v540 = cast v509 as Field
-    v541 = mul v540, Field 16777216
-    v542 = add v535, v541
-    v543 = cast v475 as Field
-    v545 = mul v543, Field 4294967296
-    v546 = add v539, v545
-    v547 = cast v507 as Field
-    v548 = mul v547, Field 4294967296
-    v549 = add v542, v548
-    v550 = cast v473 as Field
-    v552 = mul v550, Field 1099511627776
-    v553 = add v546, v552
-    v554 = cast v505 as Field
-    v555 = mul v554, Field 1099511627776
-    v556 = add v549, v555
-    v557 = cast v471 as Field
-    v559 = mul v557, Field 281474976710656
-    v560 = add v553, v559
-    v561 = cast v503 as Field
-    v562 = mul v561, Field 281474976710656
-    v563 = add v556, v562
-    v564 = cast v469 as Field
-    v566 = mul v564, Field 72057594037927936
-    v567 = add v560, v566
-    v568 = cast v501 as Field
-    v569 = mul v568, Field 72057594037927936
-    v570 = add v563, v569
-    v571 = cast v467 as Field
-    v573 = mul v571, Field 18446744073709551616
-    v574 = add v567, v573
-    v575 = cast v499 as Field
-    v576 = mul v575, Field 18446744073709551616
-    v577 = add v570, v576
-    v578 = cast v465 as Field
-    v580 = mul v578, Field 4722366482869645213696
-    v581 = add v574, v580
-    v582 = cast v497 as Field
-    v583 = mul v582, Field 4722366482869645213696
-    v584 = add v577, v583
-    v585 = cast v463 as Field
-    v587 = mul v585, Field 1208925819614629174706176
-    v588 = add v581, v587
-    v589 = cast v495 as Field
-    v590 = mul v589, Field 1208925819614629174706176
-    v591 = add v584, v590
-    v592 = cast v461 as Field
-    v594 = mul v592, Field 309485009821345068724781056
-    v595 = add v588, v594
-    v596 = cast v493 as Field
-    v597 = mul v596, Field 309485009821345068724781056
-    v598 = add v591, v597
-    v599 = cast v459 as Field
-    v601 = mul v599, Field 79228162514264337593543950336
-    v602 = add v595, v601
-    v603 = cast v491 as Field
-    v604 = mul v603, Field 79228162514264337593543950336
-    v605 = add v598, v604
-    v606 = cast v457 as Field
-    v608 = mul v606, Field 20282409603651670423947251286016
-    v609 = add v602, v608
-    v610 = cast v489 as Field
-    v611 = mul v610, Field 20282409603651670423947251286016
-    v612 = add v605, v611
-    v613 = cast v455 as Field
-    v615 = mul v613, Field 5192296858534827628530496329220096
-    v616 = add v609, v615
-    v617 = cast v487 as Field
-    v618 = mul v617, Field 5192296858534827628530496329220096
-    v619 = add v612, v618
-    v620 = cast v453 as Field
-    v622 = mul v620, Field 1329227995784915872903807060280344576
-    v623 = add v616, v622
-    v624 = cast v485 as Field
-    v625 = mul v624, Field 1329227995784915872903807060280344576
-    v626 = add v619, v625
-    v628 = mul v623, Field 340282366920938463463374607431768211456
-    v629 = add v626, v628
-    v630 = allocate -> &mut Field
-    v632 = eq v4, Field 0
-    enable_side_effects v632
-    v633 = not v632
-    enable_side_effects v633
-    v635 = call f1(v4, Field 0) -> u1
-    v636 = mul v633, v635
-    enable_side_effects v636
-    v638, v639 = call f3(Field 0) -> (Field, Field)
-    v640 = cast v636 as Field
-    v641 = mul v638, v640
-    range_check v641 to 128 bits
-    v642 = cast v636 as Field
-    v643 = mul v639, v642
-    range_check v643 to 128 bits
-    v644 = mul Field 340282366920938463463374607431768211456, v639
-    v645 = add v638, v644
-    v646 = eq Field 0, v645
-    v647 = cast v636 as Field
-    v648 = mul v645, v647
-    constrain Field 0 == v648
-    v651 = call f2(Field 53438638232309528389504892708671455233, v638) -> u1
-    v652 = sub Field 53438638232309528389504892708671455233, v638
-    v654 = sub v652, Field 1
-    v655 = cast v651 as Field
-    v656 = mul v655, Field 340282366920938463463374607431768211456
-    v657 = add v654, v656
-    v659 = sub Field 64323764613183177041862057485226039389, v639
-    v660 = cast v651 as Field
-    v661 = sub v659, v660
-    v662 = cast v636 as Field
-    v663 = mul v657, v662
-    range_check v663 to 128 bits
-    v664 = cast v636 as Field
-    v665 = mul v661, v664
-    range_check v665 to 128 bits
-    v667, v668 = call f3(v4) -> (Field, Field)
-    v669 = cast v636 as Field
-    v670 = mul v667, v669
-    range_check v670 to 128 bits
-    v671 = cast v636 as Field
-    v672 = mul v668, v671
-    range_check v672 to 128 bits
-    v673 = mul Field 340282366920938463463374607431768211456, v668
-    v674 = add v667, v673
-    v675 = eq v4, v674
-    v676 = cast v636 as Field
-    v677 = mul v4, v676
-    v678 = mul v674, v676
-    constrain v677 == v678
-    v680 = call f2(Field 53438638232309528389504892708671455233, v667) -> u1
-    v681 = sub Field 53438638232309528389504892708671455233, v667
-    v682 = sub v681, Field 1
-    v683 = cast v680 as Field
-    v684 = mul v683, Field 340282366920938463463374607431768211456
-    v685 = add v682, v684
-    v686 = sub Field 64323764613183177041862057485226039389, v668
-    v687 = cast v680 as Field
-    v688 = sub v686, v687
-    v689 = cast v636 as Field
-    v690 = mul v685, v689
-    range_check v690 to 128 bits
-    v691 = cast v636 as Field
-    v692 = mul v688, v691
-    range_check v692 to 128 bits
-    v694 = call f2(v638, v667) -> u1
-    v695 = sub v638, v667
-    v696 = sub v695, Field 1
-    v697 = cast v694 as Field
-    v698 = mul v697, Field 340282366920938463463374607431768211456
-    v699 = add v696, v698
-    v700 = sub v639, v668
-    v701 = cast v694 as Field
-    v702 = sub v700, v701
-    v703 = cast v636 as Field
-    v704 = mul v699, v703
-    range_check v704 to 128 bits
-    v705 = cast v636 as Field
-    v706 = mul v702, v705
-    range_check v706 to 128 bits
-    v707 = not v635
-    v708 = mul v633, v707
-    enable_side_effects v708
-    v710, v711 = call f3(v4) -> (Field, Field)
-    v712 = cast v708 as Field
-    v713 = mul v710, v712
-    range_check v713 to 128 bits
-    v714 = cast v708 as Field
-    v715 = mul v711, v714
-    range_check v715 to 128 bits
-    v716 = mul Field 340282366920938463463374607431768211456, v711
-    v717 = add v710, v716
-    v718 = eq v4, v717
-    v719 = cast v708 as Field
-    v720 = mul v4, v719
-    v721 = mul v717, v719
-    constrain v720 == v721
-    v723 = call f2(Field 53438638232309528389504892708671455233, v710) -> u1
-    v724 = sub Field 53438638232309528389504892708671455233, v710
-    v725 = sub v724, Field 1
-    v726 = cast v723 as Field
-    v727 = mul v726, Field 340282366920938463463374607431768211456
-    v728 = add v725, v727
-    v729 = sub Field 64323764613183177041862057485226039389, v711
-    v730 = cast v723 as Field
-    v731 = sub v729, v730
-    v732 = cast v708 as Field
-    v733 = mul v728, v732
-    range_check v733 to 128 bits
-    v734 = cast v708 as Field
-    v735 = mul v731, v734
-    range_check v735 to 128 bits
-    v737, v738 = call f3(Field 0) -> (Field, Field)
-    v739 = cast v708 as Field
-    v740 = mul v737, v739
-    range_check v740 to 128 bits
-    v741 = cast v708 as Field
-    v742 = mul v738, v741
-    range_check v742 to 128 bits
-    v743 = mul Field 340282366920938463463374607431768211456, v738
-    v744 = add v737, v743
-    v745 = eq Field 0, v744
-    v746 = cast v708 as Field
-    v747 = mul v744, v746
-    constrain Field 0 == v747
-    v749 = call f2(Field 53438638232309528389504892708671455233, v737) -> u1
-    v750 = sub Field 53438638232309528389504892708671455233, v737
-    v751 = sub v750, Field 1
-    v752 = cast v749 as Field
-    v753 = mul v752, Field 340282366920938463463374607431768211456
-    v754 = add v751, v753
-    v755 = sub Field 64323764613183177041862057485226039389, v738
-    v756 = cast v749 as Field
-    v757 = sub v755, v756
-    v758 = cast v708 as Field
-    v759 = mul v754, v758
-    range_check v759 to 128 bits
-    v760 = cast v708 as Field
-    v761 = mul v757, v760
-    range_check v761 to 128 bits
-    v763 = call f2(v710, v737) -> u1
-    v764 = sub v710, v737
-    v765 = sub v764, Field 1
-    v766 = cast v763 as Field
-    v767 = mul v766, Field 340282366920938463463374607431768211456
-    v768 = add v765, v767
-    v769 = sub v711, v738
-    v770 = cast v763 as Field
-    v771 = sub v769, v770
-    v772 = cast v708 as Field
-    v773 = mul v768, v772
-    range_check v773 to 128 bits
-    v774 = cast v708 as Field
-    v775 = mul v771, v774
-    range_check v775 to 128 bits
-    enable_side_effects v708
-    v776 = not v708
-    v777 = cast v708 as Field
-    v778 = cast v776 as Field
-    enable_side_effects u1 1
-    v779 = sub v777, v629
-    return v779
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Remove IfElse:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = allocate -> &mut Field
-    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v40 = allocate -> &mut u1
-    enable_side_effects u1 1
-    v43 = array_get v9, index u32 0 -> u8
-    v44 = eq v43, u8 48
-    v45 = not v44
-    enable_side_effects v45
-    v46 = array_get v9, index u32 0 -> u8
-    v47 = lt v46, u8 48
-    v48 = mul v47, v45
-    constrain v48 == v45
-    enable_side_effects v44
-    v50 = array_get v9, index u32 1 -> u8
-    v51 = eq v50, u8 100
-    v52 = not v51
-    v53 = mul v44, v52
-    enable_side_effects v53
-    v54 = array_get v9, index u32 1 -> u8
-    v55 = lt v54, u8 100
-    v56 = mul v55, v53
-    constrain v56 == v53
-    v57 = not v53
-    v58 = mul v57, v45
-    v59 = unchecked_add v53, v58
-    v60 = mul v44, v51
-    enable_side_effects u1 1
-    v61 = not v59
-    enable_side_effects v61
-    v63 = array_get v9, index u32 2 -> u8
-    v64 = eq v63, u8 78
-    v65 = not v64
-    v66 = mul v61, v65
-    enable_side_effects v66
-    v67 = array_get v9, index u32 2 -> u8
-    v68 = lt v67, u8 78
-    v69 = mul v68, v66
-    constrain v69 == v66
-    v70 = not v66
-    v71 = mul v70, v59
-    v72 = unchecked_add v66, v71
-    v73 = mul v61, v64
-    enable_side_effects u1 1
-    v74 = not v72
-    enable_side_effects v74
-    v76 = array_get v9, index u32 3 -> u8
-    v77 = eq v76, u8 114
-    v78 = not v77
-    v79 = mul v74, v78
-    enable_side_effects v79
-    v80 = array_get v9, index u32 3 -> u8
-    v81 = lt v80, u8 114
-    v82 = mul v81, v79
-    constrain v82 == v79
-    v83 = not v79
-    v84 = mul v83, v72
-    v85 = unchecked_add v79, v84
-    v86 = mul v74, v77
-    enable_side_effects u1 1
-    v87 = not v85
-    enable_side_effects v87
-    v89 = array_get v9, index u32 4 -> u8
-    v90 = eq v89, u8 225
-    v91 = not v90
-    v92 = mul v87, v91
-    enable_side_effects v92
-    v93 = array_get v9, index u32 4 -> u8
-    v94 = lt v93, u8 225
-    v95 = mul v94, v92
-    constrain v95 == v92
-    v96 = not v92
-    v97 = mul v96, v85
-    v98 = unchecked_add v92, v97
-    v99 = mul v87, v90
-    enable_side_effects u1 1
-    v100 = not v98
-    enable_side_effects v100
-    v102 = array_get v9, index u32 5 -> u8
-    v103 = eq v102, u8 49
-    v104 = not v103
-    v105 = mul v100, v104
-    enable_side_effects v105
-    v106 = array_get v9, index u32 5 -> u8
-    v107 = lt v106, u8 49
-    v108 = mul v107, v105
-    constrain v108 == v105
-    v109 = not v105
-    v110 = mul v109, v98
-    v111 = unchecked_add v105, v110
-    v112 = mul v100, v103
-    enable_side_effects u1 1
-    v113 = not v111
-    enable_side_effects v113
-    v115 = array_get v9, index u32 6 -> u8
-    v116 = eq v115, u8 160
-    v117 = not v116
-    v118 = mul v113, v117
-    enable_side_effects v118
-    v119 = array_get v9, index u32 6 -> u8
-    v120 = lt v119, u8 160
-    v121 = mul v120, v118
-    constrain v121 == v118
-    v122 = not v118
-    v123 = mul v122, v111
-    v124 = unchecked_add v118, v123
-    v125 = mul v113, v116
-    enable_side_effects u1 1
-    v126 = not v124
-    enable_side_effects v126
-    v128 = array_get v9, index u32 7 -> u8
-    v129 = eq v128, u8 41
-    v130 = not v129
-    v131 = mul v126, v130
-    enable_side_effects v131
-    v132 = array_get v9, index u32 7 -> u8
-    v133 = lt v132, u8 41
-    v134 = mul v133, v131
-    constrain v134 == v131
-    v135 = not v131
-    v136 = mul v135, v124
-    v137 = unchecked_add v131, v136
-    v138 = mul v126, v129
-    enable_side_effects u1 1
-    v139 = not v137
-    enable_side_effects v139
-    v141 = array_get v9, index u32 8 -> u8
-    v142 = eq v141, u8 184
-    v143 = not v142
-    v144 = mul v139, v143
-    enable_side_effects v144
-    v145 = array_get v9, index u32 8 -> u8
-    v146 = lt v145, u8 184
-    v147 = mul v146, v144
-    constrain v147 == v144
-    v148 = not v144
-    v149 = mul v148, v137
-    v150 = unchecked_add v144, v149
-    v151 = mul v139, v142
-    enable_side_effects u1 1
-    v152 = not v150
-    enable_side_effects v152
-    v154 = array_get v9, index u32 9 -> u8
-    v155 = eq v154, u8 80
-    v156 = not v155
-    v157 = mul v152, v156
-    enable_side_effects v157
-    v158 = array_get v9, index u32 9 -> u8
-    v159 = lt v158, u8 80
-    v160 = mul v159, v157
-    constrain v160 == v157
-    v161 = not v157
-    v162 = mul v161, v150
-    v163 = unchecked_add v157, v162
-    v164 = mul v152, v155
-    enable_side_effects u1 1
-    v165 = not v163
-    enable_side_effects v165
-    v167 = array_get v9, index u32 10 -> u8
-    v168 = eq v167, u8 69
-    v169 = not v168
-    v170 = mul v165, v169
-    enable_side_effects v170
-    v171 = array_get v9, index u32 10 -> u8
-    v172 = lt v171, u8 69
-    v173 = mul v172, v170
-    constrain v173 == v170
-    v174 = not v170
-    v175 = mul v174, v163
-    v176 = unchecked_add v170, v175
-    v177 = mul v165, v168
-    enable_side_effects u1 1
-    v178 = not v176
-    enable_side_effects v178
-    v180 = array_get v9, index u32 11 -> u8
-    v181 = eq v180, u8 182
-    v182 = not v181
-    v183 = mul v178, v182
-    enable_side_effects v183
-    v184 = array_get v9, index u32 11 -> u8
-    v185 = lt v184, u8 182
-    v186 = mul v185, v183
-    constrain v186 == v183
-    v187 = not v183
-    v188 = mul v187, v176
-    v189 = unchecked_add v183, v188
-    v190 = mul v178, v181
-    enable_side_effects u1 1
-    v191 = not v189
-    enable_side_effects v191
-    v193 = array_get v9, index u32 12 -> u8
-    v194 = eq v193, u8 129
-    v195 = not v194
-    v196 = mul v191, v195
-    enable_side_effects v196
-    v197 = array_get v9, index u32 12 -> u8
-    v198 = lt v197, u8 129
-    v199 = mul v198, v196
-    constrain v199 == v196
-    v200 = not v196
-    v201 = mul v200, v189
-    v202 = unchecked_add v196, v201
-    v203 = mul v191, v194
-    enable_side_effects u1 1
-    v204 = not v202
-    enable_side_effects v204
-    v206 = array_get v9, index u32 13 -> u8
-    v207 = eq v206, u8 129
-    v208 = not v207
-    v209 = mul v204, v208
-    enable_side_effects v209
-    v210 = array_get v9, index u32 13 -> u8
-    v211 = lt v210, u8 129
-    v212 = mul v211, v209
-    constrain v212 == v209
-    v213 = not v209
-    v214 = mul v213, v202
-    v215 = unchecked_add v209, v214
-    v216 = mul v204, v207
-    enable_side_effects u1 1
-    v217 = not v215
-    enable_side_effects v217
-    v219 = array_get v9, index u32 14 -> u8
-    v220 = eq v219, u8 88
-    v221 = not v220
-    v222 = mul v217, v221
-    enable_side_effects v222
-    v223 = array_get v9, index u32 14 -> u8
-    v224 = lt v223, u8 88
-    v225 = mul v224, v222
-    constrain v225 == v222
-    v226 = not v222
-    v227 = mul v226, v215
-    v228 = unchecked_add v222, v227
-    v229 = mul v217, v220
-    enable_side_effects u1 1
-    v230 = not v228
-    enable_side_effects v230
-    v232 = array_get v9, index u32 15 -> u8
-    v233 = eq v232, u8 93
-    v234 = not v233
-    v235 = mul v230, v234
-    enable_side_effects v235
-    v236 = array_get v9, index u32 15 -> u8
-    v237 = lt v236, u8 93
-    v238 = mul v237, v235
-    constrain v238 == v235
-    v239 = not v235
-    v240 = mul v239, v228
-    v241 = unchecked_add v235, v240
-    v242 = mul v230, v233
-    enable_side_effects u1 1
-    v243 = not v241
-    enable_side_effects v243
-    v245 = array_get v9, index u32 16 -> u8
-    v246 = eq v245, u8 40
-    v247 = not v246
-    v248 = mul v243, v247
-    enable_side_effects v248
-    v249 = array_get v9, index u32 16 -> u8
-    v250 = lt v249, u8 40
-    v251 = mul v250, v248
-    constrain v251 == v248
-    v252 = not v248
-    v253 = mul v252, v241
-    v254 = unchecked_add v248, v253
-    v255 = mul v243, v246
-    enable_side_effects u1 1
-    v256 = not v254
-    enable_side_effects v256
-    v258 = array_get v9, index u32 17 -> u8
-    v259 = eq v258, u8 51
-    v260 = not v259
-    v261 = mul v256, v260
-    enable_side_effects v261
-    v262 = array_get v9, index u32 17 -> u8
-    v263 = lt v262, u8 51
-    v264 = mul v263, v261
-    constrain v264 == v261
-    v265 = not v261
-    v266 = mul v265, v254
-    v267 = unchecked_add v261, v266
-    v268 = mul v256, v259
-    enable_side_effects u1 1
-    v269 = not v267
-    enable_side_effects v269
-    v271 = array_get v9, index u32 18 -> u8
-    v272 = eq v271, u8 232
-    v273 = not v272
-    v274 = mul v269, v273
-    enable_side_effects v274
-    v275 = array_get v9, index u32 18 -> u8
-    v276 = lt v275, u8 232
-    v277 = mul v276, v274
-    constrain v277 == v274
-    v278 = not v274
-    v279 = mul v278, v267
-    v280 = unchecked_add v274, v279
-    v281 = mul v269, v272
-    enable_side_effects u1 1
-    v282 = not v280
-    enable_side_effects v282
-    v284 = array_get v9, index u32 19 -> u8
-    v285 = eq v284, u8 72
-    v286 = not v285
-    v287 = mul v282, v286
-    enable_side_effects v287
-    v288 = array_get v9, index u32 19 -> u8
-    v289 = lt v288, u8 72
-    v290 = mul v289, v287
-    constrain v290 == v287
-    v291 = not v287
-    v292 = mul v291, v280
-    v293 = unchecked_add v287, v292
-    v294 = mul v282, v285
-    enable_side_effects u1 1
-    v295 = not v293
-    enable_side_effects v295
-    v297 = array_get v9, index u32 20 -> u8
-    v298 = eq v297, u8 121
-    v299 = not v298
-    v300 = mul v295, v299
-    enable_side_effects v300
-    v301 = array_get v9, index u32 20 -> u8
-    v302 = lt v301, u8 121
-    v303 = mul v302, v300
-    constrain v303 == v300
-    v304 = not v300
-    v305 = mul v304, v293
-    v306 = unchecked_add v300, v305
-    v307 = mul v295, v298
-    enable_side_effects u1 1
-    v308 = not v306
-    enable_side_effects v308
-    v310 = array_get v9, index u32 21 -> u8
-    v311 = eq v310, u8 185
-    v312 = not v311
-    v313 = mul v308, v312
-    enable_side_effects v313
-    v314 = array_get v9, index u32 21 -> u8
-    v315 = lt v314, u8 185
-    v316 = mul v315, v313
-    constrain v316 == v313
-    v317 = not v313
-    v318 = mul v317, v306
-    v319 = unchecked_add v313, v318
-    v320 = mul v308, v311
-    enable_side_effects u1 1
-    v321 = not v319
-    enable_side_effects v321
-    v323 = array_get v9, index u32 22 -> u8
-    v324 = eq v323, u8 112
-    v325 = not v324
-    v326 = mul v321, v325
-    enable_side_effects v326
-    v327 = array_get v9, index u32 22 -> u8
-    v328 = lt v327, u8 112
-    v329 = mul v328, v326
-    constrain v329 == v326
-    v330 = not v326
-    v331 = mul v330, v319
-    v332 = unchecked_add v326, v331
-    v333 = mul v321, v324
-    enable_side_effects u1 1
-    v334 = not v332
-    enable_side_effects v334
-    v336 = array_get v9, index u32 23 -> u8
-    v337 = eq v336, u8 145
-    v338 = not v337
-    v339 = mul v334, v338
-    enable_side_effects v339
-    v340 = array_get v9, index u32 23 -> u8
-    v341 = lt v340, u8 145
-    v342 = mul v341, v339
-    constrain v342 == v339
-    v343 = not v339
-    v344 = mul v343, v332
-    v345 = unchecked_add v339, v344
-    v346 = mul v334, v337
-    enable_side_effects u1 1
-    v347 = not v345
-    enable_side_effects v347
-    v349 = array_get v9, index u32 24 -> u8
-    v350 = eq v349, u8 67
-    v351 = not v350
-    v352 = mul v347, v351
-    enable_side_effects v352
-    v353 = array_get v9, index u32 24 -> u8
-    v354 = lt v353, u8 67
-    v355 = mul v354, v352
-    constrain v355 == v352
-    v356 = not v352
-    v357 = mul v356, v345
-    v358 = unchecked_add v352, v357
-    v359 = mul v347, v350
-    enable_side_effects u1 1
-    v360 = not v358
-    enable_side_effects v360
-    v362 = array_get v9, index u32 25 -> u8
-    v363 = eq v362, u8 225
-    v364 = not v363
-    v365 = mul v360, v364
-    enable_side_effects v365
-    v366 = array_get v9, index u32 25 -> u8
-    v367 = lt v366, u8 225
-    v368 = mul v367, v365
-    constrain v368 == v365
-    v369 = not v365
-    v370 = mul v369, v358
-    v371 = unchecked_add v365, v370
-    v372 = mul v360, v363
-    enable_side_effects u1 1
-    v373 = not v371
-    enable_side_effects v373
-    v375 = array_get v9, index u32 26 -> u8
-    v376 = eq v375, u8 245
-    v377 = not v376
-    v378 = mul v373, v377
-    enable_side_effects v378
-    v379 = array_get v9, index u32 26 -> u8
-    v380 = lt v379, u8 245
-    v381 = mul v380, v378
-    constrain v381 == v378
-    v382 = not v378
-    v383 = mul v382, v371
-    v384 = unchecked_add v378, v383
-    v385 = mul v373, v376
-    enable_side_effects u1 1
-    v386 = not v384
-    enable_side_effects v386
-    v388 = array_get v9, index u32 27 -> u8
-    v389 = eq v388, u8 147
-    v390 = not v389
-    v391 = mul v386, v390
-    enable_side_effects v391
-    v392 = array_get v9, index u32 27 -> u8
-    v393 = lt v392, u8 147
-    v394 = mul v393, v391
-    constrain v394 == v391
-    v395 = not v391
-    v396 = mul v395, v384
-    v397 = unchecked_add v391, v396
-    v398 = mul v386, v389
-    enable_side_effects u1 1
-    v399 = not v397
-    enable_side_effects v399
-    v401 = array_get v9, index u32 28 -> u8
-    v402 = eq v401, u8 240
-    v403 = not v402
-    v404 = mul v399, v403
-    enable_side_effects v404
-    v405 = array_get v9, index u32 28 -> u8
-    v406 = lt v405, u8 240
-    v407 = mul v406, v404
-    constrain v407 == v404
-    v408 = not v404
-    v409 = mul v408, v397
-    v410 = unchecked_add v404, v409
-    v411 = mul v399, v402
-    enable_side_effects u1 1
-    v412 = not v410
-    enable_side_effects v412
-    v414 = array_get v9, index u32 29 -> u8
-    v415 = eq v414, u8 0
-    v416 = not v415
-    v417 = mul v412, v416
-    enable_side_effects v417
-    v418 = array_get v9, index u32 29 -> u8
-    constrain u1 0 == v417
-    v420 = not v417
-    v421 = mul v420, v410
-    v422 = unchecked_add v417, v421
-    v423 = mul v412, v415
-    enable_side_effects u1 1
-    v424 = not v422
-    enable_side_effects v424
-    v426 = array_get v9, index u32 30 -> u8
-    v427 = eq v426, u8 0
-    v428 = not v427
-    v429 = mul v424, v428
-    enable_side_effects v429
-    v430 = array_get v9, index u32 30 -> u8
-    constrain u1 0 == v429
-    v431 = not v429
-    v432 = mul v431, v422
-    v433 = unchecked_add v429, v432
-    v434 = mul v424, v427
-    enable_side_effects u1 1
-    v435 = not v433
-    enable_side_effects v435
-    v437 = array_get v9, index u32 31 -> u8
-    v438 = eq v437, u8 1
-    v439 = not v438
-    v440 = mul v435, v439
-    enable_side_effects v440
-    v441 = array_get v9, index u32 31 -> u8
-    v442 = eq v441, u8 0
-    v443 = cast v440 as u8
-    v444 = unchecked_mul v441, v443
-    constrain v444 == u8 0
-    v445 = not v440
-    v446 = mul v445, v433
-    v447 = unchecked_add v440, v446
-    v448 = mul v435, v438
-    enable_side_effects u1 1
-    constrain v447 == u1 1
-    v449 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v450 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v451 = allocate -> &mut u1
-    enable_side_effects u1 1
-    v452 = allocate -> &mut [u8; 32]
-    v453 = array_get v9, index u32 0 -> u8
-    v454 = make_array [v453, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v455 = array_get v9, index u32 1 -> u8
-    v456 = make_array [v453, v455, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v457 = array_get v9, index u32 2 -> u8
-    v458 = make_array [v453, v455, v457, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v459 = array_get v9, index u32 3 -> u8
-    v460 = make_array [v453, v455, v457, v459, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v461 = array_get v9, index u32 4 -> u8
-    v462 = make_array [v453, v455, v457, v459, v461, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v463 = array_get v9, index u32 5 -> u8
-    v464 = make_array [v453, v455, v457, v459, v461, v463, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v465 = array_get v9, index u32 6 -> u8
-    v466 = make_array [v453, v455, v457, v459, v461, v463, v465, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v467 = array_get v9, index u32 7 -> u8
-    v468 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v469 = array_get v9, index u32 8 -> u8
-    v470 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v471 = array_get v9, index u32 9 -> u8
-    v472 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v473 = array_get v9, index u32 10 -> u8
-    v474 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v475 = array_get v9, index u32 11 -> u8
-    v476 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v477 = array_get v9, index u32 12 -> u8
-    v478 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v479 = array_get v9, index u32 13 -> u8
-    v480 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v481 = array_get v9, index u32 14 -> u8
-    v482 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v483 = array_get v9, index u32 15 -> u8
-    v484 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v485 = array_get v9, index u32 16 -> u8
-    v486 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v487 = array_get v9, index u32 17 -> u8
-    v488 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v489 = array_get v9, index u32 18 -> u8
-    v490 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v491 = array_get v9, index u32 19 -> u8
-    v492 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v493 = array_get v9, index u32 20 -> u8
-    v494 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v495 = array_get v9, index u32 21 -> u8
-    v496 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v497 = array_get v9, index u32 22 -> u8
-    v498 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v499 = array_get v9, index u32 23 -> u8
-    v500 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v501 = array_get v9, index u32 24 -> u8
-    v502 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v503 = array_get v9, index u32 25 -> u8
-    v504 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v505 = array_get v9, index u32 26 -> u8
-    v506 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v507 = array_get v9, index u32 27 -> u8
-    v508 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v509 = array_get v9, index u32 28 -> u8
-    v510 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, u8 0, u8 0, u8 0] : [u8; 32]
-    v511 = array_get v9, index u32 29 -> u8
-    v512 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, u8 0, u8 0] : [u8; 32]
-    v513 = array_get v9, index u32 30 -> u8
-    v514 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, v513, u8 0] : [u8; 32]
-    v515 = array_get v9, index u32 31 -> u8
-    v516 = make_array [v453, v455, v457, v459, v461, v463, v465, v467, v469, v471, v473, v475, v477, v479, v481, v483, v485, v487, v489, v491, v493, v495, v497, v499, v501, v503, v505, v507, v509, v511, v513, v515] : [u8; 32]
-    v517 = allocate -> &mut Field
-    v518 = allocate -> &mut Field
-    v519 = allocate -> &mut Field
-    v520 = cast v483 as Field
-    v521 = cast v515 as Field
-    v522 = cast v481 as Field
-    v524 = mul v522, Field 256
-    v525 = add v520, v524
-    v526 = cast v513 as Field
-    v527 = mul v526, Field 256
-    v528 = add v521, v527
-    v529 = cast v479 as Field
-    v531 = mul v529, Field 65536
-    v532 = add v525, v531
-    v533 = cast v511 as Field
-    v534 = mul v533, Field 65536
-    v535 = add v528, v534
-    v536 = cast v477 as Field
-    v538 = mul v536, Field 16777216
-    v539 = add v532, v538
-    v540 = cast v509 as Field
-    v541 = mul v540, Field 16777216
-    v542 = add v535, v541
-    v543 = cast v475 as Field
-    v545 = mul v543, Field 4294967296
-    v546 = add v539, v545
-    v547 = cast v507 as Field
-    v548 = mul v547, Field 4294967296
-    v549 = add v542, v548
-    v550 = cast v473 as Field
-    v552 = mul v550, Field 1099511627776
-    v553 = add v546, v552
-    v554 = cast v505 as Field
-    v555 = mul v554, Field 1099511627776
-    v556 = add v549, v555
-    v557 = cast v471 as Field
-    v559 = mul v557, Field 281474976710656
-    v560 = add v553, v559
-    v561 = cast v503 as Field
-    v562 = mul v561, Field 281474976710656
-    v563 = add v556, v562
-    v564 = cast v469 as Field
-    v566 = mul v564, Field 72057594037927936
-    v567 = add v560, v566
-    v568 = cast v501 as Field
-    v569 = mul v568, Field 72057594037927936
-    v570 = add v563, v569
-    v571 = cast v467 as Field
-    v573 = mul v571, Field 18446744073709551616
-    v574 = add v567, v573
-    v575 = cast v499 as Field
-    v576 = mul v575, Field 18446744073709551616
-    v577 = add v570, v576
-    v578 = cast v465 as Field
-    v580 = mul v578, Field 4722366482869645213696
-    v581 = add v574, v580
-    v582 = cast v497 as Field
-    v583 = mul v582, Field 4722366482869645213696
-    v584 = add v577, v583
-    v585 = cast v463 as Field
-    v587 = mul v585, Field 1208925819614629174706176
-    v588 = add v581, v587
-    v589 = cast v495 as Field
-    v590 = mul v589, Field 1208925819614629174706176
-    v591 = add v584, v590
-    v592 = cast v461 as Field
-    v594 = mul v592, Field 309485009821345068724781056
-    v595 = add v588, v594
-    v596 = cast v493 as Field
-    v597 = mul v596, Field 309485009821345068724781056
-    v598 = add v591, v597
-    v599 = cast v459 as Field
-    v601 = mul v599, Field 79228162514264337593543950336
-    v602 = add v595, v601
-    v603 = cast v491 as Field
-    v604 = mul v603, Field 79228162514264337593543950336
-    v605 = add v598, v604
-    v606 = cast v457 as Field
-    v608 = mul v606, Field 20282409603651670423947251286016
-    v609 = add v602, v608
-    v610 = cast v489 as Field
-    v611 = mul v610, Field 20282409603651670423947251286016
-    v612 = add v605, v611
-    v613 = cast v455 as Field
-    v615 = mul v613, Field 5192296858534827628530496329220096
-    v616 = add v609, v615
-    v617 = cast v487 as Field
-    v618 = mul v617, Field 5192296858534827628530496329220096
-    v619 = add v612, v618
-    v620 = cast v453 as Field
-    v622 = mul v620, Field 1329227995784915872903807060280344576
-    v623 = add v616, v622
-    v624 = cast v485 as Field
-    v625 = mul v624, Field 1329227995784915872903807060280344576
-    v626 = add v619, v625
-    v628 = mul v623, Field 340282366920938463463374607431768211456
-    v629 = add v626, v628
-    v630 = allocate -> &mut Field
-    v632 = eq v4, Field 0
-    enable_side_effects v632
-    v633 = not v632
-    enable_side_effects v633
-    v635 = call f1(v4, Field 0) -> u1
-    v636 = mul v633, v635
-    enable_side_effects v636
-    v638, v639 = call f3(Field 0) -> (Field, Field)
-    v640 = cast v636 as Field
-    v641 = mul v638, v640
-    range_check v641 to 128 bits
-    v642 = cast v636 as Field
-    v643 = mul v639, v642
-    range_check v643 to 128 bits
-    v644 = mul Field 340282366920938463463374607431768211456, v639
-    v645 = add v638, v644
-    v646 = eq Field 0, v645
-    v647 = cast v636 as Field
-    v648 = mul v645, v647
-    constrain Field 0 == v648
-    v651 = call f2(Field 53438638232309528389504892708671455233, v638) -> u1
-    v652 = sub Field 53438638232309528389504892708671455233, v638
-    v654 = sub v652, Field 1
-    v655 = cast v651 as Field
-    v656 = mul v655, Field 340282366920938463463374607431768211456
-    v657 = add v654, v656
-    v659 = sub Field 64323764613183177041862057485226039389, v639
-    v660 = cast v651 as Field
-    v661 = sub v659, v660
-    v662 = cast v636 as Field
-    v663 = mul v657, v662
-    range_check v663 to 128 bits
-    v664 = cast v636 as Field
-    v665 = mul v661, v664
-    range_check v665 to 128 bits
-    v667, v668 = call f3(v4) -> (Field, Field)
-    v669 = cast v636 as Field
-    v670 = mul v667, v669
-    range_check v670 to 128 bits
-    v671 = cast v636 as Field
-    v672 = mul v668, v671
-    range_check v672 to 128 bits
-    v673 = mul Field 340282366920938463463374607431768211456, v668
-    v674 = add v667, v673
-    v675 = eq v4, v674
-    v676 = cast v636 as Field
-    v677 = mul v4, v676
-    v678 = mul v674, v676
-    constrain v677 == v678
-    v680 = call f2(Field 53438638232309528389504892708671455233, v667) -> u1
-    v681 = sub Field 53438638232309528389504892708671455233, v667
-    v682 = sub v681, Field 1
-    v683 = cast v680 as Field
-    v684 = mul v683, Field 340282366920938463463374607431768211456
-    v685 = add v682, v684
-    v686 = sub Field 64323764613183177041862057485226039389, v668
-    v687 = cast v680 as Field
-    v688 = sub v686, v687
-    v689 = cast v636 as Field
-    v690 = mul v685, v689
-    range_check v690 to 128 bits
-    v691 = cast v636 as Field
-    v692 = mul v688, v691
-    range_check v692 to 128 bits
-    v694 = call f2(v638, v667) -> u1
-    v695 = sub v638, v667
-    v696 = sub v695, Field 1
-    v697 = cast v694 as Field
-    v698 = mul v697, Field 340282366920938463463374607431768211456
-    v699 = add v696, v698
-    v700 = sub v639, v668
-    v701 = cast v694 as Field
-    v702 = sub v700, v701
-    v703 = cast v636 as Field
-    v704 = mul v699, v703
-    range_check v704 to 128 bits
-    v705 = cast v636 as Field
-    v706 = mul v702, v705
-    range_check v706 to 128 bits
-    v707 = not v635
-    v708 = mul v633, v707
-    enable_side_effects v708
-    v710, v711 = call f3(v4) -> (Field, Field)
-    v712 = cast v708 as Field
-    v713 = mul v710, v712
-    range_check v713 to 128 bits
-    v714 = cast v708 as Field
-    v715 = mul v711, v714
-    range_check v715 to 128 bits
-    v716 = mul Field 340282366920938463463374607431768211456, v711
-    v717 = add v710, v716
-    v718 = eq v4, v717
-    v719 = cast v708 as Field
-    v720 = mul v4, v719
-    v721 = mul v717, v719
-    constrain v720 == v721
-    v723 = call f2(Field 53438638232309528389504892708671455233, v710) -> u1
-    v724 = sub Field 53438638232309528389504892708671455233, v710
-    v725 = sub v724, Field 1
-    v726 = cast v723 as Field
-    v727 = mul v726, Field 340282366920938463463374607431768211456
-    v728 = add v725, v727
-    v729 = sub Field 64323764613183177041862057485226039389, v711
-    v730 = cast v723 as Field
-    v731 = sub v729, v730
-    v732 = cast v708 as Field
-    v733 = mul v728, v732
-    range_check v733 to 128 bits
-    v734 = cast v708 as Field
-    v735 = mul v731, v734
-    range_check v735 to 128 bits
-    v737, v738 = call f3(Field 0) -> (Field, Field)
-    v739 = cast v708 as Field
-    v740 = mul v737, v739
-    range_check v740 to 128 bits
-    v741 = cast v708 as Field
-    v742 = mul v738, v741
-    range_check v742 to 128 bits
-    v743 = mul Field 340282366920938463463374607431768211456, v738
-    v744 = add v737, v743
-    v745 = eq Field 0, v744
-    v746 = cast v708 as Field
-    v747 = mul v744, v746
-    constrain Field 0 == v747
-    v749 = call f2(Field 53438638232309528389504892708671455233, v737) -> u1
-    v750 = sub Field 53438638232309528389504892708671455233, v737
-    v751 = sub v750, Field 1
-    v752 = cast v749 as Field
-    v753 = mul v752, Field 340282366920938463463374607431768211456
-    v754 = add v751, v753
-    v755 = sub Field 64323764613183177041862057485226039389, v738
-    v756 = cast v749 as Field
-    v757 = sub v755, v756
-    v758 = cast v708 as Field
-    v759 = mul v754, v758
-    range_check v759 to 128 bits
-    v760 = cast v708 as Field
-    v761 = mul v757, v760
-    range_check v761 to 128 bits
-    v763 = call f2(v710, v737) -> u1
-    v764 = sub v710, v737
-    v765 = sub v764, Field 1
-    v766 = cast v763 as Field
-    v767 = mul v766, Field 340282366920938463463374607431768211456
-    v768 = add v765, v767
-    v769 = sub v711, v738
-    v770 = cast v763 as Field
-    v771 = sub v769, v770
-    v772 = cast v708 as Field
-    v773 = mul v768, v772
-    range_check v773 to 128 bits
-    v774 = cast v708 as Field
-    v775 = mul v771, v774
-    range_check v775 to 128 bits
-    enable_side_effects v708
-    v776 = not v708
-    v777 = cast v708 as Field
-    v778 = cast v776 as Field
-    enable_side_effects u1 1
-    v779 = sub v777, v629
-    return v779
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Constant Folding:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = allocate -> &mut Field
-    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v40 = allocate -> &mut u1
-    enable_side_effects u1 1
-    v43 = array_get v9, index u32 0 -> u8
-    v44 = eq v43, u8 48
-    v45 = not v44
-    enable_side_effects v45
-    v46 = lt v43, u8 48
-    v47 = mul v46, v45
-    constrain v47 == v45
-    enable_side_effects v44
-    v49 = array_get v9, index u32 1 -> u8
-    v50 = eq v49, u8 100
-    v51 = not v50
-    v52 = mul v44, v51
-    enable_side_effects v52
-    v53 = lt v49, u8 100
-    v54 = mul v53, v52
-    constrain v54 == v52
-    v55 = not v52
-    v56 = mul v55, v45
-    v57 = unchecked_add v52, v56
-    v58 = mul v44, v50
-    enable_side_effects u1 1
-    v59 = not v57
-    enable_side_effects v59
-    v61 = array_get v9, index u32 2 -> u8
-    v62 = eq v61, u8 78
-    v63 = not v62
-    v64 = mul v59, v63
-    enable_side_effects v64
-    v65 = lt v61, u8 78
-    v66 = mul v65, v64
-    constrain v66 == v64
-    v67 = not v64
-    v68 = mul v67, v57
-    v69 = unchecked_add v64, v68
-    v70 = mul v59, v62
-    enable_side_effects u1 1
-    v71 = not v69
-    enable_side_effects v71
-    v73 = array_get v9, index u32 3 -> u8
-    v74 = eq v73, u8 114
-    v75 = not v74
-    v76 = mul v71, v75
-    enable_side_effects v76
-    v77 = lt v73, u8 114
-    v78 = mul v77, v76
-    constrain v78 == v76
-    v79 = not v76
-    v80 = mul v79, v69
-    v81 = unchecked_add v76, v80
-    v82 = mul v71, v74
-    enable_side_effects u1 1
-    v83 = not v81
-    enable_side_effects v83
-    v85 = array_get v9, index u32 4 -> u8
-    v86 = eq v85, u8 225
-    v87 = not v86
-    v88 = mul v83, v87
-    enable_side_effects v88
-    v89 = lt v85, u8 225
-    v90 = mul v89, v88
-    constrain v90 == v88
-    v91 = not v88
-    v92 = mul v91, v81
-    v93 = unchecked_add v88, v92
-    v94 = mul v83, v86
-    enable_side_effects u1 1
-    v95 = not v93
-    enable_side_effects v95
-    v97 = array_get v9, index u32 5 -> u8
-    v98 = eq v97, u8 49
-    v99 = not v98
-    v100 = mul v95, v99
-    enable_side_effects v100
-    v101 = lt v97, u8 49
-    v102 = mul v101, v100
-    constrain v102 == v100
-    v103 = not v100
-    v104 = mul v103, v93
-    v105 = unchecked_add v100, v104
-    v106 = mul v95, v98
-    enable_side_effects u1 1
-    v107 = not v105
-    enable_side_effects v107
-    v109 = array_get v9, index u32 6 -> u8
-    v110 = eq v109, u8 160
-    v111 = not v110
-    v112 = mul v107, v111
-    enable_side_effects v112
-    v113 = lt v109, u8 160
-    v114 = mul v113, v112
-    constrain v114 == v112
-    v115 = not v112
-    v116 = mul v115, v105
-    v117 = unchecked_add v112, v116
-    v118 = mul v107, v110
-    enable_side_effects u1 1
-    v119 = not v117
-    enable_side_effects v119
-    v121 = array_get v9, index u32 7 -> u8
-    v122 = eq v121, u8 41
-    v123 = not v122
-    v124 = mul v119, v123
-    enable_side_effects v124
-    v125 = lt v121, u8 41
-    v126 = mul v125, v124
-    constrain v126 == v124
-    v127 = not v124
-    v128 = mul v127, v117
-    v129 = unchecked_add v124, v128
-    v130 = mul v119, v122
-    enable_side_effects u1 1
-    v131 = not v129
-    enable_side_effects v131
-    v133 = array_get v9, index u32 8 -> u8
-    v134 = eq v133, u8 184
-    v135 = not v134
-    v136 = mul v131, v135
-    enable_side_effects v136
-    v137 = lt v133, u8 184
-    v138 = mul v137, v136
-    constrain v138 == v136
-    v139 = not v136
-    v140 = mul v139, v129
-    v141 = unchecked_add v136, v140
-    v142 = mul v131, v134
-    enable_side_effects u1 1
-    v143 = not v141
-    enable_side_effects v143
-    v145 = array_get v9, index u32 9 -> u8
-    v146 = eq v145, u8 80
-    v147 = not v146
-    v148 = mul v143, v147
-    enable_side_effects v148
-    v149 = lt v145, u8 80
-    v150 = mul v149, v148
-    constrain v150 == v148
-    v151 = not v148
-    v152 = mul v151, v141
-    v153 = unchecked_add v148, v152
-    v154 = mul v143, v146
-    enable_side_effects u1 1
-    v155 = not v153
-    enable_side_effects v155
-    v157 = array_get v9, index u32 10 -> u8
-    v158 = eq v157, u8 69
-    v159 = not v158
-    v160 = mul v155, v159
-    enable_side_effects v160
-    v161 = lt v157, u8 69
-    v162 = mul v161, v160
-    constrain v162 == v160
-    v163 = not v160
-    v164 = mul v163, v153
-    v165 = unchecked_add v160, v164
-    v166 = mul v155, v158
-    enable_side_effects u1 1
-    v167 = not v165
-    enable_side_effects v167
-    v169 = array_get v9, index u32 11 -> u8
-    v170 = eq v169, u8 182
-    v171 = not v170
-    v172 = mul v167, v171
-    enable_side_effects v172
-    v173 = lt v169, u8 182
-    v174 = mul v173, v172
-    constrain v174 == v172
-    v175 = not v172
-    v176 = mul v175, v165
-    v177 = unchecked_add v172, v176
-    v178 = mul v167, v170
-    enable_side_effects u1 1
-    v179 = not v177
-    enable_side_effects v179
-    v181 = array_get v9, index u32 12 -> u8
-    v182 = eq v181, u8 129
-    v183 = not v182
-    v184 = mul v179, v183
-    enable_side_effects v184
-    v185 = lt v181, u8 129
-    v186 = mul v185, v184
-    constrain v186 == v184
-    v187 = not v184
-    v188 = mul v187, v177
-    v189 = unchecked_add v184, v188
-    v190 = mul v179, v182
-    enable_side_effects u1 1
-    v191 = not v189
-    enable_side_effects v191
-    v193 = array_get v9, index u32 13 -> u8
-    v194 = eq v193, u8 129
-    v195 = not v194
-    v196 = mul v191, v195
-    enable_side_effects v196
-    v197 = lt v193, u8 129
-    v198 = mul v197, v196
-    constrain v198 == v196
-    v199 = not v196
-    v200 = mul v199, v189
-    v201 = unchecked_add v196, v200
-    v202 = mul v191, v194
-    enable_side_effects u1 1
-    v203 = not v201
-    enable_side_effects v203
-    v205 = array_get v9, index u32 14 -> u8
-    v206 = eq v205, u8 88
-    v207 = not v206
-    v208 = mul v203, v207
-    enable_side_effects v208
-    v209 = lt v205, u8 88
-    v210 = mul v209, v208
-    constrain v210 == v208
-    v211 = not v208
-    v212 = mul v211, v201
-    v213 = unchecked_add v208, v212
-    v214 = mul v203, v206
-    enable_side_effects u1 1
-    v215 = not v213
-    enable_side_effects v215
-    v217 = array_get v9, index u32 15 -> u8
-    v218 = eq v217, u8 93
-    v219 = not v218
-    v220 = mul v215, v219
-    enable_side_effects v220
-    v221 = lt v217, u8 93
-    v222 = mul v221, v220
-    constrain v222 == v220
-    v223 = not v220
-    v224 = mul v223, v213
-    v225 = unchecked_add v220, v224
-    v226 = mul v215, v218
-    enable_side_effects u1 1
-    v227 = not v225
-    enable_side_effects v227
-    v229 = array_get v9, index u32 16 -> u8
-    v230 = eq v229, u8 40
-    v231 = not v230
-    v232 = mul v227, v231
-    enable_side_effects v232
-    v233 = lt v229, u8 40
-    v234 = mul v233, v232
-    constrain v234 == v232
-    v235 = not v232
-    v236 = mul v235, v225
-    v237 = unchecked_add v232, v236
-    v238 = mul v227, v230
-    enable_side_effects u1 1
-    v239 = not v237
-    enable_side_effects v239
-    v241 = array_get v9, index u32 17 -> u8
-    v242 = eq v241, u8 51
-    v243 = not v242
-    v244 = mul v239, v243
-    enable_side_effects v244
-    v245 = lt v241, u8 51
-    v246 = mul v245, v244
-    constrain v246 == v244
-    v247 = not v244
-    v248 = mul v247, v237
-    v249 = unchecked_add v244, v248
-    v250 = mul v239, v242
-    enable_side_effects u1 1
-    v251 = not v249
-    enable_side_effects v251
-    v253 = array_get v9, index u32 18 -> u8
-    v254 = eq v253, u8 232
-    v255 = not v254
-    v256 = mul v251, v255
-    enable_side_effects v256
-    v257 = lt v253, u8 232
-    v258 = mul v257, v256
-    constrain v258 == v256
-    v259 = not v256
-    v260 = mul v259, v249
-    v261 = unchecked_add v256, v260
-    v262 = mul v251, v254
-    enable_side_effects u1 1
-    v263 = not v261
-    enable_side_effects v263
-    v265 = array_get v9, index u32 19 -> u8
-    v266 = eq v265, u8 72
-    v267 = not v266
-    v268 = mul v263, v267
-    enable_side_effects v268
-    v269 = lt v265, u8 72
-    v270 = mul v269, v268
-    constrain v270 == v268
-    v271 = not v268
-    v272 = mul v271, v261
-    v273 = unchecked_add v268, v272
-    v274 = mul v263, v266
-    enable_side_effects u1 1
-    v275 = not v273
-    enable_side_effects v275
-    v277 = array_get v9, index u32 20 -> u8
-    v278 = eq v277, u8 121
-    v279 = not v278
-    v280 = mul v275, v279
-    enable_side_effects v280
-    v281 = lt v277, u8 121
-    v282 = mul v281, v280
-    constrain v282 == v280
-    v283 = not v280
-    v284 = mul v283, v273
-    v285 = unchecked_add v280, v284
-    v286 = mul v275, v278
-    enable_side_effects u1 1
-    v287 = not v285
-    enable_side_effects v287
-    v289 = array_get v9, index u32 21 -> u8
-    v290 = eq v289, u8 185
-    v291 = not v290
-    v292 = mul v287, v291
-    enable_side_effects v292
-    v293 = lt v289, u8 185
-    v294 = mul v293, v292
-    constrain v294 == v292
-    v295 = not v292
-    v296 = mul v295, v285
-    v297 = unchecked_add v292, v296
-    v298 = mul v287, v290
-    enable_side_effects u1 1
-    v299 = not v297
-    enable_side_effects v299
-    v301 = array_get v9, index u32 22 -> u8
-    v302 = eq v301, u8 112
-    v303 = not v302
-    v304 = mul v299, v303
-    enable_side_effects v304
-    v305 = lt v301, u8 112
-    v306 = mul v305, v304
-    constrain v306 == v304
-    v307 = not v304
-    v308 = mul v307, v297
-    v309 = unchecked_add v304, v308
-    v310 = mul v299, v302
-    enable_side_effects u1 1
-    v311 = not v309
-    enable_side_effects v311
-    v313 = array_get v9, index u32 23 -> u8
-    v314 = eq v313, u8 145
-    v315 = not v314
-    v316 = mul v311, v315
-    enable_side_effects v316
-    v317 = lt v313, u8 145
-    v318 = mul v317, v316
-    constrain v318 == v316
-    v319 = not v316
-    v320 = mul v319, v309
-    v321 = unchecked_add v316, v320
-    v322 = mul v311, v314
-    enable_side_effects u1 1
-    v323 = not v321
-    enable_side_effects v323
-    v325 = array_get v9, index u32 24 -> u8
-    v326 = eq v325, u8 67
-    v327 = not v326
-    v328 = mul v323, v327
-    enable_side_effects v328
-    v329 = lt v325, u8 67
-    v330 = mul v329, v328
-    constrain v330 == v328
-    v331 = not v328
-    v332 = mul v331, v321
-    v333 = unchecked_add v328, v332
-    v334 = mul v323, v326
-    enable_side_effects u1 1
-    v335 = not v333
-    enable_side_effects v335
-    v337 = array_get v9, index u32 25 -> u8
-    v338 = eq v337, u8 225
-    v339 = not v338
-    v340 = mul v335, v339
-    enable_side_effects v340
-    v341 = lt v337, u8 225
-    v342 = mul v341, v340
-    constrain v342 == v340
-    v343 = not v340
-    v344 = mul v343, v333
-    v345 = unchecked_add v340, v344
-    v346 = mul v335, v338
-    enable_side_effects u1 1
-    v347 = not v345
-    enable_side_effects v347
-    v349 = array_get v9, index u32 26 -> u8
-    v350 = eq v349, u8 245
-    v351 = not v350
-    v352 = mul v347, v351
-    enable_side_effects v352
-    v353 = lt v349, u8 245
-    v354 = mul v353, v352
-    constrain v354 == v352
-    v355 = not v352
-    v356 = mul v355, v345
-    v357 = unchecked_add v352, v356
-    v358 = mul v347, v350
-    enable_side_effects u1 1
-    v359 = not v357
-    enable_side_effects v359
-    v361 = array_get v9, index u32 27 -> u8
-    v362 = eq v361, u8 147
-    v363 = not v362
-    v364 = mul v359, v363
-    enable_side_effects v364
-    v365 = lt v361, u8 147
-    v366 = mul v365, v364
-    constrain v366 == v364
-    v367 = not v364
-    v368 = mul v367, v357
-    v369 = unchecked_add v364, v368
-    v370 = mul v359, v362
-    enable_side_effects u1 1
-    v371 = not v369
-    enable_side_effects v371
-    v373 = array_get v9, index u32 28 -> u8
-    v374 = eq v373, u8 240
-    v375 = not v374
-    v376 = mul v371, v375
-    enable_side_effects v376
-    v377 = lt v373, u8 240
-    v378 = mul v377, v376
-    constrain v378 == v376
-    v379 = not v376
-    v380 = mul v379, v369
-    v381 = unchecked_add v376, v380
-    v382 = mul v371, v374
-    enable_side_effects u1 1
-    v383 = not v381
-    enable_side_effects v383
-    v385 = array_get v9, index u32 29 -> u8
-    v386 = eq v385, u8 0
-    v387 = not v386
-    v388 = mul v383, v387
-    enable_side_effects v388
-    constrain u1 0 == v388
-    v390 = not v388
-    v391 = mul v390, v381
-    v392 = unchecked_add v388, v391
-    v393 = mul v383, v386
-    enable_side_effects u1 1
-    v394 = not v392
-    enable_side_effects v394
-    v396 = array_get v9, index u32 30 -> u8
-    v397 = eq v396, u8 0
-    v398 = not v397
-    v399 = mul v394, v398
-    enable_side_effects v399
-    constrain u1 0 == v399
-    v400 = not v399
-    v401 = mul v400, v392
-    v402 = unchecked_add v399, v401
-    v403 = mul v394, v397
-    enable_side_effects u1 1
-    v404 = not v402
-    enable_side_effects v404
-    v406 = array_get v9, index u32 31 -> u8
-    v407 = eq v406, u8 1
-    v408 = not v407
-    v409 = mul v404, v408
-    enable_side_effects v409
-    v410 = eq v406, u8 0
-    v411 = cast v409 as u8
-    v412 = unchecked_mul v406, v411
-    constrain v412 == u8 0
-    v413 = not v409
-    v414 = mul v413, v402
-    v415 = unchecked_add v409, v414
-    v416 = mul v404, v407
-    enable_side_effects u1 1
-    constrain v415 == u1 1
-    v417 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v418 = allocate -> &mut u1
-    enable_side_effects u1 1
-    v419 = allocate -> &mut [u8; 32]
-    v420 = make_array [v43, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v421 = make_array [v43, v49, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v422 = make_array [v43, v49, v61, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v423 = make_array [v43, v49, v61, v73, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v424 = make_array [v43, v49, v61, v73, v85, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v425 = make_array [v43, v49, v61, v73, v85, v97, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v426 = make_array [v43, v49, v61, v73, v85, v97, v109, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v427 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v428 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v429 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v430 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v431 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v432 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v433 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v434 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v435 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v436 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v437 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v438 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v439 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v440 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v441 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v442 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v443 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v444 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v445 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v446 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v447 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v448 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, u8 0, u8 0, u8 0] : [u8; 32]
-    v449 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, u8 0, u8 0] : [u8; 32]
-    v450 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v396, u8 0] : [u8; 32]
-    v451 = make_array [v43, v49, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v396, v406] : [u8; 32]
-    v452 = allocate -> &mut Field
-    v453 = allocate -> &mut Field
-    v454 = allocate -> &mut Field
-    v455 = cast v217 as Field
-    v456 = cast v406 as Field
-    v457 = cast v205 as Field
-    v459 = mul v457, Field 256
-    v460 = add v455, v459
-    v461 = cast v396 as Field
-    v462 = mul v461, Field 256
-    v463 = add v456, v462
-    v464 = cast v193 as Field
-    v466 = mul v464, Field 65536
-    v467 = add v460, v466
-    v468 = cast v385 as Field
-    v469 = mul v468, Field 65536
-    v470 = add v463, v469
-    v471 = cast v181 as Field
-    v473 = mul v471, Field 16777216
-    v474 = add v467, v473
-    v475 = cast v373 as Field
-    v476 = mul v475, Field 16777216
-    v477 = add v470, v476
-    v478 = cast v169 as Field
-    v480 = mul v478, Field 4294967296
-    v481 = add v474, v480
-    v482 = cast v361 as Field
-    v483 = mul v482, Field 4294967296
-    v484 = add v477, v483
-    v485 = cast v157 as Field
-    v487 = mul v485, Field 1099511627776
-    v488 = add v481, v487
-    v489 = cast v349 as Field
-    v490 = mul v489, Field 1099511627776
-    v491 = add v484, v490
-    v492 = cast v145 as Field
-    v494 = mul v492, Field 281474976710656
-    v495 = add v488, v494
-    v496 = cast v337 as Field
-    v497 = mul v496, Field 281474976710656
-    v498 = add v491, v497
-    v499 = cast v133 as Field
-    v501 = mul v499, Field 72057594037927936
-    v502 = add v495, v501
-    v503 = cast v325 as Field
-    v504 = mul v503, Field 72057594037927936
-    v505 = add v498, v504
-    v506 = cast v121 as Field
-    v508 = mul v506, Field 18446744073709551616
-    v509 = add v502, v508
-    v510 = cast v313 as Field
-    v511 = mul v510, Field 18446744073709551616
-    v512 = add v505, v511
-    v513 = cast v109 as Field
-    v515 = mul v513, Field 4722366482869645213696
-    v516 = add v509, v515
-    v517 = cast v301 as Field
-    v518 = mul v517, Field 4722366482869645213696
-    v519 = add v512, v518
-    v520 = cast v97 as Field
-    v522 = mul v520, Field 1208925819614629174706176
-    v523 = add v516, v522
-    v524 = cast v289 as Field
-    v525 = mul v524, Field 1208925819614629174706176
-    v526 = add v519, v525
-    v527 = cast v85 as Field
-    v529 = mul v527, Field 309485009821345068724781056
-    v530 = add v523, v529
-    v531 = cast v277 as Field
-    v532 = mul v531, Field 309485009821345068724781056
-    v533 = add v526, v532
-    v534 = cast v73 as Field
-    v536 = mul v534, Field 79228162514264337593543950336
-    v537 = add v530, v536
-    v538 = cast v265 as Field
-    v539 = mul v538, Field 79228162514264337593543950336
-    v540 = add v533, v539
-    v541 = cast v61 as Field
-    v543 = mul v541, Field 20282409603651670423947251286016
-    v544 = add v537, v543
-    v545 = cast v253 as Field
-    v546 = mul v545, Field 20282409603651670423947251286016
-    v547 = add v540, v546
-    v548 = cast v49 as Field
-    v550 = mul v548, Field 5192296858534827628530496329220096
-    v551 = add v544, v550
-    v552 = cast v241 as Field
-    v553 = mul v552, Field 5192296858534827628530496329220096
-    v554 = add v547, v553
-    v555 = cast v43 as Field
-    v557 = mul v555, Field 1329227995784915872903807060280344576
-    v558 = add v551, v557
-    v559 = cast v229 as Field
-    v560 = mul v559, Field 1329227995784915872903807060280344576
-    v561 = add v554, v560
-    v563 = mul v558, Field 340282366920938463463374607431768211456
-    v564 = add v561, v563
-    v565 = allocate -> &mut Field
-    v567 = eq v4, Field 0
-    enable_side_effects v567
-    v568 = not v567
-    enable_side_effects v568
-    v570 = call f1(v4, Field 0) -> u1
-    v571 = mul v568, v570
-    enable_side_effects v571
-    v573, v574 = call f3(Field 0) -> (Field, Field)
-    v575 = cast v571 as Field
-    v576 = mul v573, v575
-    range_check v576 to 128 bits
-    v577 = mul v574, v575
-    range_check v577 to 128 bits
-    v578 = mul Field 340282366920938463463374607431768211456, v574
-    v579 = add v573, v578
-    v580 = eq Field 0, v579
-    v581 = mul v579, v575
-    constrain Field 0 == v581
-    v584 = call f2(Field 53438638232309528389504892708671455233, v573) -> u1
-    v585 = sub Field 53438638232309528389504892708671455233, v573
-    v587 = sub v585, Field 1
-    v588 = cast v584 as Field
-    v589 = mul v588, Field 340282366920938463463374607431768211456
-    v590 = add v587, v589
-    v592 = sub Field 64323764613183177041862057485226039389, v574
-    v593 = sub v592, v588
-    v594 = mul v590, v575
-    range_check v594 to 128 bits
-    v595 = mul v593, v575
-    range_check v595 to 128 bits
-    v597, v598 = call f3(v4) -> (Field, Field)
-    v599 = mul v597, v575
-    range_check v599 to 128 bits
-    v600 = mul v598, v575
-    range_check v600 to 128 bits
-    v601 = mul Field 340282366920938463463374607431768211456, v598
-    v602 = add v597, v601
-    v603 = eq v4, v602
-    v604 = mul v4, v575
-    v605 = mul v602, v575
-    constrain v604 == v605
-    v607 = call f2(Field 53438638232309528389504892708671455233, v597) -> u1
-    v608 = sub Field 53438638232309528389504892708671455233, v597
-    v609 = sub v608, Field 1
-    v610 = cast v607 as Field
-    v611 = mul v610, Field 340282366920938463463374607431768211456
-    v612 = add v609, v611
-    v613 = sub Field 64323764613183177041862057485226039389, v598
-    v614 = sub v613, v610
-    v615 = mul v612, v575
-    range_check v615 to 128 bits
-    v616 = mul v614, v575
-    range_check v616 to 128 bits
-    v618 = call f2(v573, v597) -> u1
-    v619 = sub v573, v597
-    v620 = sub v619, Field 1
-    v621 = cast v618 as Field
-    v622 = mul v621, Field 340282366920938463463374607431768211456
-    v623 = add v620, v622
-    v624 = sub v574, v598
-    v625 = sub v624, v621
-    v626 = mul v623, v575
-    range_check v626 to 128 bits
-    v627 = mul v625, v575
-    range_check v627 to 128 bits
-    v628 = not v570
-    v629 = mul v568, v628
-    enable_side_effects v629
-    v631, v632 = call f3(v4) -> (Field, Field)
-    v633 = cast v629 as Field
-    v634 = mul v631, v633
-    range_check v634 to 128 bits
-    v635 = mul v632, v633
-    range_check v635 to 128 bits
-    v636 = mul Field 340282366920938463463374607431768211456, v632
-    v637 = add v631, v636
-    v638 = eq v4, v637
-    v639 = mul v4, v633
-    v640 = mul v637, v633
-    constrain v639 == v640
-    v642 = call f2(Field 53438638232309528389504892708671455233, v631) -> u1
-    v643 = sub Field 53438638232309528389504892708671455233, v631
-    v644 = sub v643, Field 1
-    v645 = cast v642 as Field
-    v646 = mul v645, Field 340282366920938463463374607431768211456
-    v647 = add v644, v646
-    v648 = sub Field 64323764613183177041862057485226039389, v632
-    v649 = sub v648, v645
-    v650 = mul v647, v633
-    range_check v650 to 128 bits
-    v651 = mul v649, v633
-    range_check v651 to 128 bits
-    v653, v654 = call f3(Field 0) -> (Field, Field)
-    v655 = mul v653, v633
-    range_check v655 to 128 bits
-    v656 = mul v654, v633
-    range_check v656 to 128 bits
-    v657 = mul Field 340282366920938463463374607431768211456, v654
-    v658 = add v653, v657
-    v659 = eq Field 0, v658
-    v660 = mul v658, v633
-    constrain Field 0 == v660
-    v662 = call f2(Field 53438638232309528389504892708671455233, v653) -> u1
-    v663 = sub Field 53438638232309528389504892708671455233, v653
-    v664 = sub v663, Field 1
-    v665 = cast v662 as Field
-    v666 = mul v665, Field 340282366920938463463374607431768211456
-    v667 = add v664, v666
-    v668 = sub Field 64323764613183177041862057485226039389, v654
-    v669 = sub v668, v665
-    v670 = mul v667, v633
-    range_check v670 to 128 bits
-    v671 = mul v669, v633
-    range_check v671 to 128 bits
-    v673 = call f2(v631, v653) -> u1
-    v674 = sub v631, v653
-    v675 = sub v674, Field 1
-    v676 = cast v673 as Field
-    v677 = mul v676, Field 340282366920938463463374607431768211456
-    v678 = add v675, v677
-    v679 = sub v632, v654
-    v680 = sub v679, v676
-    v681 = mul v678, v633
-    range_check v681 to 128 bits
-    v682 = mul v680, v633
-    range_check v682 to 128 bits
-    enable_side_effects v629
-    v683 = not v629
-    v684 = cast v683 as Field
-    enable_side_effects u1 1
-    v685 = sub v633, v564
-    return v685
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After EnableSideEffectsIf removal:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = allocate -> &mut Field
-    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v40 = allocate -> &mut u1
-    v42 = array_get v9, index u32 0 -> u8
-    v43 = eq v42, u8 48
-    v44 = not v43
-    v45 = lt v42, u8 48
-    enable_side_effects v44
-    v46 = mul v45, v44
-    constrain v46 == v44
-    enable_side_effects v43
-    v48 = array_get v9, index u32 1 -> u8
-    v49 = eq v48, u8 100
-    v50 = not v49
-    v51 = mul v43, v50
-    v52 = lt v48, u8 100
-    enable_side_effects v51
-    v53 = mul v52, v51
-    constrain v53 == v51
-    v54 = not v51
-    v55 = mul v54, v44
-    v56 = unchecked_add v51, v55
-    v57 = mul v43, v49
-    enable_side_effects u1 1
-    v59 = not v56
-    enable_side_effects v59
-    v61 = array_get v9, index u32 2 -> u8
-    v62 = eq v61, u8 78
-    v63 = not v62
-    v64 = mul v59, v63
-    v65 = lt v61, u8 78
-    enable_side_effects v64
-    v66 = mul v65, v64
-    constrain v66 == v64
-    v67 = not v64
-    v68 = mul v67, v56
-    v69 = unchecked_add v64, v68
-    v70 = mul v59, v62
-    enable_side_effects u1 1
-    v71 = not v69
-    enable_side_effects v71
-    v73 = array_get v9, index u32 3 -> u8
-    v74 = eq v73, u8 114
-    v75 = not v74
-    v76 = mul v71, v75
-    v77 = lt v73, u8 114
-    enable_side_effects v76
-    v78 = mul v77, v76
-    constrain v78 == v76
-    v79 = not v76
-    v80 = mul v79, v69
-    v81 = unchecked_add v76, v80
-    v82 = mul v71, v74
-    enable_side_effects u1 1
-    v83 = not v81
-    enable_side_effects v83
-    v85 = array_get v9, index u32 4 -> u8
-    v86 = eq v85, u8 225
-    v87 = not v86
-    v88 = mul v83, v87
-    v89 = lt v85, u8 225
-    enable_side_effects v88
-    v90 = mul v89, v88
-    constrain v90 == v88
-    v91 = not v88
-    v92 = mul v91, v81
-    v93 = unchecked_add v88, v92
-    v94 = mul v83, v86
-    enable_side_effects u1 1
-    v95 = not v93
-    enable_side_effects v95
-    v97 = array_get v9, index u32 5 -> u8
-    v98 = eq v97, u8 49
-    v99 = not v98
-    v100 = mul v95, v99
-    v101 = lt v97, u8 49
-    enable_side_effects v100
-    v102 = mul v101, v100
-    constrain v102 == v100
-    v103 = not v100
-    v104 = mul v103, v93
-    v105 = unchecked_add v100, v104
-    v106 = mul v95, v98
-    enable_side_effects u1 1
-    v107 = not v105
-    enable_side_effects v107
-    v109 = array_get v9, index u32 6 -> u8
-    v110 = eq v109, u8 160
-    v111 = not v110
-    v112 = mul v107, v111
-    v113 = lt v109, u8 160
-    enable_side_effects v112
-    v114 = mul v113, v112
-    constrain v114 == v112
-    v115 = not v112
-    v116 = mul v115, v105
-    v117 = unchecked_add v112, v116
-    v118 = mul v107, v110
-    enable_side_effects u1 1
-    v119 = not v117
-    enable_side_effects v119
-    v121 = array_get v9, index u32 7 -> u8
-    v122 = eq v121, u8 41
-    v123 = not v122
-    v124 = mul v119, v123
-    v125 = lt v121, u8 41
-    enable_side_effects v124
-    v126 = mul v125, v124
-    constrain v126 == v124
-    v127 = not v124
-    v128 = mul v127, v117
-    v129 = unchecked_add v124, v128
-    v130 = mul v119, v122
-    enable_side_effects u1 1
-    v131 = not v129
-    enable_side_effects v131
-    v133 = array_get v9, index u32 8 -> u8
-    v134 = eq v133, u8 184
-    v135 = not v134
-    v136 = mul v131, v135
-    v137 = lt v133, u8 184
-    enable_side_effects v136
-    v138 = mul v137, v136
-    constrain v138 == v136
-    v139 = not v136
-    v140 = mul v139, v129
-    v141 = unchecked_add v136, v140
-    v142 = mul v131, v134
-    enable_side_effects u1 1
-    v143 = not v141
-    enable_side_effects v143
-    v145 = array_get v9, index u32 9 -> u8
-    v146 = eq v145, u8 80
-    v147 = not v146
-    v148 = mul v143, v147
-    v149 = lt v145, u8 80
-    enable_side_effects v148
-    v150 = mul v149, v148
-    constrain v150 == v148
-    v151 = not v148
-    v152 = mul v151, v141
-    v153 = unchecked_add v148, v152
-    v154 = mul v143, v146
-    enable_side_effects u1 1
-    v155 = not v153
-    enable_side_effects v155
-    v157 = array_get v9, index u32 10 -> u8
-    v158 = eq v157, u8 69
-    v159 = not v158
-    v160 = mul v155, v159
-    v161 = lt v157, u8 69
-    enable_side_effects v160
-    v162 = mul v161, v160
-    constrain v162 == v160
-    v163 = not v160
-    v164 = mul v163, v153
-    v165 = unchecked_add v160, v164
-    v166 = mul v155, v158
-    enable_side_effects u1 1
-    v167 = not v165
-    enable_side_effects v167
-    v169 = array_get v9, index u32 11 -> u8
-    v170 = eq v169, u8 182
-    v171 = not v170
-    v172 = mul v167, v171
-    v173 = lt v169, u8 182
-    enable_side_effects v172
-    v174 = mul v173, v172
-    constrain v174 == v172
-    v175 = not v172
-    v176 = mul v175, v165
-    v177 = unchecked_add v172, v176
-    v178 = mul v167, v170
-    enable_side_effects u1 1
-    v179 = not v177
-    enable_side_effects v179
-    v181 = array_get v9, index u32 12 -> u8
-    v182 = eq v181, u8 129
-    v183 = not v182
-    v184 = mul v179, v183
-    v185 = lt v181, u8 129
-    enable_side_effects v184
-    v186 = mul v185, v184
-    constrain v186 == v184
-    v187 = not v184
-    v188 = mul v187, v177
-    v189 = unchecked_add v184, v188
-    v190 = mul v179, v182
-    enable_side_effects u1 1
-    v191 = not v189
-    enable_side_effects v191
-    v193 = array_get v9, index u32 13 -> u8
-    v194 = eq v193, u8 129
-    v195 = not v194
-    v196 = mul v191, v195
-    v197 = lt v193, u8 129
-    enable_side_effects v196
-    v198 = mul v197, v196
-    constrain v198 == v196
-    v199 = not v196
-    v200 = mul v199, v189
-    v201 = unchecked_add v196, v200
-    v202 = mul v191, v194
-    enable_side_effects u1 1
-    v203 = not v201
-    enable_side_effects v203
-    v205 = array_get v9, index u32 14 -> u8
-    v206 = eq v205, u8 88
-    v207 = not v206
-    v208 = mul v203, v207
-    v209 = lt v205, u8 88
-    enable_side_effects v208
-    v210 = mul v209, v208
-    constrain v210 == v208
-    v211 = not v208
-    v212 = mul v211, v201
-    v213 = unchecked_add v208, v212
-    v214 = mul v203, v206
-    enable_side_effects u1 1
-    v215 = not v213
-    enable_side_effects v215
-    v217 = array_get v9, index u32 15 -> u8
-    v218 = eq v217, u8 93
-    v219 = not v218
-    v220 = mul v215, v219
-    v221 = lt v217, u8 93
-    enable_side_effects v220
-    v222 = mul v221, v220
-    constrain v222 == v220
-    v223 = not v220
-    v224 = mul v223, v213
-    v225 = unchecked_add v220, v224
-    v226 = mul v215, v218
-    enable_side_effects u1 1
-    v227 = not v225
-    enable_side_effects v227
-    v229 = array_get v9, index u32 16 -> u8
-    v230 = eq v229, u8 40
-    v231 = not v230
-    v232 = mul v227, v231
-    v233 = lt v229, u8 40
-    enable_side_effects v232
-    v234 = mul v233, v232
-    constrain v234 == v232
-    v235 = not v232
-    v236 = mul v235, v225
-    v237 = unchecked_add v232, v236
-    v238 = mul v227, v230
-    enable_side_effects u1 1
-    v239 = not v237
-    enable_side_effects v239
-    v241 = array_get v9, index u32 17 -> u8
-    v242 = eq v241, u8 51
-    v243 = not v242
-    v244 = mul v239, v243
-    v245 = lt v241, u8 51
-    enable_side_effects v244
-    v246 = mul v245, v244
-    constrain v246 == v244
-    v247 = not v244
-    v248 = mul v247, v237
-    v249 = unchecked_add v244, v248
-    v250 = mul v239, v242
-    enable_side_effects u1 1
-    v251 = not v249
-    enable_side_effects v251
-    v253 = array_get v9, index u32 18 -> u8
-    v254 = eq v253, u8 232
-    v255 = not v254
-    v256 = mul v251, v255
-    v257 = lt v253, u8 232
-    enable_side_effects v256
-    v258 = mul v257, v256
-    constrain v258 == v256
-    v259 = not v256
-    v260 = mul v259, v249
-    v261 = unchecked_add v256, v260
-    v262 = mul v251, v254
-    enable_side_effects u1 1
-    v263 = not v261
-    enable_side_effects v263
-    v265 = array_get v9, index u32 19 -> u8
-    v266 = eq v265, u8 72
-    v267 = not v266
-    v268 = mul v263, v267
-    v269 = lt v265, u8 72
-    enable_side_effects v268
-    v270 = mul v269, v268
-    constrain v270 == v268
-    v271 = not v268
-    v272 = mul v271, v261
-    v273 = unchecked_add v268, v272
-    v274 = mul v263, v266
-    enable_side_effects u1 1
-    v275 = not v273
-    enable_side_effects v275
-    v277 = array_get v9, index u32 20 -> u8
-    v278 = eq v277, u8 121
-    v279 = not v278
-    v280 = mul v275, v279
-    v281 = lt v277, u8 121
-    enable_side_effects v280
-    v282 = mul v281, v280
-    constrain v282 == v280
-    v283 = not v280
-    v284 = mul v283, v273
-    v285 = unchecked_add v280, v284
-    v286 = mul v275, v278
-    enable_side_effects u1 1
-    v287 = not v285
-    enable_side_effects v287
-    v289 = array_get v9, index u32 21 -> u8
-    v290 = eq v289, u8 185
-    v291 = not v290
-    v292 = mul v287, v291
-    v293 = lt v289, u8 185
-    enable_side_effects v292
-    v294 = mul v293, v292
-    constrain v294 == v292
-    v295 = not v292
-    v296 = mul v295, v285
-    v297 = unchecked_add v292, v296
-    v298 = mul v287, v290
-    enable_side_effects u1 1
-    v299 = not v297
-    enable_side_effects v299
-    v301 = array_get v9, index u32 22 -> u8
-    v302 = eq v301, u8 112
-    v303 = not v302
-    v304 = mul v299, v303
-    v305 = lt v301, u8 112
-    enable_side_effects v304
-    v306 = mul v305, v304
-    constrain v306 == v304
-    v307 = not v304
-    v308 = mul v307, v297
-    v309 = unchecked_add v304, v308
-    v310 = mul v299, v302
-    enable_side_effects u1 1
-    v311 = not v309
-    enable_side_effects v311
-    v313 = array_get v9, index u32 23 -> u8
-    v314 = eq v313, u8 145
-    v315 = not v314
-    v316 = mul v311, v315
-    v317 = lt v313, u8 145
-    enable_side_effects v316
-    v318 = mul v317, v316
-    constrain v318 == v316
-    v319 = not v316
-    v320 = mul v319, v309
-    v321 = unchecked_add v316, v320
-    v322 = mul v311, v314
-    enable_side_effects u1 1
-    v323 = not v321
-    enable_side_effects v323
-    v325 = array_get v9, index u32 24 -> u8
-    v326 = eq v325, u8 67
-    v327 = not v326
-    v328 = mul v323, v327
-    v329 = lt v325, u8 67
-    enable_side_effects v328
-    v330 = mul v329, v328
-    constrain v330 == v328
-    v331 = not v328
-    v332 = mul v331, v321
-    v333 = unchecked_add v328, v332
-    v334 = mul v323, v326
-    enable_side_effects u1 1
-    v335 = not v333
-    enable_side_effects v335
-    v337 = array_get v9, index u32 25 -> u8
-    v338 = eq v337, u8 225
-    v339 = not v338
-    v340 = mul v335, v339
-    v341 = lt v337, u8 225
-    enable_side_effects v340
-    v342 = mul v341, v340
-    constrain v342 == v340
-    v343 = not v340
-    v344 = mul v343, v333
-    v345 = unchecked_add v340, v344
-    v346 = mul v335, v338
-    enable_side_effects u1 1
-    v347 = not v345
-    enable_side_effects v347
-    v349 = array_get v9, index u32 26 -> u8
-    v350 = eq v349, u8 245
-    v351 = not v350
-    v352 = mul v347, v351
-    v353 = lt v349, u8 245
-    enable_side_effects v352
-    v354 = mul v353, v352
-    constrain v354 == v352
-    v355 = not v352
-    v356 = mul v355, v345
-    v357 = unchecked_add v352, v356
-    v358 = mul v347, v350
-    enable_side_effects u1 1
-    v359 = not v357
-    enable_side_effects v359
-    v361 = array_get v9, index u32 27 -> u8
-    v362 = eq v361, u8 147
-    v363 = not v362
-    v364 = mul v359, v363
-    v365 = lt v361, u8 147
-    enable_side_effects v364
-    v366 = mul v365, v364
-    constrain v366 == v364
-    v367 = not v364
-    v368 = mul v367, v357
-    v369 = unchecked_add v364, v368
-    v370 = mul v359, v362
-    enable_side_effects u1 1
-    v371 = not v369
-    enable_side_effects v371
-    v373 = array_get v9, index u32 28 -> u8
-    v374 = eq v373, u8 240
-    v375 = not v374
-    v376 = mul v371, v375
-    v377 = lt v373, u8 240
-    enable_side_effects v376
-    v378 = mul v377, v376
-    constrain v378 == v376
-    v379 = not v376
-    v380 = mul v379, v369
-    v381 = unchecked_add v376, v380
-    v382 = mul v371, v374
-    enable_side_effects u1 1
-    v383 = not v381
-    enable_side_effects v383
-    v385 = array_get v9, index u32 29 -> u8
-    v386 = eq v385, u8 0
-    v387 = not v386
-    v388 = mul v383, v387
-    constrain u1 0 == v388
-    v390 = not v388
-    enable_side_effects v388
-    v391 = mul v390, v381
-    v392 = unchecked_add v388, v391
-    v393 = mul v383, v386
-    enable_side_effects u1 1
-    v394 = not v392
-    enable_side_effects v394
-    v396 = array_get v9, index u32 30 -> u8
-    v397 = eq v396, u8 0
-    v398 = not v397
-    v399 = mul v394, v398
-    constrain u1 0 == v399
-    v400 = not v399
-    enable_side_effects v399
-    v401 = mul v400, v392
-    v402 = unchecked_add v399, v401
-    v403 = mul v394, v397
-    enable_side_effects u1 1
-    v404 = not v402
-    enable_side_effects v404
-    v406 = array_get v9, index u32 31 -> u8
-    v407 = eq v406, u8 1
-    v408 = not v407
-    v409 = mul v404, v408
-    v410 = eq v406, u8 0
-    v411 = cast v409 as u8
-    enable_side_effects v409
-    v412 = unchecked_mul v406, v411
-    constrain v412 == u8 0
-    v413 = not v409
-    v414 = mul v413, v402
-    v415 = unchecked_add v409, v414
-    v416 = mul v404, v407
-    enable_side_effects u1 1
-    constrain v415 == u1 1
-    v417 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v418 = allocate -> &mut u1
-    v419 = allocate -> &mut [u8; 32]
-    v420 = make_array [v42, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v421 = make_array [v42, v48, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v422 = make_array [v42, v48, v61, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v423 = make_array [v42, v48, v61, v73, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v424 = make_array [v42, v48, v61, v73, v85, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v425 = make_array [v42, v48, v61, v73, v85, v97, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v426 = make_array [v42, v48, v61, v73, v85, v97, v109, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v427 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v428 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v429 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v430 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v431 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v432 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v433 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v434 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v435 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v436 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v437 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v438 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v439 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v440 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v441 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v442 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v443 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v444 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v445 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v446 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v447 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v448 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, u8 0, u8 0, u8 0] : [u8; 32]
-    v449 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, u8 0, u8 0] : [u8; 32]
-    v450 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v396, u8 0] : [u8; 32]
-    v451 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v396, v406] : [u8; 32]
-    v452 = allocate -> &mut Field
-    v453 = allocate -> &mut Field
-    v454 = allocate -> &mut Field
-    v455 = cast v217 as Field
-    v456 = cast v406 as Field
-    v457 = cast v205 as Field
-    v459 = mul v457, Field 256
-    v460 = add v455, v459
-    v461 = cast v396 as Field
-    v462 = mul v461, Field 256
-    v463 = add v456, v462
-    v464 = cast v193 as Field
-    v466 = mul v464, Field 65536
-    v467 = add v460, v466
-    v468 = cast v385 as Field
-    v469 = mul v468, Field 65536
-    v470 = add v463, v469
-    v471 = cast v181 as Field
-    v473 = mul v471, Field 16777216
-    v474 = add v467, v473
-    v475 = cast v373 as Field
-    v476 = mul v475, Field 16777216
-    v477 = add v470, v476
-    v478 = cast v169 as Field
-    v480 = mul v478, Field 4294967296
-    v481 = add v474, v480
-    v482 = cast v361 as Field
-    v483 = mul v482, Field 4294967296
-    v484 = add v477, v483
-    v485 = cast v157 as Field
-    v487 = mul v485, Field 1099511627776
-    v488 = add v481, v487
-    v489 = cast v349 as Field
-    v490 = mul v489, Field 1099511627776
-    v491 = add v484, v490
-    v492 = cast v145 as Field
-    v494 = mul v492, Field 281474976710656
-    v495 = add v488, v494
-    v496 = cast v337 as Field
-    v497 = mul v496, Field 281474976710656
-    v498 = add v491, v497
-    v499 = cast v133 as Field
-    v501 = mul v499, Field 72057594037927936
-    v502 = add v495, v501
-    v503 = cast v325 as Field
-    v504 = mul v503, Field 72057594037927936
-    v505 = add v498, v504
-    v506 = cast v121 as Field
-    v508 = mul v506, Field 18446744073709551616
-    v509 = add v502, v508
-    v510 = cast v313 as Field
-    v511 = mul v510, Field 18446744073709551616
-    v512 = add v505, v511
-    v513 = cast v109 as Field
-    v515 = mul v513, Field 4722366482869645213696
-    v516 = add v509, v515
-    v517 = cast v301 as Field
-    v518 = mul v517, Field 4722366482869645213696
-    v519 = add v512, v518
-    v520 = cast v97 as Field
-    v522 = mul v520, Field 1208925819614629174706176
-    v523 = add v516, v522
-    v524 = cast v289 as Field
-    v525 = mul v524, Field 1208925819614629174706176
-    v526 = add v519, v525
-    v527 = cast v85 as Field
-    v529 = mul v527, Field 309485009821345068724781056
-    v530 = add v523, v529
-    v531 = cast v277 as Field
-    v532 = mul v531, Field 309485009821345068724781056
-    v533 = add v526, v532
-    v534 = cast v73 as Field
-    v536 = mul v534, Field 79228162514264337593543950336
-    v537 = add v530, v536
-    v538 = cast v265 as Field
-    v539 = mul v538, Field 79228162514264337593543950336
-    v540 = add v533, v539
-    v541 = cast v61 as Field
-    v543 = mul v541, Field 20282409603651670423947251286016
-    v544 = add v537, v543
-    v545 = cast v253 as Field
-    v546 = mul v545, Field 20282409603651670423947251286016
-    v547 = add v540, v546
-    v548 = cast v48 as Field
-    v550 = mul v548, Field 5192296858534827628530496329220096
-    v551 = add v544, v550
-    v552 = cast v241 as Field
-    v553 = mul v552, Field 5192296858534827628530496329220096
-    v554 = add v547, v553
-    v555 = cast v42 as Field
-    v557 = mul v555, Field 1329227995784915872903807060280344576
-    v558 = add v551, v557
-    v559 = cast v229 as Field
-    v560 = mul v559, Field 1329227995784915872903807060280344576
-    v561 = add v554, v560
-    v563 = mul v558, Field 340282366920938463463374607431768211456
-    v564 = add v561, v563
-    v565 = allocate -> &mut Field
-    v567 = eq v4, Field 0
-    v568 = not v567
-    enable_side_effects v568
-    v570 = call f1(v4, Field 0) -> u1
-    v571 = mul v568, v570
-    enable_side_effects v571
-    v573, v574 = call f3(Field 0) -> (Field, Field)
-    v575 = cast v571 as Field
-    v576 = mul v573, v575
-    range_check v576 to 128 bits
-    v577 = mul v574, v575
-    range_check v577 to 128 bits
-    v578 = mul Field 340282366920938463463374607431768211456, v574
-    v579 = add v573, v578
-    v580 = eq Field 0, v579
-    v581 = mul v579, v575
-    constrain Field 0 == v581
-    v584 = call f2(Field 53438638232309528389504892708671455233, v573) -> u1
-    v585 = sub Field 53438638232309528389504892708671455233, v573
-    v587 = sub v585, Field 1
-    v588 = cast v584 as Field
-    v589 = mul v588, Field 340282366920938463463374607431768211456
-    v590 = add v587, v589
-    v592 = sub Field 64323764613183177041862057485226039389, v574
-    v593 = sub v592, v588
-    v594 = mul v590, v575
-    range_check v594 to 128 bits
-    v595 = mul v593, v575
-    range_check v595 to 128 bits
-    v597, v598 = call f3(v4) -> (Field, Field)
-    v599 = mul v597, v575
-    range_check v599 to 128 bits
-    v600 = mul v598, v575
-    range_check v600 to 128 bits
-    v601 = mul Field 340282366920938463463374607431768211456, v598
-    v602 = add v597, v601
-    v603 = eq v4, v602
-    v604 = mul v4, v575
-    v605 = mul v602, v575
-    constrain v604 == v605
-    v607 = call f2(Field 53438638232309528389504892708671455233, v597) -> u1
-    v608 = sub Field 53438638232309528389504892708671455233, v597
-    v609 = sub v608, Field 1
-    v610 = cast v607 as Field
-    v611 = mul v610, Field 340282366920938463463374607431768211456
-    v612 = add v609, v611
-    v613 = sub Field 64323764613183177041862057485226039389, v598
-    v614 = sub v613, v610
-    v615 = mul v612, v575
-    range_check v615 to 128 bits
-    v616 = mul v614, v575
-    range_check v616 to 128 bits
-    v618 = call f2(v573, v597) -> u1
-    v619 = sub v573, v597
-    v620 = sub v619, Field 1
-    v621 = cast v618 as Field
-    v622 = mul v621, Field 340282366920938463463374607431768211456
-    v623 = add v620, v622
-    v624 = sub v574, v598
-    v625 = sub v624, v621
-    v626 = mul v623, v575
-    range_check v626 to 128 bits
-    v627 = mul v625, v575
-    range_check v627 to 128 bits
-    v628 = not v570
-    v629 = mul v568, v628
-    enable_side_effects v629
-    v631, v632 = call f3(v4) -> (Field, Field)
-    v633 = cast v629 as Field
-    v634 = mul v631, v633
-    range_check v634 to 128 bits
-    v635 = mul v632, v633
-    range_check v635 to 128 bits
-    v636 = mul Field 340282366920938463463374607431768211456, v632
-    v637 = add v631, v636
-    v638 = eq v4, v637
-    v639 = mul v4, v633
-    v640 = mul v637, v633
-    constrain v639 == v640
-    v642 = call f2(Field 53438638232309528389504892708671455233, v631) -> u1
-    v643 = sub Field 53438638232309528389504892708671455233, v631
-    v644 = sub v643, Field 1
-    v645 = cast v642 as Field
-    v646 = mul v645, Field 340282366920938463463374607431768211456
-    v647 = add v644, v646
-    v648 = sub Field 64323764613183177041862057485226039389, v632
-    v649 = sub v648, v645
-    v650 = mul v647, v633
-    range_check v650 to 128 bits
-    v651 = mul v649, v633
-    range_check v651 to 128 bits
-    v653, v654 = call f3(Field 0) -> (Field, Field)
-    v655 = mul v653, v633
-    range_check v655 to 128 bits
-    v656 = mul v654, v633
-    range_check v656 to 128 bits
-    v657 = mul Field 340282366920938463463374607431768211456, v654
-    v658 = add v653, v657
-    v659 = eq Field 0, v658
-    v660 = mul v658, v633
-    constrain Field 0 == v660
-    v662 = call f2(Field 53438638232309528389504892708671455233, v653) -> u1
-    v663 = sub Field 53438638232309528389504892708671455233, v653
-    v664 = sub v663, Field 1
-    v665 = cast v662 as Field
-    v666 = mul v665, Field 340282366920938463463374607431768211456
-    v667 = add v664, v666
-    v668 = sub Field 64323764613183177041862057485226039389, v654
-    v669 = sub v668, v665
-    v670 = mul v667, v633
-    range_check v670 to 128 bits
-    v671 = mul v669, v633
-    range_check v671 to 128 bits
-    v673 = call f2(v631, v653) -> u1
-    v674 = sub v631, v653
-    v675 = sub v674, Field 1
-    v676 = cast v673 as Field
-    v677 = mul v676, Field 340282366920938463463374607431768211456
-    v678 = add v675, v677
-    v679 = sub v632, v654
-    v680 = sub v679, v676
-    v681 = mul v678, v633
-    range_check v681 to 128 bits
-    v682 = mul v680, v633
-    range_check v682 to 128 bits
-    v683 = not v629
-    v684 = cast v683 as Field
-    enable_side_effects u1 1
-    v685 = sub v633, v564
-    return v685
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Constraint Folding:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = allocate -> &mut Field
-    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v40 = allocate -> &mut u1
-    v42 = array_get v9, index u32 0 -> u8
-    v43 = eq v42, u8 48
-    v44 = not v43
-    v45 = lt v42, u8 48
-    enable_side_effects v44
-    v46 = mul v45, v44
-    constrain v46 == v44
-    enable_side_effects v43
-    v48 = array_get v9, index u32 1 -> u8
-    v49 = eq v48, u8 100
-    v50 = not v49
-    v51 = mul v43, v50
-    v52 = lt v48, u8 100
-    enable_side_effects v51
-    v53 = mul v52, v51
-    constrain v53 == v51
-    v54 = not v51
-    v55 = mul v54, v44
-    v56 = unchecked_add v51, v55
-    v57 = mul v43, v49
-    enable_side_effects u1 1
-    v59 = not v56
-    enable_side_effects v59
-    v61 = array_get v9, index u32 2 -> u8
-    v62 = eq v61, u8 78
-    v63 = not v62
-    v64 = mul v59, v63
-    v65 = lt v61, u8 78
-    enable_side_effects v64
-    v66 = mul v65, v64
-    constrain v66 == v64
-    v67 = not v64
-    v68 = mul v67, v56
-    v69 = unchecked_add v64, v68
-    v70 = mul v59, v62
-    enable_side_effects u1 1
-    v71 = not v69
-    enable_side_effects v71
-    v73 = array_get v9, index u32 3 -> u8
-    v74 = eq v73, u8 114
-    v75 = not v74
-    v76 = mul v71, v75
-    v77 = lt v73, u8 114
-    enable_side_effects v76
-    v78 = mul v77, v76
-    constrain v78 == v76
-    v79 = not v76
-    v80 = mul v79, v69
-    v81 = unchecked_add v76, v80
-    v82 = mul v71, v74
-    enable_side_effects u1 1
-    v83 = not v81
-    enable_side_effects v83
-    v85 = array_get v9, index u32 4 -> u8
-    v86 = eq v85, u8 225
-    v87 = not v86
-    v88 = mul v83, v87
-    v89 = lt v85, u8 225
-    enable_side_effects v88
-    v90 = mul v89, v88
-    constrain v90 == v88
-    v91 = not v88
-    v92 = mul v91, v81
-    v93 = unchecked_add v88, v92
-    v94 = mul v83, v86
-    enable_side_effects u1 1
-    v95 = not v93
-    enable_side_effects v95
-    v97 = array_get v9, index u32 5 -> u8
-    v98 = eq v97, u8 49
-    v99 = not v98
-    v100 = mul v95, v99
-    v101 = lt v97, u8 49
-    enable_side_effects v100
-    v102 = mul v101, v100
-    constrain v102 == v100
-    v103 = not v100
-    v104 = mul v103, v93
-    v105 = unchecked_add v100, v104
-    v106 = mul v95, v98
-    enable_side_effects u1 1
-    v107 = not v105
-    enable_side_effects v107
-    v109 = array_get v9, index u32 6 -> u8
-    v110 = eq v109, u8 160
-    v111 = not v110
-    v112 = mul v107, v111
-    v113 = lt v109, u8 160
-    enable_side_effects v112
-    v114 = mul v113, v112
-    constrain v114 == v112
-    v115 = not v112
-    v116 = mul v115, v105
-    v117 = unchecked_add v112, v116
-    v118 = mul v107, v110
-    enable_side_effects u1 1
-    v119 = not v117
-    enable_side_effects v119
-    v121 = array_get v9, index u32 7 -> u8
-    v122 = eq v121, u8 41
-    v123 = not v122
-    v124 = mul v119, v123
-    v125 = lt v121, u8 41
-    enable_side_effects v124
-    v126 = mul v125, v124
-    constrain v126 == v124
-    v127 = not v124
-    v128 = mul v127, v117
-    v129 = unchecked_add v124, v128
-    v130 = mul v119, v122
-    enable_side_effects u1 1
-    v131 = not v129
-    enable_side_effects v131
-    v133 = array_get v9, index u32 8 -> u8
-    v134 = eq v133, u8 184
-    v135 = not v134
-    v136 = mul v131, v135
-    v137 = lt v133, u8 184
-    enable_side_effects v136
-    v138 = mul v137, v136
-    constrain v138 == v136
-    v139 = not v136
-    v140 = mul v139, v129
-    v141 = unchecked_add v136, v140
-    v142 = mul v131, v134
-    enable_side_effects u1 1
-    v143 = not v141
-    enable_side_effects v143
-    v145 = array_get v9, index u32 9 -> u8
-    v146 = eq v145, u8 80
-    v147 = not v146
-    v148 = mul v143, v147
-    v149 = lt v145, u8 80
-    enable_side_effects v148
-    v150 = mul v149, v148
-    constrain v150 == v148
-    v151 = not v148
-    v152 = mul v151, v141
-    v153 = unchecked_add v148, v152
-    v154 = mul v143, v146
-    enable_side_effects u1 1
-    v155 = not v153
-    enable_side_effects v155
-    v157 = array_get v9, index u32 10 -> u8
-    v158 = eq v157, u8 69
-    v159 = not v158
-    v160 = mul v155, v159
-    v161 = lt v157, u8 69
-    enable_side_effects v160
-    v162 = mul v161, v160
-    constrain v162 == v160
-    v163 = not v160
-    v164 = mul v163, v153
-    v165 = unchecked_add v160, v164
-    v166 = mul v155, v158
-    enable_side_effects u1 1
-    v167 = not v165
-    enable_side_effects v167
-    v169 = array_get v9, index u32 11 -> u8
-    v170 = eq v169, u8 182
-    v171 = not v170
-    v172 = mul v167, v171
-    v173 = lt v169, u8 182
-    enable_side_effects v172
-    v174 = mul v173, v172
-    constrain v174 == v172
-    v175 = not v172
-    v176 = mul v175, v165
-    v177 = unchecked_add v172, v176
-    v178 = mul v167, v170
-    enable_side_effects u1 1
-    v179 = not v177
-    enable_side_effects v179
-    v181 = array_get v9, index u32 12 -> u8
-    v182 = eq v181, u8 129
-    v183 = not v182
-    v184 = mul v179, v183
-    v185 = lt v181, u8 129
-    enable_side_effects v184
-    v186 = mul v185, v184
-    constrain v186 == v184
-    v187 = not v184
-    v188 = mul v187, v177
-    v189 = unchecked_add v184, v188
-    v190 = mul v179, v182
-    enable_side_effects u1 1
-    v191 = not v189
-    enable_side_effects v191
-    v193 = array_get v9, index u32 13 -> u8
-    v194 = eq v193, u8 129
-    v195 = not v194
-    v196 = mul v191, v195
-    v197 = lt v193, u8 129
-    enable_side_effects v196
-    v198 = mul v197, v196
-    constrain v198 == v196
-    v199 = not v196
-    v200 = mul v199, v189
-    v201 = unchecked_add v196, v200
-    v202 = mul v191, v194
-    enable_side_effects u1 1
-    v203 = not v201
-    enable_side_effects v203
-    v205 = array_get v9, index u32 14 -> u8
-    v206 = eq v205, u8 88
-    v207 = not v206
-    v208 = mul v203, v207
-    v209 = lt v205, u8 88
-    enable_side_effects v208
-    v210 = mul v209, v208
-    constrain v210 == v208
-    v211 = not v208
-    v212 = mul v211, v201
-    v213 = unchecked_add v208, v212
-    v214 = mul v203, v206
-    enable_side_effects u1 1
-    v215 = not v213
-    enable_side_effects v215
-    v217 = array_get v9, index u32 15 -> u8
-    v218 = eq v217, u8 93
-    v219 = not v218
-    v220 = mul v215, v219
-    v221 = lt v217, u8 93
-    enable_side_effects v220
-    v222 = mul v221, v220
-    constrain v222 == v220
-    v223 = not v220
-    v224 = mul v223, v213
-    v225 = unchecked_add v220, v224
-    v226 = mul v215, v218
-    enable_side_effects u1 1
-    v227 = not v225
-    enable_side_effects v227
-    v229 = array_get v9, index u32 16 -> u8
-    v230 = eq v229, u8 40
-    v231 = not v230
-    v232 = mul v227, v231
-    v233 = lt v229, u8 40
-    enable_side_effects v232
-    v234 = mul v233, v232
-    constrain v234 == v232
-    v235 = not v232
-    v236 = mul v235, v225
-    v237 = unchecked_add v232, v236
-    v238 = mul v227, v230
-    enable_side_effects u1 1
-    v239 = not v237
-    enable_side_effects v239
-    v241 = array_get v9, index u32 17 -> u8
-    v242 = eq v241, u8 51
-    v243 = not v242
-    v244 = mul v239, v243
-    v245 = lt v241, u8 51
-    enable_side_effects v244
-    v246 = mul v245, v244
-    constrain v246 == v244
-    v247 = not v244
-    v248 = mul v247, v237
-    v249 = unchecked_add v244, v248
-    v250 = mul v239, v242
-    enable_side_effects u1 1
-    v251 = not v249
-    enable_side_effects v251
-    v253 = array_get v9, index u32 18 -> u8
-    v254 = eq v253, u8 232
-    v255 = not v254
-    v256 = mul v251, v255
-    v257 = lt v253, u8 232
-    enable_side_effects v256
-    v258 = mul v257, v256
-    constrain v258 == v256
-    v259 = not v256
-    v260 = mul v259, v249
-    v261 = unchecked_add v256, v260
-    v262 = mul v251, v254
-    enable_side_effects u1 1
-    v263 = not v261
-    enable_side_effects v263
-    v265 = array_get v9, index u32 19 -> u8
-    v266 = eq v265, u8 72
-    v267 = not v266
-    v268 = mul v263, v267
-    v269 = lt v265, u8 72
-    enable_side_effects v268
-    v270 = mul v269, v268
-    constrain v270 == v268
-    v271 = not v268
-    v272 = mul v271, v261
-    v273 = unchecked_add v268, v272
-    v274 = mul v263, v266
-    enable_side_effects u1 1
-    v275 = not v273
-    enable_side_effects v275
-    v277 = array_get v9, index u32 20 -> u8
-    v278 = eq v277, u8 121
-    v279 = not v278
-    v280 = mul v275, v279
-    v281 = lt v277, u8 121
-    enable_side_effects v280
-    v282 = mul v281, v280
-    constrain v282 == v280
-    v283 = not v280
-    v284 = mul v283, v273
-    v285 = unchecked_add v280, v284
-    v286 = mul v275, v278
-    enable_side_effects u1 1
-    v287 = not v285
-    enable_side_effects v287
-    v289 = array_get v9, index u32 21 -> u8
-    v290 = eq v289, u8 185
-    v291 = not v290
-    v292 = mul v287, v291
-    v293 = lt v289, u8 185
-    enable_side_effects v292
-    v294 = mul v293, v292
-    constrain v294 == v292
-    v295 = not v292
-    v296 = mul v295, v285
-    v297 = unchecked_add v292, v296
-    v298 = mul v287, v290
-    enable_side_effects u1 1
-    v299 = not v297
-    enable_side_effects v299
-    v301 = array_get v9, index u32 22 -> u8
-    v302 = eq v301, u8 112
-    v303 = not v302
-    v304 = mul v299, v303
-    v305 = lt v301, u8 112
-    enable_side_effects v304
-    v306 = mul v305, v304
-    constrain v306 == v304
-    v307 = not v304
-    v308 = mul v307, v297
-    v309 = unchecked_add v304, v308
-    v310 = mul v299, v302
-    enable_side_effects u1 1
-    v311 = not v309
-    enable_side_effects v311
-    v313 = array_get v9, index u32 23 -> u8
-    v314 = eq v313, u8 145
-    v315 = not v314
-    v316 = mul v311, v315
-    v317 = lt v313, u8 145
-    enable_side_effects v316
-    v318 = mul v317, v316
-    constrain v318 == v316
-    v319 = not v316
-    v320 = mul v319, v309
-    v321 = unchecked_add v316, v320
-    v322 = mul v311, v314
-    enable_side_effects u1 1
-    v323 = not v321
-    enable_side_effects v323
-    v325 = array_get v9, index u32 24 -> u8
-    v326 = eq v325, u8 67
-    v327 = not v326
-    v328 = mul v323, v327
-    v329 = lt v325, u8 67
-    enable_side_effects v328
-    v330 = mul v329, v328
-    constrain v330 == v328
-    v331 = not v328
-    v332 = mul v331, v321
-    v333 = unchecked_add v328, v332
-    v334 = mul v323, v326
-    enable_side_effects u1 1
-    v335 = not v333
-    enable_side_effects v335
-    v337 = array_get v9, index u32 25 -> u8
-    v338 = eq v337, u8 225
-    v339 = not v338
-    v340 = mul v335, v339
-    v341 = lt v337, u8 225
-    enable_side_effects v340
-    v342 = mul v341, v340
-    constrain v342 == v340
-    v343 = not v340
-    v344 = mul v343, v333
-    v345 = unchecked_add v340, v344
-    v346 = mul v335, v338
-    enable_side_effects u1 1
-    v347 = not v345
-    enable_side_effects v347
-    v349 = array_get v9, index u32 26 -> u8
-    v350 = eq v349, u8 245
-    v351 = not v350
-    v352 = mul v347, v351
-    v353 = lt v349, u8 245
-    enable_side_effects v352
-    v354 = mul v353, v352
-    constrain v354 == v352
-    v355 = not v352
-    v356 = mul v355, v345
-    v357 = unchecked_add v352, v356
-    v358 = mul v347, v350
-    enable_side_effects u1 1
-    v359 = not v357
-    enable_side_effects v359
-    v361 = array_get v9, index u32 27 -> u8
-    v362 = eq v361, u8 147
-    v363 = not v362
-    v364 = mul v359, v363
-    v365 = lt v361, u8 147
-    enable_side_effects v364
-    v366 = mul v365, v364
-    constrain v366 == v364
-    v367 = not v364
-    v368 = mul v367, v357
-    v369 = unchecked_add v364, v368
-    v370 = mul v359, v362
-    enable_side_effects u1 1
-    v371 = not v369
-    enable_side_effects v371
-    v373 = array_get v9, index u32 28 -> u8
-    v374 = eq v373, u8 240
-    v375 = not v374
-    v376 = mul v371, v375
-    v377 = lt v373, u8 240
-    enable_side_effects v376
-    v378 = mul v377, v376
-    constrain v378 == v376
-    v379 = not v376
-    v380 = mul v379, v369
-    v381 = unchecked_add v376, v380
-    v382 = mul v371, v374
-    enable_side_effects u1 1
-    v383 = not v381
-    enable_side_effects v383
-    v385 = array_get v9, index u32 29 -> u8
-    v386 = eq v385, u8 0
-    v387 = not v386
-    v388 = mul v383, v387
-    constrain u1 0 == v388
-    enable_side_effects u1 0
-    v390 = unchecked_add v388, v381
-    v391 = mul v383, v386
-    enable_side_effects u1 1
-    v392 = not v390
-    enable_side_effects v392
-    v394 = array_get v9, index u32 30 -> u8
-    v395 = eq v394, u8 0
-    v396 = not v395
-    v397 = mul v392, v396
-    constrain u1 0 == v397
-    enable_side_effects u1 0
-    v398 = unchecked_add v397, v390
-    v399 = mul v392, v395
-    enable_side_effects u1 1
-    v400 = not v398
-    enable_side_effects v400
-    v402 = array_get v9, index u32 31 -> u8
-    v403 = eq v402, u8 1
-    v404 = not v403
-    v405 = mul v400, v404
-    v406 = eq v402, u8 0
-    v407 = cast v405 as u8
-    enable_side_effects v405
-    v408 = unchecked_mul v402, v407
-    constrain v408 == u8 0
-    v409 = not v405
-    v410 = mul v409, v398
-    v411 = unchecked_add v405, v410
-    v412 = mul v400, v403
-    enable_side_effects u1 1
-    constrain v411 == u1 1
-    v413 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v414 = allocate -> &mut u1
-    v415 = allocate -> &mut [u8; 32]
-    v416 = make_array [v42, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v417 = make_array [v42, v48, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v418 = make_array [v42, v48, v61, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v419 = make_array [v42, v48, v61, v73, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v420 = make_array [v42, v48, v61, v73, v85, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v421 = make_array [v42, v48, v61, v73, v85, v97, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v422 = make_array [v42, v48, v61, v73, v85, v97, v109, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v423 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v424 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v425 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v426 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v427 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v428 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v429 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v430 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v431 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v432 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v433 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v434 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v435 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v436 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v437 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v438 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v439 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v440 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v441 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v442 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v443 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v444 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, u8 0, u8 0, u8 0] : [u8; 32]
-    v445 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, u8 0, u8 0] : [u8; 32]
-    v446 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v394, u8 0] : [u8; 32]
-    v447 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v394, v402] : [u8; 32]
-    v448 = allocate -> &mut Field
-    v449 = allocate -> &mut Field
-    v450 = allocate -> &mut Field
-    v451 = cast v217 as Field
-    v452 = cast v402 as Field
-    v453 = cast v205 as Field
-    v455 = mul v453, Field 256
-    v456 = add v451, v455
-    v457 = cast v394 as Field
-    v458 = mul v457, Field 256
-    v459 = add v452, v458
-    v460 = cast v193 as Field
-    v462 = mul v460, Field 65536
-    v463 = add v456, v462
-    v464 = cast v385 as Field
-    v465 = mul v464, Field 65536
-    v466 = add v459, v465
-    v467 = cast v181 as Field
-    v469 = mul v467, Field 16777216
-    v470 = add v463, v469
-    v471 = cast v373 as Field
-    v472 = mul v471, Field 16777216
-    v473 = add v466, v472
-    v474 = cast v169 as Field
-    v476 = mul v474, Field 4294967296
-    v477 = add v470, v476
-    v478 = cast v361 as Field
-    v479 = mul v478, Field 4294967296
-    v480 = add v473, v479
-    v481 = cast v157 as Field
-    v483 = mul v481, Field 1099511627776
-    v484 = add v477, v483
-    v485 = cast v349 as Field
-    v486 = mul v485, Field 1099511627776
-    v487 = add v480, v486
-    v488 = cast v145 as Field
-    v490 = mul v488, Field 281474976710656
-    v491 = add v484, v490
-    v492 = cast v337 as Field
-    v493 = mul v492, Field 281474976710656
-    v494 = add v487, v493
-    v495 = cast v133 as Field
-    v497 = mul v495, Field 72057594037927936
-    v498 = add v491, v497
-    v499 = cast v325 as Field
-    v500 = mul v499, Field 72057594037927936
-    v501 = add v494, v500
-    v502 = cast v121 as Field
-    v504 = mul v502, Field 18446744073709551616
-    v505 = add v498, v504
-    v506 = cast v313 as Field
-    v507 = mul v506, Field 18446744073709551616
-    v508 = add v501, v507
-    v509 = cast v109 as Field
-    v511 = mul v509, Field 4722366482869645213696
-    v512 = add v505, v511
-    v513 = cast v301 as Field
-    v514 = mul v513, Field 4722366482869645213696
-    v515 = add v508, v514
-    v516 = cast v97 as Field
-    v518 = mul v516, Field 1208925819614629174706176
-    v519 = add v512, v518
-    v520 = cast v289 as Field
-    v521 = mul v520, Field 1208925819614629174706176
-    v522 = add v515, v521
-    v523 = cast v85 as Field
-    v525 = mul v523, Field 309485009821345068724781056
-    v526 = add v519, v525
-    v527 = cast v277 as Field
-    v528 = mul v527, Field 309485009821345068724781056
-    v529 = add v522, v528
-    v530 = cast v73 as Field
-    v532 = mul v530, Field 79228162514264337593543950336
-    v533 = add v526, v532
-    v534 = cast v265 as Field
-    v535 = mul v534, Field 79228162514264337593543950336
-    v536 = add v529, v535
-    v537 = cast v61 as Field
-    v539 = mul v537, Field 20282409603651670423947251286016
-    v540 = add v533, v539
-    v541 = cast v253 as Field
-    v542 = mul v541, Field 20282409603651670423947251286016
-    v543 = add v536, v542
-    v544 = cast v48 as Field
-    v546 = mul v544, Field 5192296858534827628530496329220096
-    v547 = add v540, v546
-    v548 = cast v241 as Field
-    v549 = mul v548, Field 5192296858534827628530496329220096
-    v550 = add v543, v549
-    v551 = cast v42 as Field
-    v553 = mul v551, Field 1329227995784915872903807060280344576
-    v554 = add v547, v553
-    v555 = cast v229 as Field
-    v556 = mul v555, Field 1329227995784915872903807060280344576
-    v557 = add v550, v556
-    v559 = mul v554, Field 340282366920938463463374607431768211456
-    v560 = add v557, v559
-    v561 = allocate -> &mut Field
-    v563 = eq v4, Field 0
-    v564 = not v563
-    enable_side_effects v564
-    v566 = call f1(v4, Field 0) -> u1
-    v567 = mul v564, v566
-    enable_side_effects v567
-    v569, v570 = call f3(Field 0) -> (Field, Field)
-    v571 = cast v567 as Field
-    v572 = mul v569, v571
-    range_check v572 to 128 bits
-    v573 = mul v570, v571
-    range_check v573 to 128 bits
-    v574 = mul Field 340282366920938463463374607431768211456, v570
-    v575 = add v569, v574
-    v576 = eq Field 0, v575
-    v577 = mul v575, v571
-    constrain Field 0 == v577
-    v580 = call f2(Field 53438638232309528389504892708671455233, v569) -> u1
-    v581 = sub Field 53438638232309528389504892708671455233, v569
-    v583 = sub v581, Field 1
-    v584 = cast v580 as Field
-    v585 = mul v584, Field 340282366920938463463374607431768211456
-    v586 = add v583, v585
-    v588 = sub Field 64323764613183177041862057485226039389, v570
-    v589 = sub v588, v584
-    v590 = mul v586, v571
-    range_check v590 to 128 bits
-    v591 = mul v589, v571
-    range_check v591 to 128 bits
-    v593, v594 = call f3(v4) -> (Field, Field)
-    v595 = mul v593, v571
-    range_check v595 to 128 bits
-    v596 = mul v594, v571
-    range_check v596 to 128 bits
-    v597 = mul Field 340282366920938463463374607431768211456, v594
-    v598 = add v593, v597
-    v599 = eq v4, v598
-    v600 = mul v4, v571
-    v601 = mul v598, v571
-    constrain v600 == v601
-    v603 = call f2(Field 53438638232309528389504892708671455233, v593) -> u1
-    v604 = sub Field 53438638232309528389504892708671455233, v593
-    v605 = sub v604, Field 1
-    v606 = cast v603 as Field
-    v607 = mul v606, Field 340282366920938463463374607431768211456
-    v608 = add v605, v607
-    v609 = sub Field 64323764613183177041862057485226039389, v594
-    v610 = sub v609, v606
-    v611 = mul v608, v571
-    range_check v611 to 128 bits
-    v612 = mul v610, v571
-    range_check v612 to 128 bits
-    v614 = call f2(v569, v593) -> u1
-    v615 = sub v569, v593
-    v616 = sub v615, Field 1
-    v617 = cast v614 as Field
-    v618 = mul v617, Field 340282366920938463463374607431768211456
-    v619 = add v616, v618
-    v620 = sub v570, v594
-    v621 = sub v620, v617
-    v622 = mul v619, v571
-    range_check v622 to 128 bits
-    v623 = mul v621, v571
-    range_check v623 to 128 bits
-    v624 = not v566
-    v625 = mul v564, v624
-    enable_side_effects v625
-    v627, v628 = call f3(v4) -> (Field, Field)
-    v629 = cast v625 as Field
-    v630 = mul v627, v629
-    range_check v630 to 128 bits
-    v631 = mul v628, v629
-    range_check v631 to 128 bits
-    v632 = mul Field 340282366920938463463374607431768211456, v628
-    v633 = add v627, v632
-    v634 = eq v4, v633
-    v635 = mul v4, v629
-    v636 = mul v633, v629
-    constrain v635 == v636
-    v638 = call f2(Field 53438638232309528389504892708671455233, v627) -> u1
-    v639 = sub Field 53438638232309528389504892708671455233, v627
-    v640 = sub v639, Field 1
-    v641 = cast v638 as Field
-    v642 = mul v641, Field 340282366920938463463374607431768211456
-    v643 = add v640, v642
-    v644 = sub Field 64323764613183177041862057485226039389, v628
-    v645 = sub v644, v641
-    v646 = mul v643, v629
-    range_check v646 to 128 bits
-    v647 = mul v645, v629
-    range_check v647 to 128 bits
-    v649, v650 = call f3(Field 0) -> (Field, Field)
-    v651 = mul v649, v629
-    range_check v651 to 128 bits
-    v652 = mul v650, v629
-    range_check v652 to 128 bits
-    v653 = mul Field 340282366920938463463374607431768211456, v650
-    v654 = add v649, v653
-    v655 = eq Field 0, v654
-    v656 = mul v654, v629
-    constrain Field 0 == v656
-    v658 = call f2(Field 53438638232309528389504892708671455233, v649) -> u1
-    v659 = sub Field 53438638232309528389504892708671455233, v649
-    v660 = sub v659, Field 1
-    v661 = cast v658 as Field
-    v662 = mul v661, Field 340282366920938463463374607431768211456
-    v663 = add v660, v662
-    v664 = sub Field 64323764613183177041862057485226039389, v650
-    v665 = sub v664, v661
-    v666 = mul v663, v629
-    range_check v666 to 128 bits
-    v667 = mul v665, v629
-    range_check v667 to 128 bits
-    v669 = call f2(v627, v649) -> u1
-    v670 = sub v627, v649
-    v671 = sub v670, Field 1
-    v672 = cast v669 as Field
-    v673 = mul v672, Field 340282366920938463463374607431768211456
-    v674 = add v671, v673
-    v675 = sub v628, v650
-    v676 = sub v675, v672
-    v677 = mul v674, v629
-    range_check v677 to 128 bits
-    v678 = mul v676, v629
-    range_check v678 to 128 bits
-    v679 = not v625
-    v680 = cast v679 as Field
-    enable_side_effects u1 1
-    v681 = sub v629, v560
-    return v681
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Adding constrain not equal:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = allocate -> &mut Field
-    v9 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v39 = make_array [u8 48, u8 100, u8 78, u8 114, u8 225, u8 49, u8 160, u8 41, u8 184, u8 80, u8 69, u8 182, u8 129, u8 129, u8 88, u8 93, u8 40, u8 51, u8 232, u8 72, u8 121, u8 185, u8 112, u8 145, u8 67, u8 225, u8 245, u8 147, u8 240, u8 0, u8 0, u8 1] : [u8]
-    v40 = allocate -> &mut u1
-    v42 = array_get v9, index u32 0 -> u8
-    v43 = eq v42, u8 48
-    v44 = not v43
-    v45 = lt v42, u8 48
-    enable_side_effects v44
-    v46 = mul v45, v44
-    constrain v46 == v44
-    enable_side_effects v43
-    v48 = array_get v9, index u32 1 -> u8
-    v49 = eq v48, u8 100
-    v50 = not v49
-    v51 = mul v43, v50
-    v52 = lt v48, u8 100
-    enable_side_effects v51
-    v53 = mul v52, v51
-    constrain v53 == v51
-    v54 = not v51
-    v55 = mul v54, v44
-    v56 = unchecked_add v51, v55
-    v57 = mul v43, v49
-    enable_side_effects u1 1
-    v59 = not v56
-    enable_side_effects v59
-    v61 = array_get v9, index u32 2 -> u8
-    v62 = eq v61, u8 78
-    v63 = not v62
-    v64 = mul v59, v63
-    v65 = lt v61, u8 78
-    enable_side_effects v64
-    v66 = mul v65, v64
-    constrain v66 == v64
-    v67 = not v64
-    v68 = mul v67, v56
-    v69 = unchecked_add v64, v68
-    v70 = mul v59, v62
-    enable_side_effects u1 1
-    v71 = not v69
-    enable_side_effects v71
-    v73 = array_get v9, index u32 3 -> u8
-    v74 = eq v73, u8 114
-    v75 = not v74
-    v76 = mul v71, v75
-    v77 = lt v73, u8 114
-    enable_side_effects v76
-    v78 = mul v77, v76
-    constrain v78 == v76
-    v79 = not v76
-    v80 = mul v79, v69
-    v81 = unchecked_add v76, v80
-    v82 = mul v71, v74
-    enable_side_effects u1 1
-    v83 = not v81
-    enable_side_effects v83
-    v85 = array_get v9, index u32 4 -> u8
-    v86 = eq v85, u8 225
-    v87 = not v86
-    v88 = mul v83, v87
-    v89 = lt v85, u8 225
-    enable_side_effects v88
-    v90 = mul v89, v88
-    constrain v90 == v88
-    v91 = not v88
-    v92 = mul v91, v81
-    v93 = unchecked_add v88, v92
-    v94 = mul v83, v86
-    enable_side_effects u1 1
-    v95 = not v93
-    enable_side_effects v95
-    v97 = array_get v9, index u32 5 -> u8
-    v98 = eq v97, u8 49
-    v99 = not v98
-    v100 = mul v95, v99
-    v101 = lt v97, u8 49
-    enable_side_effects v100
-    v102 = mul v101, v100
-    constrain v102 == v100
-    v103 = not v100
-    v104 = mul v103, v93
-    v105 = unchecked_add v100, v104
-    v106 = mul v95, v98
-    enable_side_effects u1 1
-    v107 = not v105
-    enable_side_effects v107
-    v109 = array_get v9, index u32 6 -> u8
-    v110 = eq v109, u8 160
-    v111 = not v110
-    v112 = mul v107, v111
-    v113 = lt v109, u8 160
-    enable_side_effects v112
-    v114 = mul v113, v112
-    constrain v114 == v112
-    v115 = not v112
-    v116 = mul v115, v105
-    v117 = unchecked_add v112, v116
-    v118 = mul v107, v110
-    enable_side_effects u1 1
-    v119 = not v117
-    enable_side_effects v119
-    v121 = array_get v9, index u32 7 -> u8
-    v122 = eq v121, u8 41
-    v123 = not v122
-    v124 = mul v119, v123
-    v125 = lt v121, u8 41
-    enable_side_effects v124
-    v126 = mul v125, v124
-    constrain v126 == v124
-    v127 = not v124
-    v128 = mul v127, v117
-    v129 = unchecked_add v124, v128
-    v130 = mul v119, v122
-    enable_side_effects u1 1
-    v131 = not v129
-    enable_side_effects v131
-    v133 = array_get v9, index u32 8 -> u8
-    v134 = eq v133, u8 184
-    v135 = not v134
-    v136 = mul v131, v135
-    v137 = lt v133, u8 184
-    enable_side_effects v136
-    v138 = mul v137, v136
-    constrain v138 == v136
-    v139 = not v136
-    v140 = mul v139, v129
-    v141 = unchecked_add v136, v140
-    v142 = mul v131, v134
-    enable_side_effects u1 1
-    v143 = not v141
-    enable_side_effects v143
-    v145 = array_get v9, index u32 9 -> u8
-    v146 = eq v145, u8 80
-    v147 = not v146
-    v148 = mul v143, v147
-    v149 = lt v145, u8 80
-    enable_side_effects v148
-    v150 = mul v149, v148
-    constrain v150 == v148
-    v151 = not v148
-    v152 = mul v151, v141
-    v153 = unchecked_add v148, v152
-    v154 = mul v143, v146
-    enable_side_effects u1 1
-    v155 = not v153
-    enable_side_effects v155
-    v157 = array_get v9, index u32 10 -> u8
-    v158 = eq v157, u8 69
-    v159 = not v158
-    v160 = mul v155, v159
-    v161 = lt v157, u8 69
-    enable_side_effects v160
-    v162 = mul v161, v160
-    constrain v162 == v160
-    v163 = not v160
-    v164 = mul v163, v153
-    v165 = unchecked_add v160, v164
-    v166 = mul v155, v158
-    enable_side_effects u1 1
-    v167 = not v165
-    enable_side_effects v167
-    v169 = array_get v9, index u32 11 -> u8
-    v170 = eq v169, u8 182
-    v171 = not v170
-    v172 = mul v167, v171
-    v173 = lt v169, u8 182
-    enable_side_effects v172
-    v174 = mul v173, v172
-    constrain v174 == v172
-    v175 = not v172
-    v176 = mul v175, v165
-    v177 = unchecked_add v172, v176
-    v178 = mul v167, v170
-    enable_side_effects u1 1
-    v179 = not v177
-    enable_side_effects v179
-    v181 = array_get v9, index u32 12 -> u8
-    v182 = eq v181, u8 129
-    v183 = not v182
-    v184 = mul v179, v183
-    v185 = lt v181, u8 129
-    enable_side_effects v184
-    v186 = mul v185, v184
-    constrain v186 == v184
-    v187 = not v184
-    v188 = mul v187, v177
-    v189 = unchecked_add v184, v188
-    v190 = mul v179, v182
-    enable_side_effects u1 1
-    v191 = not v189
-    enable_side_effects v191
-    v193 = array_get v9, index u32 13 -> u8
-    v194 = eq v193, u8 129
-    v195 = not v194
-    v196 = mul v191, v195
-    v197 = lt v193, u8 129
-    enable_side_effects v196
-    v198 = mul v197, v196
-    constrain v198 == v196
-    v199 = not v196
-    v200 = mul v199, v189
-    v201 = unchecked_add v196, v200
-    v202 = mul v191, v194
-    enable_side_effects u1 1
-    v203 = not v201
-    enable_side_effects v203
-    v205 = array_get v9, index u32 14 -> u8
-    v206 = eq v205, u8 88
-    v207 = not v206
-    v208 = mul v203, v207
-    v209 = lt v205, u8 88
-    enable_side_effects v208
-    v210 = mul v209, v208
-    constrain v210 == v208
-    v211 = not v208
-    v212 = mul v211, v201
-    v213 = unchecked_add v208, v212
-    v214 = mul v203, v206
-    enable_side_effects u1 1
-    v215 = not v213
-    enable_side_effects v215
-    v217 = array_get v9, index u32 15 -> u8
-    v218 = eq v217, u8 93
-    v219 = not v218
-    v220 = mul v215, v219
-    v221 = lt v217, u8 93
-    enable_side_effects v220
-    v222 = mul v221, v220
-    constrain v222 == v220
-    v223 = not v220
-    v224 = mul v223, v213
-    v225 = unchecked_add v220, v224
-    v226 = mul v215, v218
-    enable_side_effects u1 1
-    v227 = not v225
-    enable_side_effects v227
-    v229 = array_get v9, index u32 16 -> u8
-    v230 = eq v229, u8 40
-    v231 = not v230
-    v232 = mul v227, v231
-    v233 = lt v229, u8 40
-    enable_side_effects v232
-    v234 = mul v233, v232
-    constrain v234 == v232
-    v235 = not v232
-    v236 = mul v235, v225
-    v237 = unchecked_add v232, v236
-    v238 = mul v227, v230
-    enable_side_effects u1 1
-    v239 = not v237
-    enable_side_effects v239
-    v241 = array_get v9, index u32 17 -> u8
-    v242 = eq v241, u8 51
-    v243 = not v242
-    v244 = mul v239, v243
-    v245 = lt v241, u8 51
-    enable_side_effects v244
-    v246 = mul v245, v244
-    constrain v246 == v244
-    v247 = not v244
-    v248 = mul v247, v237
-    v249 = unchecked_add v244, v248
-    v250 = mul v239, v242
-    enable_side_effects u1 1
-    v251 = not v249
-    enable_side_effects v251
-    v253 = array_get v9, index u32 18 -> u8
-    v254 = eq v253, u8 232
-    v255 = not v254
-    v256 = mul v251, v255
-    v257 = lt v253, u8 232
-    enable_side_effects v256
-    v258 = mul v257, v256
-    constrain v258 == v256
-    v259 = not v256
-    v260 = mul v259, v249
-    v261 = unchecked_add v256, v260
-    v262 = mul v251, v254
-    enable_side_effects u1 1
-    v263 = not v261
-    enable_side_effects v263
-    v265 = array_get v9, index u32 19 -> u8
-    v266 = eq v265, u8 72
-    v267 = not v266
-    v268 = mul v263, v267
-    v269 = lt v265, u8 72
-    enable_side_effects v268
-    v270 = mul v269, v268
-    constrain v270 == v268
-    v271 = not v268
-    v272 = mul v271, v261
-    v273 = unchecked_add v268, v272
-    v274 = mul v263, v266
-    enable_side_effects u1 1
-    v275 = not v273
-    enable_side_effects v275
-    v277 = array_get v9, index u32 20 -> u8
-    v278 = eq v277, u8 121
-    v279 = not v278
-    v280 = mul v275, v279
-    v281 = lt v277, u8 121
-    enable_side_effects v280
-    v282 = mul v281, v280
-    constrain v282 == v280
-    v283 = not v280
-    v284 = mul v283, v273
-    v285 = unchecked_add v280, v284
-    v286 = mul v275, v278
-    enable_side_effects u1 1
-    v287 = not v285
-    enable_side_effects v287
-    v289 = array_get v9, index u32 21 -> u8
-    v290 = eq v289, u8 185
-    v291 = not v290
-    v292 = mul v287, v291
-    v293 = lt v289, u8 185
-    enable_side_effects v292
-    v294 = mul v293, v292
-    constrain v294 == v292
-    v295 = not v292
-    v296 = mul v295, v285
-    v297 = unchecked_add v292, v296
-    v298 = mul v287, v290
-    enable_side_effects u1 1
-    v299 = not v297
-    enable_side_effects v299
-    v301 = array_get v9, index u32 22 -> u8
-    v302 = eq v301, u8 112
-    v303 = not v302
-    v304 = mul v299, v303
-    v305 = lt v301, u8 112
-    enable_side_effects v304
-    v306 = mul v305, v304
-    constrain v306 == v304
-    v307 = not v304
-    v308 = mul v307, v297
-    v309 = unchecked_add v304, v308
-    v310 = mul v299, v302
-    enable_side_effects u1 1
-    v311 = not v309
-    enable_side_effects v311
-    v313 = array_get v9, index u32 23 -> u8
-    v314 = eq v313, u8 145
-    v315 = not v314
-    v316 = mul v311, v315
-    v317 = lt v313, u8 145
-    enable_side_effects v316
-    v318 = mul v317, v316
-    constrain v318 == v316
-    v319 = not v316
-    v320 = mul v319, v309
-    v321 = unchecked_add v316, v320
-    v322 = mul v311, v314
-    enable_side_effects u1 1
-    v323 = not v321
-    enable_side_effects v323
-    v325 = array_get v9, index u32 24 -> u8
-    v326 = eq v325, u8 67
-    v327 = not v326
-    v328 = mul v323, v327
-    v329 = lt v325, u8 67
-    enable_side_effects v328
-    v330 = mul v329, v328
-    constrain v330 == v328
-    v331 = not v328
-    v332 = mul v331, v321
-    v333 = unchecked_add v328, v332
-    v334 = mul v323, v326
-    enable_side_effects u1 1
-    v335 = not v333
-    enable_side_effects v335
-    v337 = array_get v9, index u32 25 -> u8
-    v338 = eq v337, u8 225
-    v339 = not v338
-    v340 = mul v335, v339
-    v341 = lt v337, u8 225
-    enable_side_effects v340
-    v342 = mul v341, v340
-    constrain v342 == v340
-    v343 = not v340
-    v344 = mul v343, v333
-    v345 = unchecked_add v340, v344
-    v346 = mul v335, v338
-    enable_side_effects u1 1
-    v347 = not v345
-    enable_side_effects v347
-    v349 = array_get v9, index u32 26 -> u8
-    v350 = eq v349, u8 245
-    v351 = not v350
-    v352 = mul v347, v351
-    v353 = lt v349, u8 245
-    enable_side_effects v352
-    v354 = mul v353, v352
-    constrain v354 == v352
-    v355 = not v352
-    v356 = mul v355, v345
-    v357 = unchecked_add v352, v356
-    v358 = mul v347, v350
-    enable_side_effects u1 1
-    v359 = not v357
-    enable_side_effects v359
-    v361 = array_get v9, index u32 27 -> u8
-    v362 = eq v361, u8 147
-    v363 = not v362
-    v364 = mul v359, v363
-    v365 = lt v361, u8 147
-    enable_side_effects v364
-    v366 = mul v365, v364
-    constrain v366 == v364
-    v367 = not v364
-    v368 = mul v367, v357
-    v369 = unchecked_add v364, v368
-    v370 = mul v359, v362
-    enable_side_effects u1 1
-    v371 = not v369
-    enable_side_effects v371
-    v373 = array_get v9, index u32 28 -> u8
-    v374 = eq v373, u8 240
-    v375 = not v374
-    v376 = mul v371, v375
-    v377 = lt v373, u8 240
-    enable_side_effects v376
-    v378 = mul v377, v376
-    constrain v378 == v376
-    v379 = not v376
-    v380 = mul v379, v369
-    v381 = unchecked_add v376, v380
-    v382 = mul v371, v374
-    enable_side_effects u1 1
-    v383 = not v381
-    enable_side_effects v383
-    v385 = array_get v9, index u32 29 -> u8
-    v386 = eq v385, u8 0
-    v387 = not v386
-    v388 = mul v383, v387
-    constrain u1 0 == v388
-    enable_side_effects u1 0
-    v390 = unchecked_add v388, v381
-    v391 = mul v383, v386
-    enable_side_effects u1 1
-    v392 = not v390
-    enable_side_effects v392
-    v394 = array_get v9, index u32 30 -> u8
-    v395 = eq v394, u8 0
-    v396 = not v395
-    v397 = mul v392, v396
-    constrain u1 0 == v397
-    enable_side_effects u1 0
-    v398 = unchecked_add v397, v390
-    v399 = mul v392, v395
-    enable_side_effects u1 1
-    v400 = not v398
-    enable_side_effects v400
-    v402 = array_get v9, index u32 31 -> u8
-    v403 = eq v402, u8 1
-    v404 = not v403
-    v405 = mul v400, v404
-    v406 = eq v402, u8 0
-    v407 = cast v405 as u8
-    enable_side_effects v405
-    v408 = unchecked_mul v402, v407
-    constrain v408 == u8 0
-    v409 = not v405
-    v410 = mul v409, v398
-    v411 = unchecked_add v405, v410
-    v412 = mul v400, v403
-    enable_side_effects u1 1
-    constrain v411 == u1 1
-    v413 = make_array [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v414 = allocate -> &mut u1
-    v415 = allocate -> &mut [u8; 32]
-    v416 = make_array [v42, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v417 = make_array [v42, v48, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v418 = make_array [v42, v48, v61, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v419 = make_array [v42, v48, v61, v73, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v420 = make_array [v42, v48, v61, v73, v85, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v421 = make_array [v42, v48, v61, v73, v85, v97, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v422 = make_array [v42, v48, v61, v73, v85, v97, v109, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v423 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v424 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v425 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v426 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v427 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v428 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v429 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v430 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v431 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v432 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v433 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v434 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v435 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v436 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v437 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v438 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v439 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v440 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v441 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v442 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, u8 0, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v443 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, u8 0, u8 0, u8 0, u8 0] : [u8; 32]
-    v444 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, u8 0, u8 0, u8 0] : [u8; 32]
-    v445 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, u8 0, u8 0] : [u8; 32]
-    v446 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v394, u8 0] : [u8; 32]
-    v447 = make_array [v42, v48, v61, v73, v85, v97, v109, v121, v133, v145, v157, v169, v181, v193, v205, v217, v229, v241, v253, v265, v277, v289, v301, v313, v325, v337, v349, v361, v373, v385, v394, v402] : [u8; 32]
-    v448 = allocate -> &mut Field
-    v449 = allocate -> &mut Field
-    v450 = allocate -> &mut Field
-    v451 = cast v217 as Field
-    v452 = cast v402 as Field
-    v453 = cast v205 as Field
-    v455 = mul v453, Field 256
-    v456 = add v451, v455
-    v457 = cast v394 as Field
-    v458 = mul v457, Field 256
-    v459 = add v452, v458
-    v460 = cast v193 as Field
-    v462 = mul v460, Field 65536
-    v463 = add v456, v462
-    v464 = cast v385 as Field
-    v465 = mul v464, Field 65536
-    v466 = add v459, v465
-    v467 = cast v181 as Field
-    v469 = mul v467, Field 16777216
-    v470 = add v463, v469
-    v471 = cast v373 as Field
-    v472 = mul v471, Field 16777216
-    v473 = add v466, v472
-    v474 = cast v169 as Field
-    v476 = mul v474, Field 4294967296
-    v477 = add v470, v476
-    v478 = cast v361 as Field
-    v479 = mul v478, Field 4294967296
-    v480 = add v473, v479
-    v481 = cast v157 as Field
-    v483 = mul v481, Field 1099511627776
-    v484 = add v477, v483
-    v485 = cast v349 as Field
-    v486 = mul v485, Field 1099511627776
-    v487 = add v480, v486
-    v488 = cast v145 as Field
-    v490 = mul v488, Field 281474976710656
-    v491 = add v484, v490
-    v492 = cast v337 as Field
-    v493 = mul v492, Field 281474976710656
-    v494 = add v487, v493
-    v495 = cast v133 as Field
-    v497 = mul v495, Field 72057594037927936
-    v498 = add v491, v497
-    v499 = cast v325 as Field
-    v500 = mul v499, Field 72057594037927936
-    v501 = add v494, v500
-    v502 = cast v121 as Field
-    v504 = mul v502, Field 18446744073709551616
-    v505 = add v498, v504
-    v506 = cast v313 as Field
-    v507 = mul v506, Field 18446744073709551616
-    v508 = add v501, v507
-    v509 = cast v109 as Field
-    v511 = mul v509, Field 4722366482869645213696
-    v512 = add v505, v511
-    v513 = cast v301 as Field
-    v514 = mul v513, Field 4722366482869645213696
-    v515 = add v508, v514
-    v516 = cast v97 as Field
-    v518 = mul v516, Field 1208925819614629174706176
-    v519 = add v512, v518
-    v520 = cast v289 as Field
-    v521 = mul v520, Field 1208925819614629174706176
-    v522 = add v515, v521
-    v523 = cast v85 as Field
-    v525 = mul v523, Field 309485009821345068724781056
-    v526 = add v519, v525
-    v527 = cast v277 as Field
-    v528 = mul v527, Field 309485009821345068724781056
-    v529 = add v522, v528
-    v530 = cast v73 as Field
-    v532 = mul v530, Field 79228162514264337593543950336
-    v533 = add v526, v532
-    v534 = cast v265 as Field
-    v535 = mul v534, Field 79228162514264337593543950336
-    v536 = add v529, v535
-    v537 = cast v61 as Field
-    v539 = mul v537, Field 20282409603651670423947251286016
-    v540 = add v533, v539
-    v541 = cast v253 as Field
-    v542 = mul v541, Field 20282409603651670423947251286016
-    v543 = add v536, v542
-    v544 = cast v48 as Field
-    v546 = mul v544, Field 5192296858534827628530496329220096
-    v547 = add v540, v546
-    v548 = cast v241 as Field
-    v549 = mul v548, Field 5192296858534827628530496329220096
-    v550 = add v543, v549
-    v551 = cast v42 as Field
-    v553 = mul v551, Field 1329227995784915872903807060280344576
-    v554 = add v547, v553
-    v555 = cast v229 as Field
-    v556 = mul v555, Field 1329227995784915872903807060280344576
-    v557 = add v550, v556
-    v559 = mul v554, Field 340282366920938463463374607431768211456
-    v560 = add v557, v559
-    v561 = allocate -> &mut Field
-    v563 = eq v4, Field 0
-    v564 = not v563
-    enable_side_effects v564
-    v566 = call f1(v4, Field 0) -> u1
-    v567 = mul v564, v566
-    enable_side_effects v567
-    v569, v570 = call f3(Field 0) -> (Field, Field)
-    v571 = cast v567 as Field
-    v572 = mul v569, v571
-    range_check v572 to 128 bits
-    v573 = mul v570, v571
-    range_check v573 to 128 bits
-    v574 = mul Field 340282366920938463463374607431768211456, v570
-    v575 = add v569, v574
-    v576 = eq Field 0, v575
-    v577 = mul v575, v571
-    constrain Field 0 == v577
-    v580 = call f2(Field 53438638232309528389504892708671455233, v569) -> u1
-    v581 = sub Field 53438638232309528389504892708671455233, v569
-    v583 = sub v581, Field 1
-    v584 = cast v580 as Field
-    v585 = mul v584, Field 340282366920938463463374607431768211456
-    v586 = add v583, v585
-    v588 = sub Field 64323764613183177041862057485226039389, v570
-    v589 = sub v588, v584
-    v590 = mul v586, v571
-    range_check v590 to 128 bits
-    v591 = mul v589, v571
-    range_check v591 to 128 bits
-    v593, v594 = call f3(v4) -> (Field, Field)
-    v595 = mul v593, v571
-    range_check v595 to 128 bits
-    v596 = mul v594, v571
-    range_check v596 to 128 bits
-    v597 = mul Field 340282366920938463463374607431768211456, v594
-    v598 = add v593, v597
-    v599 = eq v4, v598
-    v600 = mul v4, v571
-    v601 = mul v598, v571
-    constrain v600 == v601
-    v603 = call f2(Field 53438638232309528389504892708671455233, v593) -> u1
-    v604 = sub Field 53438638232309528389504892708671455233, v593
-    v605 = sub v604, Field 1
-    v606 = cast v603 as Field
-    v607 = mul v606, Field 340282366920938463463374607431768211456
-    v608 = add v605, v607
-    v609 = sub Field 64323764613183177041862057485226039389, v594
-    v610 = sub v609, v606
-    v611 = mul v608, v571
-    range_check v611 to 128 bits
-    v612 = mul v610, v571
-    range_check v612 to 128 bits
-    v614 = call f2(v569, v593) -> u1
-    v615 = sub v569, v593
-    v616 = sub v615, Field 1
-    v617 = cast v614 as Field
-    v618 = mul v617, Field 340282366920938463463374607431768211456
-    v619 = add v616, v618
-    v620 = sub v570, v594
-    v621 = sub v620, v617
-    v622 = mul v619, v571
-    range_check v622 to 128 bits
-    v623 = mul v621, v571
-    range_check v623 to 128 bits
-    v624 = not v566
-    v625 = mul v564, v624
-    enable_side_effects v625
-    v627, v628 = call f3(v4) -> (Field, Field)
-    v629 = cast v625 as Field
-    v630 = mul v627, v629
-    range_check v630 to 128 bits
-    v631 = mul v628, v629
-    range_check v631 to 128 bits
-    v632 = mul Field 340282366920938463463374607431768211456, v628
-    v633 = add v627, v632
-    v634 = eq v4, v633
-    v635 = mul v4, v629
-    v636 = mul v633, v629
-    constrain v635 == v636
-    v638 = call f2(Field 53438638232309528389504892708671455233, v627) -> u1
-    v639 = sub Field 53438638232309528389504892708671455233, v627
-    v640 = sub v639, Field 1
-    v641 = cast v638 as Field
-    v642 = mul v641, Field 340282366920938463463374607431768211456
-    v643 = add v640, v642
-    v644 = sub Field 64323764613183177041862057485226039389, v628
-    v645 = sub v644, v641
-    v646 = mul v643, v629
-    range_check v646 to 128 bits
-    v647 = mul v645, v629
-    range_check v647 to 128 bits
-    v649, v650 = call f3(Field 0) -> (Field, Field)
-    v651 = mul v649, v629
-    range_check v651 to 128 bits
-    v652 = mul v650, v629
-    range_check v652 to 128 bits
-    v653 = mul Field 340282366920938463463374607431768211456, v650
-    v654 = add v649, v653
-    v655 = eq Field 0, v654
-    v656 = mul v654, v629
-    constrain Field 0 == v656
-    v658 = call f2(Field 53438638232309528389504892708671455233, v649) -> u1
-    v659 = sub Field 53438638232309528389504892708671455233, v649
-    v660 = sub v659, Field 1
-    v661 = cast v658 as Field
-    v662 = mul v661, Field 340282366920938463463374607431768211456
-    v663 = add v660, v662
-    v664 = sub Field 64323764613183177041862057485226039389, v650
-    v665 = sub v664, v661
-    v666 = mul v663, v629
-    range_check v666 to 128 bits
-    v667 = mul v665, v629
-    range_check v667 to 128 bits
-    v669 = call f2(v627, v649) -> u1
-    v670 = sub v627, v649
-    v671 = sub v670, Field 1
-    v672 = cast v669 as Field
-    v673 = mul v672, Field 340282366920938463463374607431768211456
-    v674 = add v671, v673
-    v675 = sub v628, v650
-    v676 = sub v675, v672
-    v677 = mul v674, v629
-    range_check v677 to 128 bits
-    v678 = mul v676, v629
-    range_check v678 to 128 bits
-    v679 = not v625
-    v680 = cast v679 as Field
-    enable_side_effects u1 1
-    v681 = sub v629, v560
-    return v681
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = allocate -> &mut Field
-    v6 = truncate v4 to 64 bits, max_bit_size: 254
-    v7 = cast v6 as u64
-    v8 = sub v4, v6
-    v9 = div v8, Field 18446744073709551616
-    v10 = truncate v9 to 64 bits, max_bit_size: 254
-    v11 = cast v10 as u64
-    v12 = sub v9, v10
-    v13 = div v12, Field 18446744073709551616
-    v14 = mul v10, Field 18446744073709551616
-    v15 = add v14, v6
-    return v15, v13
-}
-
-After Dead Instruction Elimination (1st):
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v7 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v9 = array_get v7, index u32 0 -> u8
-    v11 = eq v9, u8 48
-    v12 = not v11
-    v13 = lt v9, u8 48
-    enable_side_effects v12
-    v14 = mul v13, v12
-    constrain v14 == v12
-    enable_side_effects v11
-    v16 = array_get v7, index u32 1 -> u8
-    v18 = eq v16, u8 100
-    v19 = not v18
-    v20 = mul v11, v19
-    v21 = lt v16, u8 100
-    enable_side_effects v20
-    v22 = mul v21, v20
-    constrain v22 == v20
-    v23 = not v20
-    v24 = mul v23, v12
-    v25 = unchecked_add v20, v24
-    enable_side_effects u1 1
-    v27 = not v25
-    enable_side_effects v27
-    v29 = array_get v7, index u32 2 -> u8
-    v31 = eq v29, u8 78
-    v32 = not v31
-    v33 = mul v27, v32
-    v34 = lt v29, u8 78
-    enable_side_effects v33
-    v35 = mul v34, v33
-    constrain v35 == v33
-    v36 = not v33
-    v37 = mul v36, v25
-    v38 = unchecked_add v33, v37
-    enable_side_effects u1 1
-    v39 = not v38
-    enable_side_effects v39
-    v41 = array_get v7, index u32 3 -> u8
-    v43 = eq v41, u8 114
-    v44 = not v43
-    v45 = mul v39, v44
-    v46 = lt v41, u8 114
-    enable_side_effects v45
-    v47 = mul v46, v45
-    constrain v47 == v45
-    v48 = not v45
-    v49 = mul v48, v38
-    v50 = unchecked_add v45, v49
-    enable_side_effects u1 1
-    v51 = not v50
-    enable_side_effects v51
-    v53 = array_get v7, index u32 4 -> u8
-    v55 = eq v53, u8 225
-    v56 = not v55
-    v57 = mul v51, v56
-    v58 = lt v53, u8 225
-    enable_side_effects v57
-    v59 = mul v58, v57
-    constrain v59 == v57
-    v60 = not v57
-    v61 = mul v60, v50
-    v62 = unchecked_add v57, v61
-    enable_side_effects u1 1
-    v63 = not v62
-    enable_side_effects v63
-    v65 = array_get v7, index u32 5 -> u8
-    v67 = eq v65, u8 49
-    v68 = not v67
-    v69 = mul v63, v68
-    v70 = lt v65, u8 49
-    enable_side_effects v69
-    v71 = mul v70, v69
-    constrain v71 == v69
-    v72 = not v69
-    v73 = mul v72, v62
-    v74 = unchecked_add v69, v73
-    enable_side_effects u1 1
-    v75 = not v74
-    enable_side_effects v75
-    v77 = array_get v7, index u32 6 -> u8
-    v79 = eq v77, u8 160
-    v80 = not v79
-    v81 = mul v75, v80
-    v82 = lt v77, u8 160
-    enable_side_effects v81
-    v83 = mul v82, v81
-    constrain v83 == v81
-    v84 = not v81
-    v85 = mul v84, v74
-    v86 = unchecked_add v81, v85
-    enable_side_effects u1 1
-    v87 = not v86
-    enable_side_effects v87
-    v89 = array_get v7, index u32 7 -> u8
-    v91 = eq v89, u8 41
-    v92 = not v91
-    v93 = mul v87, v92
-    v94 = lt v89, u8 41
-    enable_side_effects v93
-    v95 = mul v94, v93
-    constrain v95 == v93
-    v96 = not v93
-    v97 = mul v96, v86
-    v98 = unchecked_add v93, v97
-    enable_side_effects u1 1
-    v99 = not v98
-    enable_side_effects v99
-    v101 = array_get v7, index u32 8 -> u8
-    v103 = eq v101, u8 184
-    v104 = not v103
-    v105 = mul v99, v104
-    v106 = lt v101, u8 184
-    enable_side_effects v105
-    v107 = mul v106, v105
-    constrain v107 == v105
-    v108 = not v105
-    v109 = mul v108, v98
-    v110 = unchecked_add v105, v109
-    enable_side_effects u1 1
-    v111 = not v110
-    enable_side_effects v111
-    v113 = array_get v7, index u32 9 -> u8
-    v115 = eq v113, u8 80
-    v116 = not v115
-    v117 = mul v111, v116
-    v118 = lt v113, u8 80
-    enable_side_effects v117
-    v119 = mul v118, v117
-    constrain v119 == v117
-    v120 = not v117
-    v121 = mul v120, v110
-    v122 = unchecked_add v117, v121
-    enable_side_effects u1 1
-    v123 = not v122
-    enable_side_effects v123
-    v125 = array_get v7, index u32 10 -> u8
-    v127 = eq v125, u8 69
-    v128 = not v127
-    v129 = mul v123, v128
-    v130 = lt v125, u8 69
-    enable_side_effects v129
-    v131 = mul v130, v129
-    constrain v131 == v129
-    v132 = not v129
-    v133 = mul v132, v122
-    v134 = unchecked_add v129, v133
-    enable_side_effects u1 1
-    v135 = not v134
-    enable_side_effects v135
-    v137 = array_get v7, index u32 11 -> u8
-    v139 = eq v137, u8 182
-    v140 = not v139
-    v141 = mul v135, v140
-    v142 = lt v137, u8 182
-    enable_side_effects v141
-    v143 = mul v142, v141
-    constrain v143 == v141
-    v144 = not v141
-    v145 = mul v144, v134
-    v146 = unchecked_add v141, v145
-    enable_side_effects u1 1
-    v147 = not v146
-    enable_side_effects v147
-    v149 = array_get v7, index u32 12 -> u8
-    v151 = eq v149, u8 129
-    v152 = not v151
-    v153 = mul v147, v152
-    v154 = lt v149, u8 129
-    enable_side_effects v153
-    v155 = mul v154, v153
-    constrain v155 == v153
-    v156 = not v153
-    v157 = mul v156, v146
-    v158 = unchecked_add v153, v157
-    enable_side_effects u1 1
-    v159 = not v158
-    enable_side_effects v159
-    v161 = array_get v7, index u32 13 -> u8
-    v162 = eq v161, u8 129
-    v163 = not v162
-    v164 = mul v159, v163
-    v165 = lt v161, u8 129
-    enable_side_effects v164
-    v166 = mul v165, v164
-    constrain v166 == v164
-    v167 = not v164
-    v168 = mul v167, v158
-    v169 = unchecked_add v164, v168
-    enable_side_effects u1 1
-    v170 = not v169
-    enable_side_effects v170
-    v172 = array_get v7, index u32 14 -> u8
-    v174 = eq v172, u8 88
-    v175 = not v174
-    v176 = mul v170, v175
-    v177 = lt v172, u8 88
-    enable_side_effects v176
-    v178 = mul v177, v176
-    constrain v178 == v176
-    v179 = not v176
-    v180 = mul v179, v169
-    v181 = unchecked_add v176, v180
-    enable_side_effects u1 1
-    v182 = not v181
-    enable_side_effects v182
-    v184 = array_get v7, index u32 15 -> u8
-    v186 = eq v184, u8 93
-    v187 = not v186
-    v188 = mul v182, v187
-    v189 = lt v184, u8 93
-    enable_side_effects v188
-    v190 = mul v189, v188
-    constrain v190 == v188
-    v191 = not v188
-    v192 = mul v191, v181
-    v193 = unchecked_add v188, v192
-    enable_side_effects u1 1
-    v194 = not v193
-    enable_side_effects v194
-    v196 = array_get v7, index u32 16 -> u8
-    v198 = eq v196, u8 40
-    v199 = not v198
-    v200 = mul v194, v199
-    v201 = lt v196, u8 40
-    enable_side_effects v200
-    v202 = mul v201, v200
-    constrain v202 == v200
-    v203 = not v200
-    v204 = mul v203, v193
-    v205 = unchecked_add v200, v204
-    enable_side_effects u1 1
-    v206 = not v205
-    enable_side_effects v206
-    v208 = array_get v7, index u32 17 -> u8
-    v210 = eq v208, u8 51
-    v211 = not v210
-    v212 = mul v206, v211
-    v213 = lt v208, u8 51
-    enable_side_effects v212
-    v214 = mul v213, v212
-    constrain v214 == v212
-    v215 = not v212
-    v216 = mul v215, v205
-    v217 = unchecked_add v212, v216
-    enable_side_effects u1 1
-    v218 = not v217
-    enable_side_effects v218
-    v220 = array_get v7, index u32 18 -> u8
-    v222 = eq v220, u8 232
-    v223 = not v222
-    v224 = mul v218, v223
-    v225 = lt v220, u8 232
-    enable_side_effects v224
-    v226 = mul v225, v224
-    constrain v226 == v224
-    v227 = not v224
-    v228 = mul v227, v217
-    v229 = unchecked_add v224, v228
-    enable_side_effects u1 1
-    v230 = not v229
-    enable_side_effects v230
-    v232 = array_get v7, index u32 19 -> u8
-    v234 = eq v232, u8 72
-    v235 = not v234
-    v236 = mul v230, v235
-    v237 = lt v232, u8 72
-    enable_side_effects v236
-    v238 = mul v237, v236
-    constrain v238 == v236
-    v239 = not v236
-    v240 = mul v239, v229
-    v241 = unchecked_add v236, v240
-    enable_side_effects u1 1
-    v242 = not v241
-    enable_side_effects v242
-    v244 = array_get v7, index u32 20 -> u8
-    v246 = eq v244, u8 121
-    v247 = not v246
-    v248 = mul v242, v247
-    v249 = lt v244, u8 121
-    enable_side_effects v248
-    v250 = mul v249, v248
-    constrain v250 == v248
-    v251 = not v248
-    v252 = mul v251, v241
-    v253 = unchecked_add v248, v252
-    enable_side_effects u1 1
-    v254 = not v253
-    enable_side_effects v254
-    v256 = array_get v7, index u32 21 -> u8
-    v258 = eq v256, u8 185
-    v259 = not v258
-    v260 = mul v254, v259
-    v261 = lt v256, u8 185
-    enable_side_effects v260
-    v262 = mul v261, v260
-    constrain v262 == v260
-    v263 = not v260
-    v264 = mul v263, v253
-    v265 = unchecked_add v260, v264
-    enable_side_effects u1 1
-    v266 = not v265
-    enable_side_effects v266
-    v268 = array_get v7, index u32 22 -> u8
-    v270 = eq v268, u8 112
-    v271 = not v270
-    v272 = mul v266, v271
-    v273 = lt v268, u8 112
-    enable_side_effects v272
-    v274 = mul v273, v272
-    constrain v274 == v272
-    v275 = not v272
-    v276 = mul v275, v265
-    v277 = unchecked_add v272, v276
-    enable_side_effects u1 1
-    v278 = not v277
-    enable_side_effects v278
-    v280 = array_get v7, index u32 23 -> u8
-    v282 = eq v280, u8 145
-    v283 = not v282
-    v284 = mul v278, v283
-    v285 = lt v280, u8 145
-    enable_side_effects v284
-    v286 = mul v285, v284
-    constrain v286 == v284
-    v287 = not v284
-    v288 = mul v287, v277
-    v289 = unchecked_add v284, v288
-    enable_side_effects u1 1
-    v290 = not v289
-    enable_side_effects v290
-    v292 = array_get v7, index u32 24 -> u8
-    v294 = eq v292, u8 67
-    v295 = not v294
-    v296 = mul v290, v295
-    v297 = lt v292, u8 67
-    enable_side_effects v296
-    v298 = mul v297, v296
-    constrain v298 == v296
-    v299 = not v296
-    v300 = mul v299, v289
-    v301 = unchecked_add v296, v300
-    enable_side_effects u1 1
-    v302 = not v301
-    enable_side_effects v302
-    v304 = array_get v7, index u32 25 -> u8
-    v305 = eq v304, u8 225
-    v306 = not v305
-    v307 = mul v302, v306
-    v308 = lt v304, u8 225
-    enable_side_effects v307
-    v309 = mul v308, v307
-    constrain v309 == v307
-    v310 = not v307
-    v311 = mul v310, v301
-    v312 = unchecked_add v307, v311
-    enable_side_effects u1 1
-    v313 = not v312
-    enable_side_effects v313
-    v315 = array_get v7, index u32 26 -> u8
-    v317 = eq v315, u8 245
-    v318 = not v317
-    v319 = mul v313, v318
-    v320 = lt v315, u8 245
-    enable_side_effects v319
-    v321 = mul v320, v319
-    constrain v321 == v319
-    v322 = not v319
-    v323 = mul v322, v312
-    v324 = unchecked_add v319, v323
-    enable_side_effects u1 1
-    v325 = not v324
-    enable_side_effects v325
-    v327 = array_get v7, index u32 27 -> u8
-    v329 = eq v327, u8 147
-    v330 = not v329
-    v331 = mul v325, v330
-    v332 = lt v327, u8 147
-    enable_side_effects v331
-    v333 = mul v332, v331
-    constrain v333 == v331
-    v334 = not v331
-    v335 = mul v334, v324
-    v336 = unchecked_add v331, v335
-    enable_side_effects u1 1
-    v337 = not v336
-    enable_side_effects v337
-    v339 = array_get v7, index u32 28 -> u8
-    v341 = eq v339, u8 240
-    v342 = not v341
-    v343 = mul v337, v342
-    v344 = lt v339, u8 240
-    enable_side_effects v343
-    v345 = mul v344, v343
-    constrain v345 == v343
-    v346 = not v343
-    v347 = mul v346, v336
-    v348 = unchecked_add v343, v347
-    enable_side_effects u1 1
-    v349 = not v348
-    enable_side_effects v349
-    v351 = array_get v7, index u32 29 -> u8
-    v353 = eq v351, u8 0
-    v354 = not v353
-    v355 = mul v349, v354
-    constrain u1 0 == v355
-    enable_side_effects u1 0
-    v357 = unchecked_add v355, v348
-    enable_side_effects u1 1
-    v358 = not v357
-    enable_side_effects v358
-    v360 = array_get v7, index u32 30 -> u8
-    v361 = eq v360, u8 0
-    v362 = not v361
-    v363 = mul v358, v362
-    constrain u1 0 == v363
-    enable_side_effects u1 0
-    v364 = unchecked_add v363, v357
-    enable_side_effects u1 1
-    v365 = not v364
-    enable_side_effects v365
-    v367 = array_get v7, index u32 31 -> u8
-    v369 = eq v367, u8 1
-    v370 = not v369
-    v371 = mul v365, v370
-    v372 = cast v371 as u8
-    enable_side_effects v371
-    v373 = unchecked_mul v367, v372
-    constrain v373 == u8 0
-    v374 = not v371
-    v375 = mul v374, v364
-    v376 = unchecked_add v371, v375
-    enable_side_effects u1 1
-    constrain v376 == u1 1
-    v377 = cast v184 as Field
-    v378 = cast v367 as Field
-    v379 = cast v172 as Field
-    v381 = mul v379, Field 256
-    v382 = add v377, v381
-    v383 = cast v360 as Field
-    v384 = mul v383, Field 256
-    v385 = add v378, v384
-    v386 = cast v161 as Field
-    v388 = mul v386, Field 65536
-    v389 = add v382, v388
-    v390 = cast v351 as Field
-    v391 = mul v390, Field 65536
-    v392 = add v385, v391
-    v393 = cast v149 as Field
-    v395 = mul v393, Field 16777216
-    v396 = add v389, v395
-    v397 = cast v339 as Field
-    v398 = mul v397, Field 16777216
-    v399 = add v392, v398
-    v400 = cast v137 as Field
-    v402 = mul v400, Field 4294967296
-    v403 = add v396, v402
-    v404 = cast v327 as Field
-    v405 = mul v404, Field 4294967296
-    v406 = add v399, v405
-    v407 = cast v125 as Field
-    v409 = mul v407, Field 1099511627776
-    v410 = add v403, v409
-    v411 = cast v315 as Field
-    v412 = mul v411, Field 1099511627776
-    v413 = add v406, v412
-    v414 = cast v113 as Field
-    v416 = mul v414, Field 281474976710656
-    v417 = add v410, v416
-    v418 = cast v304 as Field
-    v419 = mul v418, Field 281474976710656
-    v420 = add v413, v419
-    v421 = cast v101 as Field
-    v423 = mul v421, Field 72057594037927936
-    v424 = add v417, v423
-    v425 = cast v292 as Field
-    v426 = mul v425, Field 72057594037927936
-    v427 = add v420, v426
-    v428 = cast v89 as Field
-    v430 = mul v428, Field 18446744073709551616
-    v431 = add v424, v430
-    v432 = cast v280 as Field
-    v433 = mul v432, Field 18446744073709551616
-    v434 = add v427, v433
-    v435 = cast v77 as Field
-    v437 = mul v435, Field 4722366482869645213696
-    v438 = add v431, v437
-    v439 = cast v268 as Field
-    v440 = mul v439, Field 4722366482869645213696
-    v441 = add v434, v440
-    v442 = cast v65 as Field
-    v444 = mul v442, Field 1208925819614629174706176
-    v445 = add v438, v444
-    v446 = cast v256 as Field
-    v447 = mul v446, Field 1208925819614629174706176
-    v448 = add v441, v447
-    v449 = cast v53 as Field
-    v451 = mul v449, Field 309485009821345068724781056
-    v452 = add v445, v451
-    v453 = cast v244 as Field
-    v454 = mul v453, Field 309485009821345068724781056
-    v455 = add v448, v454
-    v456 = cast v41 as Field
-    v458 = mul v456, Field 79228162514264337593543950336
-    v459 = add v452, v458
-    v460 = cast v232 as Field
-    v461 = mul v460, Field 79228162514264337593543950336
-    v462 = add v455, v461
-    v463 = cast v29 as Field
-    v465 = mul v463, Field 20282409603651670423947251286016
-    v466 = add v459, v465
-    v467 = cast v220 as Field
-    v468 = mul v467, Field 20282409603651670423947251286016
-    v469 = add v462, v468
-    v470 = cast v16 as Field
-    v472 = mul v470, Field 5192296858534827628530496329220096
-    v473 = add v466, v472
-    v474 = cast v208 as Field
-    v475 = mul v474, Field 5192296858534827628530496329220096
-    v476 = add v469, v475
-    v477 = cast v9 as Field
-    v479 = mul v477, Field 1329227995784915872903807060280344576
-    v480 = add v473, v479
-    v481 = cast v196 as Field
-    v482 = mul v481, Field 1329227995784915872903807060280344576
-    v483 = add v476, v482
-    v485 = mul v480, Field 340282366920938463463374607431768211456
-    v486 = add v483, v485
-    v488 = eq v4, Field 0
-    v489 = not v488
-    enable_side_effects v489
-    v491 = call f1(v4, Field 0) -> u1
-    v492 = mul v489, v491
-    enable_side_effects v492
-    v494, v495 = call f3(Field 0) -> (Field, Field)
-    v496 = cast v492 as Field
-    v497 = mul v494, v496
-    range_check v497 to 128 bits
-    v498 = mul v495, v496
-    range_check v498 to 128 bits
-    v499 = mul Field 340282366920938463463374607431768211456, v495
-    v500 = add v494, v499
-    v501 = mul v500, v496
-    constrain Field 0 == v501
-    v504 = call f2(Field 53438638232309528389504892708671455233, v494) -> u1
-    v505 = sub Field 53438638232309528389504892708671455233, v494
-    v507 = sub v505, Field 1
-    v508 = cast v504 as Field
-    v509 = mul v508, Field 340282366920938463463374607431768211456
-    v510 = add v507, v509
-    v512 = sub Field 64323764613183177041862057485226039389, v495
-    v513 = sub v512, v508
-    v514 = mul v510, v496
-    range_check v514 to 128 bits
-    v515 = mul v513, v496
-    range_check v515 to 128 bits
-    v517, v518 = call f3(v4) -> (Field, Field)
-    v519 = mul v517, v496
-    range_check v519 to 128 bits
-    v520 = mul v518, v496
-    range_check v520 to 128 bits
-    v521 = mul Field 340282366920938463463374607431768211456, v518
-    v522 = add v517, v521
-    v523 = mul v4, v496
-    v524 = mul v522, v496
-    constrain v523 == v524
-    v526 = call f2(Field 53438638232309528389504892708671455233, v517) -> u1
-    v527 = sub Field 53438638232309528389504892708671455233, v517
-    v528 = sub v527, Field 1
-    v529 = cast v526 as Field
-    v530 = mul v529, Field 340282366920938463463374607431768211456
-    v531 = add v528, v530
-    v532 = sub Field 64323764613183177041862057485226039389, v518
-    v533 = sub v532, v529
-    v534 = mul v531, v496
-    range_check v534 to 128 bits
-    v535 = mul v533, v496
-    range_check v535 to 128 bits
-    v537 = call f2(v494, v517) -> u1
-    v538 = sub v494, v517
-    v539 = sub v538, Field 1
-    v540 = cast v537 as Field
-    v541 = mul v540, Field 340282366920938463463374607431768211456
-    v542 = add v539, v541
-    v543 = sub v495, v518
-    v544 = sub v543, v540
-    v545 = mul v542, v496
-    range_check v545 to 128 bits
-    v546 = mul v544, v496
-    range_check v546 to 128 bits
-    v547 = not v491
-    v548 = mul v489, v547
-    enable_side_effects v548
-    v550, v551 = call f3(v4) -> (Field, Field)
-    v552 = cast v548 as Field
-    v553 = mul v550, v552
-    range_check v553 to 128 bits
-    v554 = mul v551, v552
-    range_check v554 to 128 bits
-    v555 = mul Field 340282366920938463463374607431768211456, v551
-    v556 = add v550, v555
-    v557 = mul v4, v552
-    v558 = mul v556, v552
-    constrain v557 == v558
-    v560 = call f2(Field 53438638232309528389504892708671455233, v550) -> u1
-    v561 = sub Field 53438638232309528389504892708671455233, v550
-    v562 = sub v561, Field 1
-    v563 = cast v560 as Field
-    v564 = mul v563, Field 340282366920938463463374607431768211456
-    v565 = add v562, v564
-    v566 = sub Field 64323764613183177041862057485226039389, v551
-    v567 = sub v566, v563
-    v568 = mul v565, v552
-    range_check v568 to 128 bits
-    v569 = mul v567, v552
-    range_check v569 to 128 bits
-    v571, v572 = call f3(Field 0) -> (Field, Field)
-    v573 = mul v571, v552
-    range_check v573 to 128 bits
-    v574 = mul v572, v552
-    range_check v574 to 128 bits
-    v575 = mul Field 340282366920938463463374607431768211456, v572
-    v576 = add v571, v575
-    v577 = mul v576, v552
-    constrain Field 0 == v577
-    v579 = call f2(Field 53438638232309528389504892708671455233, v571) -> u1
-    v580 = sub Field 53438638232309528389504892708671455233, v571
-    v581 = sub v580, Field 1
-    v582 = cast v579 as Field
-    v583 = mul v582, Field 340282366920938463463374607431768211456
-    v584 = add v581, v583
-    v585 = sub Field 64323764613183177041862057485226039389, v572
-    v586 = sub v585, v582
-    v587 = mul v584, v552
-    range_check v587 to 128 bits
-    v588 = mul v586, v552
-    range_check v588 to 128 bits
-    v590 = call f2(v550, v571) -> u1
-    v591 = sub v550, v571
-    v592 = sub v591, Field 1
-    v593 = cast v590 as Field
-    v594 = mul v593, Field 340282366920938463463374607431768211456
-    v595 = add v592, v594
-    v596 = sub v551, v572
-    v597 = sub v596, v593
-    v598 = mul v595, v552
-    range_check v598 to 128 bits
-    v599 = mul v597, v552
-    range_check v599 to 128 bits
-    enable_side_effects u1 1
-    v600 = sub v552, v486
-    return v600
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = truncate v4 to 64 bits, max_bit_size: 254
-    v6 = sub v4, v5
-    v7 = div v6, Field 18446744073709551616
-    v8 = truncate v7 to 64 bits, max_bit_size: 254
-    v9 = sub v7, v8
-    v10 = div v9, Field 18446744073709551616
-    v11 = mul v8, Field 18446744073709551616
-    v12 = add v11, v5
-    return v12, v10
-}
-
-After Simplifying::
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v7 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v9 = array_get v7, index u32 0 -> u8
-    v11 = eq v9, u8 48
-    v12 = not v11
-    v13 = lt v9, u8 48
-    enable_side_effects v12
-    v14 = mul v13, v12
-    constrain v14 == v12
-    enable_side_effects v11
-    v16 = array_get v7, index u32 1 -> u8
-    v18 = eq v16, u8 100
-    v19 = not v18
-    v20 = mul v11, v19
-    v21 = lt v16, u8 100
-    enable_side_effects v20
-    v22 = mul v21, v20
-    constrain v22 == v20
-    v23 = not v20
-    v24 = mul v23, v12
-    v25 = unchecked_add v20, v24
-    enable_side_effects u1 1
-    v27 = not v25
-    enable_side_effects v27
-    v29 = array_get v7, index u32 2 -> u8
-    v31 = eq v29, u8 78
-    v32 = not v31
-    v33 = mul v27, v32
-    v34 = lt v29, u8 78
-    enable_side_effects v33
-    v35 = mul v34, v33
-    constrain v35 == v33
-    v36 = not v33
-    v37 = mul v36, v25
-    v38 = unchecked_add v33, v37
-    enable_side_effects u1 1
-    v39 = not v38
-    enable_side_effects v39
-    v41 = array_get v7, index u32 3 -> u8
-    v43 = eq v41, u8 114
-    v44 = not v43
-    v45 = mul v39, v44
-    v46 = lt v41, u8 114
-    enable_side_effects v45
-    v47 = mul v46, v45
-    constrain v47 == v45
-    v48 = not v45
-    v49 = mul v48, v38
-    v50 = unchecked_add v45, v49
-    enable_side_effects u1 1
-    v51 = not v50
-    enable_side_effects v51
-    v53 = array_get v7, index u32 4 -> u8
-    v55 = eq v53, u8 225
-    v56 = not v55
-    v57 = mul v51, v56
-    v58 = lt v53, u8 225
-    enable_side_effects v57
-    v59 = mul v58, v57
-    constrain v59 == v57
-    v60 = not v57
-    v61 = mul v60, v50
-    v62 = unchecked_add v57, v61
-    enable_side_effects u1 1
-    v63 = not v62
-    enable_side_effects v63
-    v65 = array_get v7, index u32 5 -> u8
-    v67 = eq v65, u8 49
-    v68 = not v67
-    v69 = mul v63, v68
-    v70 = lt v65, u8 49
-    enable_side_effects v69
-    v71 = mul v70, v69
-    constrain v71 == v69
-    v72 = not v69
-    v73 = mul v72, v62
-    v74 = unchecked_add v69, v73
-    enable_side_effects u1 1
-    v75 = not v74
-    enable_side_effects v75
-    v77 = array_get v7, index u32 6 -> u8
-    v79 = eq v77, u8 160
-    v80 = not v79
-    v81 = mul v75, v80
-    v82 = lt v77, u8 160
-    enable_side_effects v81
-    v83 = mul v82, v81
-    constrain v83 == v81
-    v84 = not v81
-    v85 = mul v84, v74
-    v86 = unchecked_add v81, v85
-    enable_side_effects u1 1
-    v87 = not v86
-    enable_side_effects v87
-    v89 = array_get v7, index u32 7 -> u8
-    v91 = eq v89, u8 41
-    v92 = not v91
-    v93 = mul v87, v92
-    v94 = lt v89, u8 41
-    enable_side_effects v93
-    v95 = mul v94, v93
-    constrain v95 == v93
-    v96 = not v93
-    v97 = mul v96, v86
-    v98 = unchecked_add v93, v97
-    enable_side_effects u1 1
-    v99 = not v98
-    enable_side_effects v99
-    v101 = array_get v7, index u32 8 -> u8
-    v103 = eq v101, u8 184
-    v104 = not v103
-    v105 = mul v99, v104
-    v106 = lt v101, u8 184
-    enable_side_effects v105
-    v107 = mul v106, v105
-    constrain v107 == v105
-    v108 = not v105
-    v109 = mul v108, v98
-    v110 = unchecked_add v105, v109
-    enable_side_effects u1 1
-    v111 = not v110
-    enable_side_effects v111
-    v113 = array_get v7, index u32 9 -> u8
-    v115 = eq v113, u8 80
-    v116 = not v115
-    v117 = mul v111, v116
-    v118 = lt v113, u8 80
-    enable_side_effects v117
-    v119 = mul v118, v117
-    constrain v119 == v117
-    v120 = not v117
-    v121 = mul v120, v110
-    v122 = unchecked_add v117, v121
-    enable_side_effects u1 1
-    v123 = not v122
-    enable_side_effects v123
-    v125 = array_get v7, index u32 10 -> u8
-    v127 = eq v125, u8 69
-    v128 = not v127
-    v129 = mul v123, v128
-    v130 = lt v125, u8 69
-    enable_side_effects v129
-    v131 = mul v130, v129
-    constrain v131 == v129
-    v132 = not v129
-    v133 = mul v132, v122
-    v134 = unchecked_add v129, v133
-    enable_side_effects u1 1
-    v135 = not v134
-    enable_side_effects v135
-    v137 = array_get v7, index u32 11 -> u8
-    v139 = eq v137, u8 182
-    v140 = not v139
-    v141 = mul v135, v140
-    v142 = lt v137, u8 182
-    enable_side_effects v141
-    v143 = mul v142, v141
-    constrain v143 == v141
-    v144 = not v141
-    v145 = mul v144, v134
-    v146 = unchecked_add v141, v145
-    enable_side_effects u1 1
-    v147 = not v146
-    enable_side_effects v147
-    v149 = array_get v7, index u32 12 -> u8
-    v151 = eq v149, u8 129
-    v152 = not v151
-    v153 = mul v147, v152
-    v154 = lt v149, u8 129
-    enable_side_effects v153
-    v155 = mul v154, v153
-    constrain v155 == v153
-    v156 = not v153
-    v157 = mul v156, v146
-    v158 = unchecked_add v153, v157
-    enable_side_effects u1 1
-    v159 = not v158
-    enable_side_effects v159
-    v161 = array_get v7, index u32 13 -> u8
-    v162 = eq v161, u8 129
-    v163 = not v162
-    v164 = mul v159, v163
-    v165 = lt v161, u8 129
-    enable_side_effects v164
-    v166 = mul v165, v164
-    constrain v166 == v164
-    v167 = not v164
-    v168 = mul v167, v158
-    v169 = unchecked_add v164, v168
-    enable_side_effects u1 1
-    v170 = not v169
-    enable_side_effects v170
-    v172 = array_get v7, index u32 14 -> u8
-    v174 = eq v172, u8 88
-    v175 = not v174
-    v176 = mul v170, v175
-    v177 = lt v172, u8 88
-    enable_side_effects v176
-    v178 = mul v177, v176
-    constrain v178 == v176
-    v179 = not v176
-    v180 = mul v179, v169
-    v181 = unchecked_add v176, v180
-    enable_side_effects u1 1
-    v182 = not v181
-    enable_side_effects v182
-    v184 = array_get v7, index u32 15 -> u8
-    v186 = eq v184, u8 93
-    v187 = not v186
-    v188 = mul v182, v187
-    v189 = lt v184, u8 93
-    enable_side_effects v188
-    v190 = mul v189, v188
-    constrain v190 == v188
-    v191 = not v188
-    v192 = mul v191, v181
-    v193 = unchecked_add v188, v192
-    enable_side_effects u1 1
-    v194 = not v193
-    enable_side_effects v194
-    v196 = array_get v7, index u32 16 -> u8
-    v198 = eq v196, u8 40
-    v199 = not v198
-    v200 = mul v194, v199
-    v201 = lt v196, u8 40
-    enable_side_effects v200
-    v202 = mul v201, v200
-    constrain v202 == v200
-    v203 = not v200
-    v204 = mul v203, v193
-    v205 = unchecked_add v200, v204
-    enable_side_effects u1 1
-    v206 = not v205
-    enable_side_effects v206
-    v208 = array_get v7, index u32 17 -> u8
-    v210 = eq v208, u8 51
-    v211 = not v210
-    v212 = mul v206, v211
-    v213 = lt v208, u8 51
-    enable_side_effects v212
-    v214 = mul v213, v212
-    constrain v214 == v212
-    v215 = not v212
-    v216 = mul v215, v205
-    v217 = unchecked_add v212, v216
-    enable_side_effects u1 1
-    v218 = not v217
-    enable_side_effects v218
-    v220 = array_get v7, index u32 18 -> u8
-    v222 = eq v220, u8 232
-    v223 = not v222
-    v224 = mul v218, v223
-    v225 = lt v220, u8 232
-    enable_side_effects v224
-    v226 = mul v225, v224
-    constrain v226 == v224
-    v227 = not v224
-    v228 = mul v227, v217
-    v229 = unchecked_add v224, v228
-    enable_side_effects u1 1
-    v230 = not v229
-    enable_side_effects v230
-    v232 = array_get v7, index u32 19 -> u8
-    v234 = eq v232, u8 72
-    v235 = not v234
-    v236 = mul v230, v235
-    v237 = lt v232, u8 72
-    enable_side_effects v236
-    v238 = mul v237, v236
-    constrain v238 == v236
-    v239 = not v236
-    v240 = mul v239, v229
-    v241 = unchecked_add v236, v240
-    enable_side_effects u1 1
-    v242 = not v241
-    enable_side_effects v242
-    v244 = array_get v7, index u32 20 -> u8
-    v246 = eq v244, u8 121
-    v247 = not v246
-    v248 = mul v242, v247
-    v249 = lt v244, u8 121
-    enable_side_effects v248
-    v250 = mul v249, v248
-    constrain v250 == v248
-    v251 = not v248
-    v252 = mul v251, v241
-    v253 = unchecked_add v248, v252
-    enable_side_effects u1 1
-    v254 = not v253
-    enable_side_effects v254
-    v256 = array_get v7, index u32 21 -> u8
-    v258 = eq v256, u8 185
-    v259 = not v258
-    v260 = mul v254, v259
-    v261 = lt v256, u8 185
-    enable_side_effects v260
-    v262 = mul v261, v260
-    constrain v262 == v260
-    v263 = not v260
-    v264 = mul v263, v253
-    v265 = unchecked_add v260, v264
-    enable_side_effects u1 1
-    v266 = not v265
-    enable_side_effects v266
-    v268 = array_get v7, index u32 22 -> u8
-    v270 = eq v268, u8 112
-    v271 = not v270
-    v272 = mul v266, v271
-    v273 = lt v268, u8 112
-    enable_side_effects v272
-    v274 = mul v273, v272
-    constrain v274 == v272
-    v275 = not v272
-    v276 = mul v275, v265
-    v277 = unchecked_add v272, v276
-    enable_side_effects u1 1
-    v278 = not v277
-    enable_side_effects v278
-    v280 = array_get v7, index u32 23 -> u8
-    v282 = eq v280, u8 145
-    v283 = not v282
-    v284 = mul v278, v283
-    v285 = lt v280, u8 145
-    enable_side_effects v284
-    v286 = mul v285, v284
-    constrain v286 == v284
-    v287 = not v284
-    v288 = mul v287, v277
-    v289 = unchecked_add v284, v288
-    enable_side_effects u1 1
-    v290 = not v289
-    enable_side_effects v290
-    v292 = array_get v7, index u32 24 -> u8
-    v294 = eq v292, u8 67
-    v295 = not v294
-    v296 = mul v290, v295
-    v297 = lt v292, u8 67
-    enable_side_effects v296
-    v298 = mul v297, v296
-    constrain v298 == v296
-    v299 = not v296
-    v300 = mul v299, v289
-    v301 = unchecked_add v296, v300
-    enable_side_effects u1 1
-    v302 = not v301
-    enable_side_effects v302
-    v304 = array_get v7, index u32 25 -> u8
-    v305 = eq v304, u8 225
-    v306 = not v305
-    v307 = mul v302, v306
-    v308 = lt v304, u8 225
-    enable_side_effects v307
-    v309 = mul v308, v307
-    constrain v309 == v307
-    v310 = not v307
-    v311 = mul v310, v301
-    v312 = unchecked_add v307, v311
-    enable_side_effects u1 1
-    v313 = not v312
-    enable_side_effects v313
-    v315 = array_get v7, index u32 26 -> u8
-    v317 = eq v315, u8 245
-    v318 = not v317
-    v319 = mul v313, v318
-    v320 = lt v315, u8 245
-    enable_side_effects v319
-    v321 = mul v320, v319
-    constrain v321 == v319
-    v322 = not v319
-    v323 = mul v322, v312
-    v324 = unchecked_add v319, v323
-    enable_side_effects u1 1
-    v325 = not v324
-    enable_side_effects v325
-    v327 = array_get v7, index u32 27 -> u8
-    v329 = eq v327, u8 147
-    v330 = not v329
-    v331 = mul v325, v330
-    v332 = lt v327, u8 147
-    enable_side_effects v331
-    v333 = mul v332, v331
-    constrain v333 == v331
-    v334 = not v331
-    v335 = mul v334, v324
-    v336 = unchecked_add v331, v335
-    enable_side_effects u1 1
-    v337 = not v336
-    enable_side_effects v337
-    v339 = array_get v7, index u32 28 -> u8
-    v341 = eq v339, u8 240
-    v342 = not v341
-    v343 = mul v337, v342
-    v344 = lt v339, u8 240
-    enable_side_effects v343
-    v345 = mul v344, v343
-    constrain v345 == v343
-    v346 = not v343
-    v347 = mul v346, v336
-    v348 = unchecked_add v343, v347
-    enable_side_effects u1 1
-    v349 = not v348
-    enable_side_effects v349
-    v351 = array_get v7, index u32 29 -> u8
-    v353 = eq v351, u8 0
-    v354 = not v353
-    v355 = mul v349, v354
-    constrain u1 0 == v355
-    enable_side_effects u1 0
-    v357 = unchecked_add v355, v348
-    enable_side_effects u1 1
-    v358 = not v357
-    enable_side_effects v358
-    v360 = array_get v7, index u32 30 -> u8
-    v361 = eq v360, u8 0
-    v362 = not v361
-    v363 = mul v358, v362
-    constrain u1 0 == v363
-    enable_side_effects u1 0
-    v364 = unchecked_add v363, v357
-    enable_side_effects u1 1
-    v365 = not v364
-    enable_side_effects v365
-    v367 = array_get v7, index u32 31 -> u8
-    v369 = eq v367, u8 1
-    v370 = not v369
-    v371 = mul v365, v370
-    v372 = cast v371 as u8
-    enable_side_effects v371
-    v373 = unchecked_mul v367, v372
-    constrain v373 == u8 0
-    v374 = not v371
-    v375 = mul v374, v364
-    v376 = unchecked_add v371, v375
-    enable_side_effects u1 1
-    constrain v376 == u1 1
-    v377 = cast v184 as Field
-    v378 = cast v367 as Field
-    v379 = cast v172 as Field
-    v381 = mul v379, Field 256
-    v382 = add v377, v381
-    v383 = cast v360 as Field
-    v384 = mul v383, Field 256
-    v385 = add v378, v384
-    v386 = cast v161 as Field
-    v388 = mul v386, Field 65536
-    v389 = add v382, v388
-    v390 = cast v351 as Field
-    v391 = mul v390, Field 65536
-    v392 = add v385, v391
-    v393 = cast v149 as Field
-    v395 = mul v393, Field 16777216
-    v396 = add v389, v395
-    v397 = cast v339 as Field
-    v398 = mul v397, Field 16777216
-    v399 = add v392, v398
-    v400 = cast v137 as Field
-    v402 = mul v400, Field 4294967296
-    v403 = add v396, v402
-    v404 = cast v327 as Field
-    v405 = mul v404, Field 4294967296
-    v406 = add v399, v405
-    v407 = cast v125 as Field
-    v409 = mul v407, Field 1099511627776
-    v410 = add v403, v409
-    v411 = cast v315 as Field
-    v412 = mul v411, Field 1099511627776
-    v413 = add v406, v412
-    v414 = cast v113 as Field
-    v416 = mul v414, Field 281474976710656
-    v417 = add v410, v416
-    v418 = cast v304 as Field
-    v419 = mul v418, Field 281474976710656
-    v420 = add v413, v419
-    v421 = cast v101 as Field
-    v423 = mul v421, Field 72057594037927936
-    v424 = add v417, v423
-    v425 = cast v292 as Field
-    v426 = mul v425, Field 72057594037927936
-    v427 = add v420, v426
-    v428 = cast v89 as Field
-    v430 = mul v428, Field 18446744073709551616
-    v431 = add v424, v430
-    v432 = cast v280 as Field
-    v433 = mul v432, Field 18446744073709551616
-    v434 = add v427, v433
-    v435 = cast v77 as Field
-    v437 = mul v435, Field 4722366482869645213696
-    v438 = add v431, v437
-    v439 = cast v268 as Field
-    v440 = mul v439, Field 4722366482869645213696
-    v441 = add v434, v440
-    v442 = cast v65 as Field
-    v444 = mul v442, Field 1208925819614629174706176
-    v445 = add v438, v444
-    v446 = cast v256 as Field
-    v447 = mul v446, Field 1208925819614629174706176
-    v448 = add v441, v447
-    v449 = cast v53 as Field
-    v451 = mul v449, Field 309485009821345068724781056
-    v452 = add v445, v451
-    v453 = cast v244 as Field
-    v454 = mul v453, Field 309485009821345068724781056
-    v455 = add v448, v454
-    v456 = cast v41 as Field
-    v458 = mul v456, Field 79228162514264337593543950336
-    v459 = add v452, v458
-    v460 = cast v232 as Field
-    v461 = mul v460, Field 79228162514264337593543950336
-    v462 = add v455, v461
-    v463 = cast v29 as Field
-    v465 = mul v463, Field 20282409603651670423947251286016
-    v466 = add v459, v465
-    v467 = cast v220 as Field
-    v468 = mul v467, Field 20282409603651670423947251286016
-    v469 = add v462, v468
-    v470 = cast v16 as Field
-    v472 = mul v470, Field 5192296858534827628530496329220096
-    v473 = add v466, v472
-    v474 = cast v208 as Field
-    v475 = mul v474, Field 5192296858534827628530496329220096
-    v476 = add v469, v475
-    v477 = cast v9 as Field
-    v479 = mul v477, Field 1329227995784915872903807060280344576
-    v480 = add v473, v479
-    v481 = cast v196 as Field
-    v482 = mul v481, Field 1329227995784915872903807060280344576
-    v483 = add v476, v482
-    v485 = mul v480, Field 340282366920938463463374607431768211456
-    v486 = add v483, v485
-    v488 = eq v4, Field 0
-    v489 = not v488
-    enable_side_effects v489
-    v491 = call f1(v4, Field 0) -> u1
-    v492 = mul v489, v491
-    enable_side_effects v492
-    v494, v495 = call f3(Field 0) -> (Field, Field)
-    v496 = cast v492 as Field
-    v497 = mul v494, v496
-    range_check v497 to 128 bits
-    v498 = mul v495, v496
-    range_check v498 to 128 bits
-    v499 = mul Field 340282366920938463463374607431768211456, v495
-    v500 = add v494, v499
-    v501 = mul v500, v496
-    constrain Field 0 == v501
-    v504 = call f2(Field 53438638232309528389504892708671455233, v494) -> u1
-    v505 = sub Field 53438638232309528389504892708671455233, v494
-    v507 = sub v505, Field 1
-    v508 = cast v504 as Field
-    v509 = mul v508, Field 340282366920938463463374607431768211456
-    v510 = add v507, v509
-    v512 = sub Field 64323764613183177041862057485226039389, v495
-    v513 = sub v512, v508
-    v514 = mul v510, v496
-    range_check v514 to 128 bits
-    v515 = mul v513, v496
-    range_check v515 to 128 bits
-    v517, v518 = call f3(v4) -> (Field, Field)
-    v519 = mul v517, v496
-    range_check v519 to 128 bits
-    v520 = mul v518, v496
-    range_check v520 to 128 bits
-    v521 = mul Field 340282366920938463463374607431768211456, v518
-    v522 = add v517, v521
-    v523 = mul v4, v496
-    v524 = mul v522, v496
-    constrain v523 == v524
-    v526 = call f2(Field 53438638232309528389504892708671455233, v517) -> u1
-    v527 = sub Field 53438638232309528389504892708671455233, v517
-    v528 = sub v527, Field 1
-    v529 = cast v526 as Field
-    v530 = mul v529, Field 340282366920938463463374607431768211456
-    v531 = add v528, v530
-    v532 = sub Field 64323764613183177041862057485226039389, v518
-    v533 = sub v532, v529
-    v534 = mul v531, v496
-    range_check v534 to 128 bits
-    v535 = mul v533, v496
-    range_check v535 to 128 bits
-    v537 = call f2(v494, v517) -> u1
-    v538 = sub v494, v517
-    v539 = sub v538, Field 1
-    v540 = cast v537 as Field
-    v541 = mul v540, Field 340282366920938463463374607431768211456
-    v542 = add v539, v541
-    v543 = sub v495, v518
-    v544 = sub v543, v540
-    v545 = mul v542, v496
-    range_check v545 to 128 bits
-    v546 = mul v544, v496
-    range_check v546 to 128 bits
-    v547 = not v491
-    v548 = mul v489, v547
-    enable_side_effects v548
-    v550, v551 = call f3(v4) -> (Field, Field)
-    v552 = cast v548 as Field
-    v553 = mul v550, v552
-    range_check v553 to 128 bits
-    v554 = mul v551, v552
-    range_check v554 to 128 bits
-    v555 = mul Field 340282366920938463463374607431768211456, v551
-    v556 = add v550, v555
-    v557 = mul v4, v552
-    v558 = mul v556, v552
-    constrain v557 == v558
-    v560 = call f2(Field 53438638232309528389504892708671455233, v550) -> u1
-    v561 = sub Field 53438638232309528389504892708671455233, v550
-    v562 = sub v561, Field 1
-    v563 = cast v560 as Field
-    v564 = mul v563, Field 340282366920938463463374607431768211456
-    v565 = add v562, v564
-    v566 = sub Field 64323764613183177041862057485226039389, v551
-    v567 = sub v566, v563
-    v568 = mul v565, v552
-    range_check v568 to 128 bits
-    v569 = mul v567, v552
-    range_check v569 to 128 bits
-    v571, v572 = call f3(Field 0) -> (Field, Field)
-    v573 = mul v571, v552
-    range_check v573 to 128 bits
-    v574 = mul v572, v552
-    range_check v574 to 128 bits
-    v575 = mul Field 340282366920938463463374607431768211456, v572
-    v576 = add v571, v575
-    v577 = mul v576, v552
-    constrain Field 0 == v577
-    v579 = call f2(Field 53438638232309528389504892708671455233, v571) -> u1
-    v580 = sub Field 53438638232309528389504892708671455233, v571
-    v581 = sub v580, Field 1
-    v582 = cast v579 as Field
-    v583 = mul v582, Field 340282366920938463463374607431768211456
-    v584 = add v581, v583
-    v585 = sub Field 64323764613183177041862057485226039389, v572
-    v586 = sub v585, v582
-    v587 = mul v584, v552
-    range_check v587 to 128 bits
-    v588 = mul v586, v552
-    range_check v588 to 128 bits
-    v590 = call f2(v550, v571) -> u1
-    v591 = sub v550, v571
-    v592 = sub v591, Field 1
-    v593 = cast v590 as Field
-    v594 = mul v593, Field 340282366920938463463374607431768211456
-    v595 = add v592, v594
-    v596 = sub v551, v572
-    v597 = sub v596, v593
-    v598 = mul v595, v552
-    range_check v598 to 128 bits
-    v599 = mul v597, v552
-    range_check v599 to 128 bits
-    enable_side_effects u1 1
-    v600 = sub v552, v486
-    return v600
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = truncate v4 to 64 bits, max_bit_size: 254
-    v6 = sub v4, v5
-    v7 = div v6, Field 18446744073709551616
-    v8 = truncate v7 to 64 bits, max_bit_size: 254
-    v9 = sub v7, v8
-    v10 = div v9, Field 18446744073709551616
-    v11 = mul v8, Field 18446744073709551616
-    v12 = add v11, v5
-    return v12, v10
-}
-
-After Array Set Optimizations:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v7 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v9 = array_get v7, index u32 0 -> u8
-    v11 = eq v9, u8 48
-    v12 = not v11
-    v13 = lt v9, u8 48
-    enable_side_effects v12
-    v14 = mul v13, v12
-    constrain v14 == v12
-    enable_side_effects v11
-    v16 = array_get v7, index u32 1 -> u8
-    v18 = eq v16, u8 100
-    v19 = not v18
-    v20 = mul v11, v19
-    v21 = lt v16, u8 100
-    enable_side_effects v20
-    v22 = mul v21, v20
-    constrain v22 == v20
-    v23 = not v20
-    v24 = mul v23, v12
-    v25 = unchecked_add v20, v24
-    enable_side_effects u1 1
-    v27 = not v25
-    enable_side_effects v27
-    v29 = array_get v7, index u32 2 -> u8
-    v31 = eq v29, u8 78
-    v32 = not v31
-    v33 = mul v27, v32
-    v34 = lt v29, u8 78
-    enable_side_effects v33
-    v35 = mul v34, v33
-    constrain v35 == v33
-    v36 = not v33
-    v37 = mul v36, v25
-    v38 = unchecked_add v33, v37
-    enable_side_effects u1 1
-    v39 = not v38
-    enable_side_effects v39
-    v41 = array_get v7, index u32 3 -> u8
-    v43 = eq v41, u8 114
-    v44 = not v43
-    v45 = mul v39, v44
-    v46 = lt v41, u8 114
-    enable_side_effects v45
-    v47 = mul v46, v45
-    constrain v47 == v45
-    v48 = not v45
-    v49 = mul v48, v38
-    v50 = unchecked_add v45, v49
-    enable_side_effects u1 1
-    v51 = not v50
-    enable_side_effects v51
-    v53 = array_get v7, index u32 4 -> u8
-    v55 = eq v53, u8 225
-    v56 = not v55
-    v57 = mul v51, v56
-    v58 = lt v53, u8 225
-    enable_side_effects v57
-    v59 = mul v58, v57
-    constrain v59 == v57
-    v60 = not v57
-    v61 = mul v60, v50
-    v62 = unchecked_add v57, v61
-    enable_side_effects u1 1
-    v63 = not v62
-    enable_side_effects v63
-    v65 = array_get v7, index u32 5 -> u8
-    v67 = eq v65, u8 49
-    v68 = not v67
-    v69 = mul v63, v68
-    v70 = lt v65, u8 49
-    enable_side_effects v69
-    v71 = mul v70, v69
-    constrain v71 == v69
-    v72 = not v69
-    v73 = mul v72, v62
-    v74 = unchecked_add v69, v73
-    enable_side_effects u1 1
-    v75 = not v74
-    enable_side_effects v75
-    v77 = array_get v7, index u32 6 -> u8
-    v79 = eq v77, u8 160
-    v80 = not v79
-    v81 = mul v75, v80
-    v82 = lt v77, u8 160
-    enable_side_effects v81
-    v83 = mul v82, v81
-    constrain v83 == v81
-    v84 = not v81
-    v85 = mul v84, v74
-    v86 = unchecked_add v81, v85
-    enable_side_effects u1 1
-    v87 = not v86
-    enable_side_effects v87
-    v89 = array_get v7, index u32 7 -> u8
-    v91 = eq v89, u8 41
-    v92 = not v91
-    v93 = mul v87, v92
-    v94 = lt v89, u8 41
-    enable_side_effects v93
-    v95 = mul v94, v93
-    constrain v95 == v93
-    v96 = not v93
-    v97 = mul v96, v86
-    v98 = unchecked_add v93, v97
-    enable_side_effects u1 1
-    v99 = not v98
-    enable_side_effects v99
-    v101 = array_get v7, index u32 8 -> u8
-    v103 = eq v101, u8 184
-    v104 = not v103
-    v105 = mul v99, v104
-    v106 = lt v101, u8 184
-    enable_side_effects v105
-    v107 = mul v106, v105
-    constrain v107 == v105
-    v108 = not v105
-    v109 = mul v108, v98
-    v110 = unchecked_add v105, v109
-    enable_side_effects u1 1
-    v111 = not v110
-    enable_side_effects v111
-    v113 = array_get v7, index u32 9 -> u8
-    v115 = eq v113, u8 80
-    v116 = not v115
-    v117 = mul v111, v116
-    v118 = lt v113, u8 80
-    enable_side_effects v117
-    v119 = mul v118, v117
-    constrain v119 == v117
-    v120 = not v117
-    v121 = mul v120, v110
-    v122 = unchecked_add v117, v121
-    enable_side_effects u1 1
-    v123 = not v122
-    enable_side_effects v123
-    v125 = array_get v7, index u32 10 -> u8
-    v127 = eq v125, u8 69
-    v128 = not v127
-    v129 = mul v123, v128
-    v130 = lt v125, u8 69
-    enable_side_effects v129
-    v131 = mul v130, v129
-    constrain v131 == v129
-    v132 = not v129
-    v133 = mul v132, v122
-    v134 = unchecked_add v129, v133
-    enable_side_effects u1 1
-    v135 = not v134
-    enable_side_effects v135
-    v137 = array_get v7, index u32 11 -> u8
-    v139 = eq v137, u8 182
-    v140 = not v139
-    v141 = mul v135, v140
-    v142 = lt v137, u8 182
-    enable_side_effects v141
-    v143 = mul v142, v141
-    constrain v143 == v141
-    v144 = not v141
-    v145 = mul v144, v134
-    v146 = unchecked_add v141, v145
-    enable_side_effects u1 1
-    v147 = not v146
-    enable_side_effects v147
-    v149 = array_get v7, index u32 12 -> u8
-    v151 = eq v149, u8 129
-    v152 = not v151
-    v153 = mul v147, v152
-    v154 = lt v149, u8 129
-    enable_side_effects v153
-    v155 = mul v154, v153
-    constrain v155 == v153
-    v156 = not v153
-    v157 = mul v156, v146
-    v158 = unchecked_add v153, v157
-    enable_side_effects u1 1
-    v159 = not v158
-    enable_side_effects v159
-    v161 = array_get v7, index u32 13 -> u8
-    v162 = eq v161, u8 129
-    v163 = not v162
-    v164 = mul v159, v163
-    v165 = lt v161, u8 129
-    enable_side_effects v164
-    v166 = mul v165, v164
-    constrain v166 == v164
-    v167 = not v164
-    v168 = mul v167, v158
-    v169 = unchecked_add v164, v168
-    enable_side_effects u1 1
-    v170 = not v169
-    enable_side_effects v170
-    v172 = array_get v7, index u32 14 -> u8
-    v174 = eq v172, u8 88
-    v175 = not v174
-    v176 = mul v170, v175
-    v177 = lt v172, u8 88
-    enable_side_effects v176
-    v178 = mul v177, v176
-    constrain v178 == v176
-    v179 = not v176
-    v180 = mul v179, v169
-    v181 = unchecked_add v176, v180
-    enable_side_effects u1 1
-    v182 = not v181
-    enable_side_effects v182
-    v184 = array_get v7, index u32 15 -> u8
-    v186 = eq v184, u8 93
-    v187 = not v186
-    v188 = mul v182, v187
-    v189 = lt v184, u8 93
-    enable_side_effects v188
-    v190 = mul v189, v188
-    constrain v190 == v188
-    v191 = not v188
-    v192 = mul v191, v181
-    v193 = unchecked_add v188, v192
-    enable_side_effects u1 1
-    v194 = not v193
-    enable_side_effects v194
-    v196 = array_get v7, index u32 16 -> u8
-    v198 = eq v196, u8 40
-    v199 = not v198
-    v200 = mul v194, v199
-    v201 = lt v196, u8 40
-    enable_side_effects v200
-    v202 = mul v201, v200
-    constrain v202 == v200
-    v203 = not v200
-    v204 = mul v203, v193
-    v205 = unchecked_add v200, v204
-    enable_side_effects u1 1
-    v206 = not v205
-    enable_side_effects v206
-    v208 = array_get v7, index u32 17 -> u8
-    v210 = eq v208, u8 51
-    v211 = not v210
-    v212 = mul v206, v211
-    v213 = lt v208, u8 51
-    enable_side_effects v212
-    v214 = mul v213, v212
-    constrain v214 == v212
-    v215 = not v212
-    v216 = mul v215, v205
-    v217 = unchecked_add v212, v216
-    enable_side_effects u1 1
-    v218 = not v217
-    enable_side_effects v218
-    v220 = array_get v7, index u32 18 -> u8
-    v222 = eq v220, u8 232
-    v223 = not v222
-    v224 = mul v218, v223
-    v225 = lt v220, u8 232
-    enable_side_effects v224
-    v226 = mul v225, v224
-    constrain v226 == v224
-    v227 = not v224
-    v228 = mul v227, v217
-    v229 = unchecked_add v224, v228
-    enable_side_effects u1 1
-    v230 = not v229
-    enable_side_effects v230
-    v232 = array_get v7, index u32 19 -> u8
-    v234 = eq v232, u8 72
-    v235 = not v234
-    v236 = mul v230, v235
-    v237 = lt v232, u8 72
-    enable_side_effects v236
-    v238 = mul v237, v236
-    constrain v238 == v236
-    v239 = not v236
-    v240 = mul v239, v229
-    v241 = unchecked_add v236, v240
-    enable_side_effects u1 1
-    v242 = not v241
-    enable_side_effects v242
-    v244 = array_get v7, index u32 20 -> u8
-    v246 = eq v244, u8 121
-    v247 = not v246
-    v248 = mul v242, v247
-    v249 = lt v244, u8 121
-    enable_side_effects v248
-    v250 = mul v249, v248
-    constrain v250 == v248
-    v251 = not v248
-    v252 = mul v251, v241
-    v253 = unchecked_add v248, v252
-    enable_side_effects u1 1
-    v254 = not v253
-    enable_side_effects v254
-    v256 = array_get v7, index u32 21 -> u8
-    v258 = eq v256, u8 185
-    v259 = not v258
-    v260 = mul v254, v259
-    v261 = lt v256, u8 185
-    enable_side_effects v260
-    v262 = mul v261, v260
-    constrain v262 == v260
-    v263 = not v260
-    v264 = mul v263, v253
-    v265 = unchecked_add v260, v264
-    enable_side_effects u1 1
-    v266 = not v265
-    enable_side_effects v266
-    v268 = array_get v7, index u32 22 -> u8
-    v270 = eq v268, u8 112
-    v271 = not v270
-    v272 = mul v266, v271
-    v273 = lt v268, u8 112
-    enable_side_effects v272
-    v274 = mul v273, v272
-    constrain v274 == v272
-    v275 = not v272
-    v276 = mul v275, v265
-    v277 = unchecked_add v272, v276
-    enable_side_effects u1 1
-    v278 = not v277
-    enable_side_effects v278
-    v280 = array_get v7, index u32 23 -> u8
-    v282 = eq v280, u8 145
-    v283 = not v282
-    v284 = mul v278, v283
-    v285 = lt v280, u8 145
-    enable_side_effects v284
-    v286 = mul v285, v284
-    constrain v286 == v284
-    v287 = not v284
-    v288 = mul v287, v277
-    v289 = unchecked_add v284, v288
-    enable_side_effects u1 1
-    v290 = not v289
-    enable_side_effects v290
-    v292 = array_get v7, index u32 24 -> u8
-    v294 = eq v292, u8 67
-    v295 = not v294
-    v296 = mul v290, v295
-    v297 = lt v292, u8 67
-    enable_side_effects v296
-    v298 = mul v297, v296
-    constrain v298 == v296
-    v299 = not v296
-    v300 = mul v299, v289
-    v301 = unchecked_add v296, v300
-    enable_side_effects u1 1
-    v302 = not v301
-    enable_side_effects v302
-    v304 = array_get v7, index u32 25 -> u8
-    v305 = eq v304, u8 225
-    v306 = not v305
-    v307 = mul v302, v306
-    v308 = lt v304, u8 225
-    enable_side_effects v307
-    v309 = mul v308, v307
-    constrain v309 == v307
-    v310 = not v307
-    v311 = mul v310, v301
-    v312 = unchecked_add v307, v311
-    enable_side_effects u1 1
-    v313 = not v312
-    enable_side_effects v313
-    v315 = array_get v7, index u32 26 -> u8
-    v317 = eq v315, u8 245
-    v318 = not v317
-    v319 = mul v313, v318
-    v320 = lt v315, u8 245
-    enable_side_effects v319
-    v321 = mul v320, v319
-    constrain v321 == v319
-    v322 = not v319
-    v323 = mul v322, v312
-    v324 = unchecked_add v319, v323
-    enable_side_effects u1 1
-    v325 = not v324
-    enable_side_effects v325
-    v327 = array_get v7, index u32 27 -> u8
-    v329 = eq v327, u8 147
-    v330 = not v329
-    v331 = mul v325, v330
-    v332 = lt v327, u8 147
-    enable_side_effects v331
-    v333 = mul v332, v331
-    constrain v333 == v331
-    v334 = not v331
-    v335 = mul v334, v324
-    v336 = unchecked_add v331, v335
-    enable_side_effects u1 1
-    v337 = not v336
-    enable_side_effects v337
-    v339 = array_get v7, index u32 28 -> u8
-    v341 = eq v339, u8 240
-    v342 = not v341
-    v343 = mul v337, v342
-    v344 = lt v339, u8 240
-    enable_side_effects v343
-    v345 = mul v344, v343
-    constrain v345 == v343
-    v346 = not v343
-    v347 = mul v346, v336
-    v348 = unchecked_add v343, v347
-    enable_side_effects u1 1
-    v349 = not v348
-    enable_side_effects v349
-    v351 = array_get v7, index u32 29 -> u8
-    v353 = eq v351, u8 0
-    v354 = not v353
-    v355 = mul v349, v354
-    constrain u1 0 == v355
-    enable_side_effects u1 0
-    v357 = unchecked_add v355, v348
-    enable_side_effects u1 1
-    v358 = not v357
-    enable_side_effects v358
-    v360 = array_get v7, index u32 30 -> u8
-    v361 = eq v360, u8 0
-    v362 = not v361
-    v363 = mul v358, v362
-    constrain u1 0 == v363
-    enable_side_effects u1 0
-    v364 = unchecked_add v363, v357
-    enable_side_effects u1 1
-    v365 = not v364
-    enable_side_effects v365
-    v367 = array_get v7, index u32 31 -> u8
-    v369 = eq v367, u8 1
-    v370 = not v369
-    v371 = mul v365, v370
-    v372 = cast v371 as u8
-    enable_side_effects v371
-    v373 = unchecked_mul v367, v372
-    constrain v373 == u8 0
-    v374 = not v371
-    v375 = mul v374, v364
-    v376 = unchecked_add v371, v375
-    enable_side_effects u1 1
-    constrain v376 == u1 1
-    v377 = cast v184 as Field
-    v378 = cast v367 as Field
-    v379 = cast v172 as Field
-    v381 = mul v379, Field 256
-    v382 = add v377, v381
-    v383 = cast v360 as Field
-    v384 = mul v383, Field 256
-    v385 = add v378, v384
-    v386 = cast v161 as Field
-    v388 = mul v386, Field 65536
-    v389 = add v382, v388
-    v390 = cast v351 as Field
-    v391 = mul v390, Field 65536
-    v392 = add v385, v391
-    v393 = cast v149 as Field
-    v395 = mul v393, Field 16777216
-    v396 = add v389, v395
-    v397 = cast v339 as Field
-    v398 = mul v397, Field 16777216
-    v399 = add v392, v398
-    v400 = cast v137 as Field
-    v402 = mul v400, Field 4294967296
-    v403 = add v396, v402
-    v404 = cast v327 as Field
-    v405 = mul v404, Field 4294967296
-    v406 = add v399, v405
-    v407 = cast v125 as Field
-    v409 = mul v407, Field 1099511627776
-    v410 = add v403, v409
-    v411 = cast v315 as Field
-    v412 = mul v411, Field 1099511627776
-    v413 = add v406, v412
-    v414 = cast v113 as Field
-    v416 = mul v414, Field 281474976710656
-    v417 = add v410, v416
-    v418 = cast v304 as Field
-    v419 = mul v418, Field 281474976710656
-    v420 = add v413, v419
-    v421 = cast v101 as Field
-    v423 = mul v421, Field 72057594037927936
-    v424 = add v417, v423
-    v425 = cast v292 as Field
-    v426 = mul v425, Field 72057594037927936
-    v427 = add v420, v426
-    v428 = cast v89 as Field
-    v430 = mul v428, Field 18446744073709551616
-    v431 = add v424, v430
-    v432 = cast v280 as Field
-    v433 = mul v432, Field 18446744073709551616
-    v434 = add v427, v433
-    v435 = cast v77 as Field
-    v437 = mul v435, Field 4722366482869645213696
-    v438 = add v431, v437
-    v439 = cast v268 as Field
-    v440 = mul v439, Field 4722366482869645213696
-    v441 = add v434, v440
-    v442 = cast v65 as Field
-    v444 = mul v442, Field 1208925819614629174706176
-    v445 = add v438, v444
-    v446 = cast v256 as Field
-    v447 = mul v446, Field 1208925819614629174706176
-    v448 = add v441, v447
-    v449 = cast v53 as Field
-    v451 = mul v449, Field 309485009821345068724781056
-    v452 = add v445, v451
-    v453 = cast v244 as Field
-    v454 = mul v453, Field 309485009821345068724781056
-    v455 = add v448, v454
-    v456 = cast v41 as Field
-    v458 = mul v456, Field 79228162514264337593543950336
-    v459 = add v452, v458
-    v460 = cast v232 as Field
-    v461 = mul v460, Field 79228162514264337593543950336
-    v462 = add v455, v461
-    v463 = cast v29 as Field
-    v465 = mul v463, Field 20282409603651670423947251286016
-    v466 = add v459, v465
-    v467 = cast v220 as Field
-    v468 = mul v467, Field 20282409603651670423947251286016
-    v469 = add v462, v468
-    v470 = cast v16 as Field
-    v472 = mul v470, Field 5192296858534827628530496329220096
-    v473 = add v466, v472
-    v474 = cast v208 as Field
-    v475 = mul v474, Field 5192296858534827628530496329220096
-    v476 = add v469, v475
-    v477 = cast v9 as Field
-    v479 = mul v477, Field 1329227995784915872903807060280344576
-    v480 = add v473, v479
-    v481 = cast v196 as Field
-    v482 = mul v481, Field 1329227995784915872903807060280344576
-    v483 = add v476, v482
-    v485 = mul v480, Field 340282366920938463463374607431768211456
-    v486 = add v483, v485
-    v488 = eq v4, Field 0
-    v489 = not v488
-    enable_side_effects v489
-    v491 = call f1(v4, Field 0) -> u1
-    v492 = mul v489, v491
-    enable_side_effects v492
-    v494, v495 = call f3(Field 0) -> (Field, Field)
-    v496 = cast v492 as Field
-    v497 = mul v494, v496
-    range_check v497 to 128 bits
-    v498 = mul v495, v496
-    range_check v498 to 128 bits
-    v499 = mul Field 340282366920938463463374607431768211456, v495
-    v500 = add v494, v499
-    v501 = mul v500, v496
-    constrain Field 0 == v501
-    v504 = call f2(Field 53438638232309528389504892708671455233, v494) -> u1
-    v505 = sub Field 53438638232309528389504892708671455233, v494
-    v507 = sub v505, Field 1
-    v508 = cast v504 as Field
-    v509 = mul v508, Field 340282366920938463463374607431768211456
-    v510 = add v507, v509
-    v512 = sub Field 64323764613183177041862057485226039389, v495
-    v513 = sub v512, v508
-    v514 = mul v510, v496
-    range_check v514 to 128 bits
-    v515 = mul v513, v496
-    range_check v515 to 128 bits
-    v517, v518 = call f3(v4) -> (Field, Field)
-    v519 = mul v517, v496
-    range_check v519 to 128 bits
-    v520 = mul v518, v496
-    range_check v520 to 128 bits
-    v521 = mul Field 340282366920938463463374607431768211456, v518
-    v522 = add v517, v521
-    v523 = mul v4, v496
-    v524 = mul v522, v496
-    constrain v523 == v524
-    v526 = call f2(Field 53438638232309528389504892708671455233, v517) -> u1
-    v527 = sub Field 53438638232309528389504892708671455233, v517
-    v528 = sub v527, Field 1
-    v529 = cast v526 as Field
-    v530 = mul v529, Field 340282366920938463463374607431768211456
-    v531 = add v528, v530
-    v532 = sub Field 64323764613183177041862057485226039389, v518
-    v533 = sub v532, v529
-    v534 = mul v531, v496
-    range_check v534 to 128 bits
-    v535 = mul v533, v496
-    range_check v535 to 128 bits
-    v537 = call f2(v494, v517) -> u1
-    v538 = sub v494, v517
-    v539 = sub v538, Field 1
-    v540 = cast v537 as Field
-    v541 = mul v540, Field 340282366920938463463374607431768211456
-    v542 = add v539, v541
-    v543 = sub v495, v518
-    v544 = sub v543, v540
-    v545 = mul v542, v496
-    range_check v545 to 128 bits
-    v546 = mul v544, v496
-    range_check v546 to 128 bits
-    v547 = not v491
-    v548 = mul v489, v547
-    enable_side_effects v548
-    v550, v551 = call f3(v4) -> (Field, Field)
-    v552 = cast v548 as Field
-    v553 = mul v550, v552
-    range_check v553 to 128 bits
-    v554 = mul v551, v552
-    range_check v554 to 128 bits
-    v555 = mul Field 340282366920938463463374607431768211456, v551
-    v556 = add v550, v555
-    v557 = mul v4, v552
-    v558 = mul v556, v552
-    constrain v557 == v558
-    v560 = call f2(Field 53438638232309528389504892708671455233, v550) -> u1
-    v561 = sub Field 53438638232309528389504892708671455233, v550
-    v562 = sub v561, Field 1
-    v563 = cast v560 as Field
-    v564 = mul v563, Field 340282366920938463463374607431768211456
-    v565 = add v562, v564
-    v566 = sub Field 64323764613183177041862057485226039389, v551
-    v567 = sub v566, v563
-    v568 = mul v565, v552
-    range_check v568 to 128 bits
-    v569 = mul v567, v552
-    range_check v569 to 128 bits
-    v571, v572 = call f3(Field 0) -> (Field, Field)
-    v573 = mul v571, v552
-    range_check v573 to 128 bits
-    v574 = mul v572, v552
-    range_check v574 to 128 bits
-    v575 = mul Field 340282366920938463463374607431768211456, v572
-    v576 = add v571, v575
-    v577 = mul v576, v552
-    constrain Field 0 == v577
-    v579 = call f2(Field 53438638232309528389504892708671455233, v571) -> u1
-    v580 = sub Field 53438638232309528389504892708671455233, v571
-    v581 = sub v580, Field 1
-    v582 = cast v579 as Field
-    v583 = mul v582, Field 340282366920938463463374607431768211456
-    v584 = add v581, v583
-    v585 = sub Field 64323764613183177041862057485226039389, v572
-    v586 = sub v585, v582
-    v587 = mul v584, v552
-    range_check v587 to 128 bits
-    v588 = mul v586, v552
-    range_check v588 to 128 bits
-    v590 = call f2(v550, v571) -> u1
-    v591 = sub v550, v571
-    v592 = sub v591, Field 1
-    v593 = cast v590 as Field
-    v594 = mul v593, Field 340282366920938463463374607431768211456
-    v595 = add v592, v594
-    v596 = sub v551, v572
-    v597 = sub v596, v593
-    v598 = mul v595, v552
-    range_check v598 to 128 bits
-    v599 = mul v597, v552
-    range_check v599 to 128 bits
-    enable_side_effects u1 1
-    v600 = sub v552, v486
-    return v600
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = truncate v4 to 64 bits, max_bit_size: 254
-    v6 = sub v4, v5
-    v7 = div v6, Field 18446744073709551616
-    v8 = truncate v7 to 64 bits, max_bit_size: 254
-    v9 = sub v7, v8
-    v10 = div v9, Field 18446744073709551616
-    v11 = mul v8, Field 18446744073709551616
-    v12 = add v11, v5
-    return v12, v10
-}
-
-After Inlining Brillig Calls Inlining:
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v7 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v9 = array_get v7, index u32 0 -> u8
-    v11 = eq v9, u8 48
-    v12 = not v11
-    v13 = lt v9, u8 48
-    enable_side_effects v12
-    v14 = mul v13, v12
-    constrain v14 == v12
-    enable_side_effects v11
-    v16 = array_get v7, index u32 1 -> u8
-    v18 = eq v16, u8 100
-    v19 = not v18
-    v20 = mul v11, v19
-    v21 = lt v16, u8 100
-    enable_side_effects v20
-    v22 = mul v21, v20
-    constrain v22 == v20
-    v23 = not v20
-    v24 = mul v23, v12
-    v25 = unchecked_add v20, v24
-    enable_side_effects u1 1
-    v27 = not v25
-    enable_side_effects v27
-    v29 = array_get v7, index u32 2 -> u8
-    v31 = eq v29, u8 78
-    v32 = not v31
-    v33 = mul v27, v32
-    v34 = lt v29, u8 78
-    enable_side_effects v33
-    v35 = mul v34, v33
-    constrain v35 == v33
-    v36 = not v33
-    v37 = mul v36, v25
-    v38 = unchecked_add v33, v37
-    enable_side_effects u1 1
-    v39 = not v38
-    enable_side_effects v39
-    v41 = array_get v7, index u32 3 -> u8
-    v43 = eq v41, u8 114
-    v44 = not v43
-    v45 = mul v39, v44
-    v46 = lt v41, u8 114
-    enable_side_effects v45
-    v47 = mul v46, v45
-    constrain v47 == v45
-    v48 = not v45
-    v49 = mul v48, v38
-    v50 = unchecked_add v45, v49
-    enable_side_effects u1 1
-    v51 = not v50
-    enable_side_effects v51
-    v53 = array_get v7, index u32 4 -> u8
-    v55 = eq v53, u8 225
-    v56 = not v55
-    v57 = mul v51, v56
-    v58 = lt v53, u8 225
-    enable_side_effects v57
-    v59 = mul v58, v57
-    constrain v59 == v57
-    v60 = not v57
-    v61 = mul v60, v50
-    v62 = unchecked_add v57, v61
-    enable_side_effects u1 1
-    v63 = not v62
-    enable_side_effects v63
-    v65 = array_get v7, index u32 5 -> u8
-    v67 = eq v65, u8 49
-    v68 = not v67
-    v69 = mul v63, v68
-    v70 = lt v65, u8 49
-    enable_side_effects v69
-    v71 = mul v70, v69
-    constrain v71 == v69
-    v72 = not v69
-    v73 = mul v72, v62
-    v74 = unchecked_add v69, v73
-    enable_side_effects u1 1
-    v75 = not v74
-    enable_side_effects v75
-    v77 = array_get v7, index u32 6 -> u8
-    v79 = eq v77, u8 160
-    v80 = not v79
-    v81 = mul v75, v80
-    v82 = lt v77, u8 160
-    enable_side_effects v81
-    v83 = mul v82, v81
-    constrain v83 == v81
-    v84 = not v81
-    v85 = mul v84, v74
-    v86 = unchecked_add v81, v85
-    enable_side_effects u1 1
-    v87 = not v86
-    enable_side_effects v87
-    v89 = array_get v7, index u32 7 -> u8
-    v91 = eq v89, u8 41
-    v92 = not v91
-    v93 = mul v87, v92
-    v94 = lt v89, u8 41
-    enable_side_effects v93
-    v95 = mul v94, v93
-    constrain v95 == v93
-    v96 = not v93
-    v97 = mul v96, v86
-    v98 = unchecked_add v93, v97
-    enable_side_effects u1 1
-    v99 = not v98
-    enable_side_effects v99
-    v101 = array_get v7, index u32 8 -> u8
-    v103 = eq v101, u8 184
-    v104 = not v103
-    v105 = mul v99, v104
-    v106 = lt v101, u8 184
-    enable_side_effects v105
-    v107 = mul v106, v105
-    constrain v107 == v105
-    v108 = not v105
-    v109 = mul v108, v98
-    v110 = unchecked_add v105, v109
-    enable_side_effects u1 1
-    v111 = not v110
-    enable_side_effects v111
-    v113 = array_get v7, index u32 9 -> u8
-    v115 = eq v113, u8 80
-    v116 = not v115
-    v117 = mul v111, v116
-    v118 = lt v113, u8 80
-    enable_side_effects v117
-    v119 = mul v118, v117
-    constrain v119 == v117
-    v120 = not v117
-    v121 = mul v120, v110
-    v122 = unchecked_add v117, v121
-    enable_side_effects u1 1
-    v123 = not v122
-    enable_side_effects v123
-    v125 = array_get v7, index u32 10 -> u8
-    v127 = eq v125, u8 69
-    v128 = not v127
-    v129 = mul v123, v128
-    v130 = lt v125, u8 69
-    enable_side_effects v129
-    v131 = mul v130, v129
-    constrain v131 == v129
-    v132 = not v129
-    v133 = mul v132, v122
-    v134 = unchecked_add v129, v133
-    enable_side_effects u1 1
-    v135 = not v134
-    enable_side_effects v135
-    v137 = array_get v7, index u32 11 -> u8
-    v139 = eq v137, u8 182
-    v140 = not v139
-    v141 = mul v135, v140
-    v142 = lt v137, u8 182
-    enable_side_effects v141
-    v143 = mul v142, v141
-    constrain v143 == v141
-    v144 = not v141
-    v145 = mul v144, v134
-    v146 = unchecked_add v141, v145
-    enable_side_effects u1 1
-    v147 = not v146
-    enable_side_effects v147
-    v149 = array_get v7, index u32 12 -> u8
-    v151 = eq v149, u8 129
-    v152 = not v151
-    v153 = mul v147, v152
-    v154 = lt v149, u8 129
-    enable_side_effects v153
-    v155 = mul v154, v153
-    constrain v155 == v153
-    v156 = not v153
-    v157 = mul v156, v146
-    v158 = unchecked_add v153, v157
-    enable_side_effects u1 1
-    v159 = not v158
-    enable_side_effects v159
-    v161 = array_get v7, index u32 13 -> u8
-    v162 = eq v161, u8 129
-    v163 = not v162
-    v164 = mul v159, v163
-    v165 = lt v161, u8 129
-    enable_side_effects v164
-    v166 = mul v165, v164
-    constrain v166 == v164
-    v167 = not v164
-    v168 = mul v167, v158
-    v169 = unchecked_add v164, v168
-    enable_side_effects u1 1
-    v170 = not v169
-    enable_side_effects v170
-    v172 = array_get v7, index u32 14 -> u8
-    v174 = eq v172, u8 88
-    v175 = not v174
-    v176 = mul v170, v175
-    v177 = lt v172, u8 88
-    enable_side_effects v176
-    v178 = mul v177, v176
-    constrain v178 == v176
-    v179 = not v176
-    v180 = mul v179, v169
-    v181 = unchecked_add v176, v180
-    enable_side_effects u1 1
-    v182 = not v181
-    enable_side_effects v182
-    v184 = array_get v7, index u32 15 -> u8
-    v186 = eq v184, u8 93
-    v187 = not v186
-    v188 = mul v182, v187
-    v189 = lt v184, u8 93
-    enable_side_effects v188
-    v190 = mul v189, v188
-    constrain v190 == v188
-    v191 = not v188
-    v192 = mul v191, v181
-    v193 = unchecked_add v188, v192
-    enable_side_effects u1 1
-    v194 = not v193
-    enable_side_effects v194
-    v196 = array_get v7, index u32 16 -> u8
-    v198 = eq v196, u8 40
-    v199 = not v198
-    v200 = mul v194, v199
-    v201 = lt v196, u8 40
-    enable_side_effects v200
-    v202 = mul v201, v200
-    constrain v202 == v200
-    v203 = not v200
-    v204 = mul v203, v193
-    v205 = unchecked_add v200, v204
-    enable_side_effects u1 1
-    v206 = not v205
-    enable_side_effects v206
-    v208 = array_get v7, index u32 17 -> u8
-    v210 = eq v208, u8 51
-    v211 = not v210
-    v212 = mul v206, v211
-    v213 = lt v208, u8 51
-    enable_side_effects v212
-    v214 = mul v213, v212
-    constrain v214 == v212
-    v215 = not v212
-    v216 = mul v215, v205
-    v217 = unchecked_add v212, v216
-    enable_side_effects u1 1
-    v218 = not v217
-    enable_side_effects v218
-    v220 = array_get v7, index u32 18 -> u8
-    v222 = eq v220, u8 232
-    v223 = not v222
-    v224 = mul v218, v223
-    v225 = lt v220, u8 232
-    enable_side_effects v224
-    v226 = mul v225, v224
-    constrain v226 == v224
-    v227 = not v224
-    v228 = mul v227, v217
-    v229 = unchecked_add v224, v228
-    enable_side_effects u1 1
-    v230 = not v229
-    enable_side_effects v230
-    v232 = array_get v7, index u32 19 -> u8
-    v234 = eq v232, u8 72
-    v235 = not v234
-    v236 = mul v230, v235
-    v237 = lt v232, u8 72
-    enable_side_effects v236
-    v238 = mul v237, v236
-    constrain v238 == v236
-    v239 = not v236
-    v240 = mul v239, v229
-    v241 = unchecked_add v236, v240
-    enable_side_effects u1 1
-    v242 = not v241
-    enable_side_effects v242
-    v244 = array_get v7, index u32 20 -> u8
-    v246 = eq v244, u8 121
-    v247 = not v246
-    v248 = mul v242, v247
-    v249 = lt v244, u8 121
-    enable_side_effects v248
-    v250 = mul v249, v248
-    constrain v250 == v248
-    v251 = not v248
-    v252 = mul v251, v241
-    v253 = unchecked_add v248, v252
-    enable_side_effects u1 1
-    v254 = not v253
-    enable_side_effects v254
-    v256 = array_get v7, index u32 21 -> u8
-    v258 = eq v256, u8 185
-    v259 = not v258
-    v260 = mul v254, v259
-    v261 = lt v256, u8 185
-    enable_side_effects v260
-    v262 = mul v261, v260
-    constrain v262 == v260
-    v263 = not v260
-    v264 = mul v263, v253
-    v265 = unchecked_add v260, v264
-    enable_side_effects u1 1
-    v266 = not v265
-    enable_side_effects v266
-    v268 = array_get v7, index u32 22 -> u8
-    v270 = eq v268, u8 112
-    v271 = not v270
-    v272 = mul v266, v271
-    v273 = lt v268, u8 112
-    enable_side_effects v272
-    v274 = mul v273, v272
-    constrain v274 == v272
-    v275 = not v272
-    v276 = mul v275, v265
-    v277 = unchecked_add v272, v276
-    enable_side_effects u1 1
-    v278 = not v277
-    enable_side_effects v278
-    v280 = array_get v7, index u32 23 -> u8
-    v282 = eq v280, u8 145
-    v283 = not v282
-    v284 = mul v278, v283
-    v285 = lt v280, u8 145
-    enable_side_effects v284
-    v286 = mul v285, v284
-    constrain v286 == v284
-    v287 = not v284
-    v288 = mul v287, v277
-    v289 = unchecked_add v284, v288
-    enable_side_effects u1 1
-    v290 = not v289
-    enable_side_effects v290
-    v292 = array_get v7, index u32 24 -> u8
-    v294 = eq v292, u8 67
-    v295 = not v294
-    v296 = mul v290, v295
-    v297 = lt v292, u8 67
-    enable_side_effects v296
-    v298 = mul v297, v296
-    constrain v298 == v296
-    v299 = not v296
-    v300 = mul v299, v289
-    v301 = unchecked_add v296, v300
-    enable_side_effects u1 1
-    v302 = not v301
-    enable_side_effects v302
-    v304 = array_get v7, index u32 25 -> u8
-    v305 = eq v304, u8 225
-    v306 = not v305
-    v307 = mul v302, v306
-    v308 = lt v304, u8 225
-    enable_side_effects v307
-    v309 = mul v308, v307
-    constrain v309 == v307
-    v310 = not v307
-    v311 = mul v310, v301
-    v312 = unchecked_add v307, v311
-    enable_side_effects u1 1
-    v313 = not v312
-    enable_side_effects v313
-    v315 = array_get v7, index u32 26 -> u8
-    v317 = eq v315, u8 245
-    v318 = not v317
-    v319 = mul v313, v318
-    v320 = lt v315, u8 245
-    enable_side_effects v319
-    v321 = mul v320, v319
-    constrain v321 == v319
-    v322 = not v319
-    v323 = mul v322, v312
-    v324 = unchecked_add v319, v323
-    enable_side_effects u1 1
-    v325 = not v324
-    enable_side_effects v325
-    v327 = array_get v7, index u32 27 -> u8
-    v329 = eq v327, u8 147
-    v330 = not v329
-    v331 = mul v325, v330
-    v332 = lt v327, u8 147
-    enable_side_effects v331
-    v333 = mul v332, v331
-    constrain v333 == v331
-    v334 = not v331
-    v335 = mul v334, v324
-    v336 = unchecked_add v331, v335
-    enable_side_effects u1 1
-    v337 = not v336
-    enable_side_effects v337
-    v339 = array_get v7, index u32 28 -> u8
-    v341 = eq v339, u8 240
-    v342 = not v341
-    v343 = mul v337, v342
-    v344 = lt v339, u8 240
-    enable_side_effects v343
-    v345 = mul v344, v343
-    constrain v345 == v343
-    v346 = not v343
-    v347 = mul v346, v336
-    v348 = unchecked_add v343, v347
-    enable_side_effects u1 1
-    v349 = not v348
-    enable_side_effects v349
-    v351 = array_get v7, index u32 29 -> u8
-    v353 = eq v351, u8 0
-    v354 = not v353
-    v355 = mul v349, v354
-    constrain u1 0 == v355
-    enable_side_effects u1 0
-    v357 = unchecked_add v355, v348
-    enable_side_effects u1 1
-    v358 = not v357
-    enable_side_effects v358
-    v360 = array_get v7, index u32 30 -> u8
-    v361 = eq v360, u8 0
-    v362 = not v361
-    v363 = mul v358, v362
-    constrain u1 0 == v363
-    enable_side_effects u1 0
-    v364 = unchecked_add v363, v357
-    enable_side_effects u1 1
-    v365 = not v364
-    enable_side_effects v365
-    v367 = array_get v7, index u32 31 -> u8
-    v369 = eq v367, u8 1
-    v370 = not v369
-    v371 = mul v365, v370
-    v372 = cast v371 as u8
-    enable_side_effects v371
-    v373 = unchecked_mul v367, v372
-    constrain v373 == u8 0
-    v374 = not v371
-    v375 = mul v374, v364
-    v376 = unchecked_add v371, v375
-    enable_side_effects u1 1
-    constrain v376 == u1 1
-    v377 = cast v184 as Field
-    v378 = cast v367 as Field
-    v379 = cast v172 as Field
-    v381 = mul v379, Field 256
-    v382 = add v377, v381
-    v383 = cast v360 as Field
-    v384 = mul v383, Field 256
-    v385 = add v378, v384
-    v386 = cast v161 as Field
-    v388 = mul v386, Field 65536
-    v389 = add v382, v388
-    v390 = cast v351 as Field
-    v391 = mul v390, Field 65536
-    v392 = add v385, v391
-    v393 = cast v149 as Field
-    v395 = mul v393, Field 16777216
-    v396 = add v389, v395
-    v397 = cast v339 as Field
-    v398 = mul v397, Field 16777216
-    v399 = add v392, v398
-    v400 = cast v137 as Field
-    v402 = mul v400, Field 4294967296
-    v403 = add v396, v402
-    v404 = cast v327 as Field
-    v405 = mul v404, Field 4294967296
-    v406 = add v399, v405
-    v407 = cast v125 as Field
-    v409 = mul v407, Field 1099511627776
-    v410 = add v403, v409
-    v411 = cast v315 as Field
-    v412 = mul v411, Field 1099511627776
-    v413 = add v406, v412
-    v414 = cast v113 as Field
-    v416 = mul v414, Field 281474976710656
-    v417 = add v410, v416
-    v418 = cast v304 as Field
-    v419 = mul v418, Field 281474976710656
-    v420 = add v413, v419
-    v421 = cast v101 as Field
-    v423 = mul v421, Field 72057594037927936
-    v424 = add v417, v423
-    v425 = cast v292 as Field
-    v426 = mul v425, Field 72057594037927936
-    v427 = add v420, v426
-    v428 = cast v89 as Field
-    v430 = mul v428, Field 18446744073709551616
-    v431 = add v424, v430
-    v432 = cast v280 as Field
-    v433 = mul v432, Field 18446744073709551616
-    v434 = add v427, v433
-    v435 = cast v77 as Field
-    v437 = mul v435, Field 4722366482869645213696
-    v438 = add v431, v437
-    v439 = cast v268 as Field
-    v440 = mul v439, Field 4722366482869645213696
-    v441 = add v434, v440
-    v442 = cast v65 as Field
-    v444 = mul v442, Field 1208925819614629174706176
-    v445 = add v438, v444
-    v446 = cast v256 as Field
-    v447 = mul v446, Field 1208925819614629174706176
-    v448 = add v441, v447
-    v449 = cast v53 as Field
-    v451 = mul v449, Field 309485009821345068724781056
-    v452 = add v445, v451
-    v453 = cast v244 as Field
-    v454 = mul v453, Field 309485009821345068724781056
-    v455 = add v448, v454
-    v456 = cast v41 as Field
-    v458 = mul v456, Field 79228162514264337593543950336
-    v459 = add v452, v458
-    v460 = cast v232 as Field
-    v461 = mul v460, Field 79228162514264337593543950336
-    v462 = add v455, v461
-    v463 = cast v29 as Field
-    v465 = mul v463, Field 20282409603651670423947251286016
-    v466 = add v459, v465
-    v467 = cast v220 as Field
-    v468 = mul v467, Field 20282409603651670423947251286016
-    v469 = add v462, v468
-    v470 = cast v16 as Field
-    v472 = mul v470, Field 5192296858534827628530496329220096
-    v473 = add v466, v472
-    v474 = cast v208 as Field
-    v475 = mul v474, Field 5192296858534827628530496329220096
-    v476 = add v469, v475
-    v477 = cast v9 as Field
-    v479 = mul v477, Field 1329227995784915872903807060280344576
-    v480 = add v473, v479
-    v481 = cast v196 as Field
-    v482 = mul v481, Field 1329227995784915872903807060280344576
-    v483 = add v476, v482
-    v485 = mul v480, Field 340282366920938463463374607431768211456
-    v486 = add v483, v485
-    v488 = eq v4, Field 0
-    v489 = not v488
-    enable_side_effects v489
-    v491 = call f1(v4, Field 0) -> u1
-    v492 = mul v489, v491
-    enable_side_effects v492
-    v493 = cast v492 as Field
-    v495 = mul Field 53438638232309528389504892708671455232, v493
-    range_check v495 to 128 bits
-    v497 = mul Field 64323764613183177041862057485226039389, v493
-    range_check v497 to 128 bits
-    v499, v500 = call f3(v4) -> (Field, Field)
-    v501 = mul v499, v493
-    range_check v501 to 128 bits
-    v502 = mul v500, v493
-    range_check v502 to 128 bits
-    v503 = mul Field 340282366920938463463374607431768211456, v500
-    v504 = add v499, v503
-    v505 = mul v4, v493
-    v506 = mul v504, v493
-    constrain v505 == v506
-    v509 = call f2(Field 53438638232309528389504892708671455233, v499) -> u1
-    v510 = sub Field 53438638232309528389504892708671455233, v499
-    v512 = sub v510, Field 1
-    v513 = cast v509 as Field
-    v514 = mul v513, Field 340282366920938463463374607431768211456
-    v515 = add v512, v514
-    v516 = sub Field 64323764613183177041862057485226039389, v500
-    v517 = sub v516, v513
-    v518 = mul v515, v493
-    range_check v518 to 128 bits
-    v519 = mul v517, v493
-    range_check v519 to 128 bits
-    v521 = call f2(Field 0, v499) -> u1
-    v522 = sub Field 0, v499
-    v523 = sub v522, Field 1
-    v524 = cast v521 as Field
-    v525 = mul v524, Field 340282366920938463463374607431768211456
-    v526 = add v523, v525
-    v527 = sub Field 0, v500
-    v528 = sub v527, v524
-    v529 = mul v526, v493
-    range_check v529 to 128 bits
-    v530 = mul v528, v493
-    range_check v530 to 128 bits
-    v531 = not v491
-    v532 = mul v489, v531
-    enable_side_effects v532
-    v534, v535 = call f3(v4) -> (Field, Field)
-    v536 = cast v532 as Field
-    v537 = mul v534, v536
-    range_check v537 to 128 bits
-    v538 = mul v535, v536
-    range_check v538 to 128 bits
-    v539 = mul Field 340282366920938463463374607431768211456, v535
-    v540 = add v534, v539
-    v541 = mul v4, v536
-    v542 = mul v540, v536
-    constrain v541 == v542
-    v544 = call f2(Field 53438638232309528389504892708671455233, v534) -> u1
-    v545 = sub Field 53438638232309528389504892708671455233, v534
-    v546 = sub v545, Field 1
-    v547 = cast v544 as Field
-    v548 = mul v547, Field 340282366920938463463374607431768211456
-    v549 = add v546, v548
-    v550 = sub Field 64323764613183177041862057485226039389, v535
-    v551 = sub v550, v547
-    v552 = mul v549, v536
-    range_check v552 to 128 bits
-    v553 = mul v551, v536
-    range_check v553 to 128 bits
-    v554 = mul Field 53438638232309528389504892708671455232, v536
-    range_check v554 to 128 bits
-    v555 = mul Field 64323764613183177041862057485226039389, v536
-    range_check v555 to 128 bits
-    v557 = call f2(v534, Field 0) -> u1
-    v558 = sub v534, Field 1
-    v559 = cast v557 as Field
-    v560 = mul v559, Field 340282366920938463463374607431768211456
-    v561 = add v558, v560
-    v562 = sub v535, v559
-    v563 = mul v561, v536
-    range_check v563 to 128 bits
-    v564 = mul v562, v536
-    range_check v564 to 128 bits
-    enable_side_effects u1 1
-    v565 = sub v536, v486
-    return v565
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = truncate v4 to 64 bits, max_bit_size: 254
-    v6 = sub v4, v5
-    v7 = div v6, Field 18446744073709551616
-    v8 = truncate v7 to 64 bits, max_bit_size: 254
-    v9 = sub v7, v8
-    v10 = div v9, Field 18446744073709551616
-    v11 = mul v8, Field 18446744073709551616
-    v12 = add v11, v5
-    return v12, v10
-}
-
-After Dead Instruction Elimination (2nd):
-g0 = Field 340282366920938463463374607431768211456
-g1 = Field 53438638232309528389504892708671455233
-g2 = Field 64323764613183177041862057485226039389
-g3 = Field 18446744073709551616
-
-acir(inline) fn main f0 {
-  b0(v4: Field):
-    v7 = call to_be_radix(v4, u32 256) -> [u8; 32]
-    v9 = array_get v7, index u32 0 -> u8
-    v11 = eq v9, u8 48
-    v12 = not v11
-    v13 = lt v9, u8 48
-    enable_side_effects v12
-    v14 = mul v13, v12
-    constrain v14 == v12
-    enable_side_effects v11
-    v16 = array_get v7, index u32 1 -> u8
-    v18 = eq v16, u8 100
-    v19 = not v18
-    v20 = mul v11, v19
-    v21 = lt v16, u8 100
-    enable_side_effects v20
-    v22 = mul v21, v20
-    constrain v22 == v20
-    v23 = not v20
-    v24 = mul v23, v12
-    v25 = unchecked_add v20, v24
-    enable_side_effects u1 1
-    v27 = not v25
-    enable_side_effects v27
-    v29 = array_get v7, index u32 2 -> u8
-    v31 = eq v29, u8 78
-    v32 = not v31
-    v33 = mul v27, v32
-    v34 = lt v29, u8 78
-    enable_side_effects v33
-    v35 = mul v34, v33
-    constrain v35 == v33
-    v36 = not v33
-    v37 = mul v36, v25
-    v38 = unchecked_add v33, v37
-    enable_side_effects u1 1
-    v39 = not v38
-    enable_side_effects v39
-    v41 = array_get v7, index u32 3 -> u8
-    v43 = eq v41, u8 114
-    v44 = not v43
-    v45 = mul v39, v44
-    v46 = lt v41, u8 114
-    enable_side_effects v45
-    v47 = mul v46, v45
-    constrain v47 == v45
-    v48 = not v45
-    v49 = mul v48, v38
-    v50 = unchecked_add v45, v49
-    enable_side_effects u1 1
-    v51 = not v50
-    enable_side_effects v51
-    v53 = array_get v7, index u32 4 -> u8
-    v55 = eq v53, u8 225
-    v56 = not v55
-    v57 = mul v51, v56
-    v58 = lt v53, u8 225
-    enable_side_effects v57
-    v59 = mul v58, v57
-    constrain v59 == v57
-    v60 = not v57
-    v61 = mul v60, v50
-    v62 = unchecked_add v57, v61
-    enable_side_effects u1 1
-    v63 = not v62
-    enable_side_effects v63
-    v65 = array_get v7, index u32 5 -> u8
-    v67 = eq v65, u8 49
-    v68 = not v67
-    v69 = mul v63, v68
-    v70 = lt v65, u8 49
-    enable_side_effects v69
-    v71 = mul v70, v69
-    constrain v71 == v69
-    v72 = not v69
-    v73 = mul v72, v62
-    v74 = unchecked_add v69, v73
-    enable_side_effects u1 1
-    v75 = not v74
-    enable_side_effects v75
-    v77 = array_get v7, index u32 6 -> u8
-    v79 = eq v77, u8 160
-    v80 = not v79
-    v81 = mul v75, v80
-    v82 = lt v77, u8 160
-    enable_side_effects v81
-    v83 = mul v82, v81
-    constrain v83 == v81
-    v84 = not v81
-    v85 = mul v84, v74
-    v86 = unchecked_add v81, v85
-    enable_side_effects u1 1
-    v87 = not v86
-    enable_side_effects v87
-    v89 = array_get v7, index u32 7 -> u8
-    v91 = eq v89, u8 41
-    v92 = not v91
-    v93 = mul v87, v92
-    v94 = lt v89, u8 41
-    enable_side_effects v93
-    v95 = mul v94, v93
-    constrain v95 == v93
-    v96 = not v93
-    v97 = mul v96, v86
-    v98 = unchecked_add v93, v97
-    enable_side_effects u1 1
-    v99 = not v98
-    enable_side_effects v99
-    v101 = array_get v7, index u32 8 -> u8
-    v103 = eq v101, u8 184
-    v104 = not v103
-    v105 = mul v99, v104
-    v106 = lt v101, u8 184
-    enable_side_effects v105
-    v107 = mul v106, v105
-    constrain v107 == v105
-    v108 = not v105
-    v109 = mul v108, v98
-    v110 = unchecked_add v105, v109
-    enable_side_effects u1 1
-    v111 = not v110
-    enable_side_effects v111
-    v113 = array_get v7, index u32 9 -> u8
-    v115 = eq v113, u8 80
-    v116 = not v115
-    v117 = mul v111, v116
-    v118 = lt v113, u8 80
-    enable_side_effects v117
-    v119 = mul v118, v117
-    constrain v119 == v117
-    v120 = not v117
-    v121 = mul v120, v110
-    v122 = unchecked_add v117, v121
-    enable_side_effects u1 1
-    v123 = not v122
-    enable_side_effects v123
-    v125 = array_get v7, index u32 10 -> u8
-    v127 = eq v125, u8 69
-    v128 = not v127
-    v129 = mul v123, v128
-    v130 = lt v125, u8 69
-    enable_side_effects v129
-    v131 = mul v130, v129
-    constrain v131 == v129
-    v132 = not v129
-    v133 = mul v132, v122
-    v134 = unchecked_add v129, v133
-    enable_side_effects u1 1
-    v135 = not v134
-    enable_side_effects v135
-    v137 = array_get v7, index u32 11 -> u8
-    v139 = eq v137, u8 182
-    v140 = not v139
-    v141 = mul v135, v140
-    v142 = lt v137, u8 182
-    enable_side_effects v141
-    v143 = mul v142, v141
-    constrain v143 == v141
-    v144 = not v141
-    v145 = mul v144, v134
-    v146 = unchecked_add v141, v145
-    enable_side_effects u1 1
-    v147 = not v146
-    enable_side_effects v147
-    v149 = array_get v7, index u32 12 -> u8
-    v151 = eq v149, u8 129
-    v152 = not v151
-    v153 = mul v147, v152
-    v154 = lt v149, u8 129
-    enable_side_effects v153
-    v155 = mul v154, v153
-    constrain v155 == v153
-    v156 = not v153
-    v157 = mul v156, v146
-    v158 = unchecked_add v153, v157
-    enable_side_effects u1 1
-    v159 = not v158
-    enable_side_effects v159
-    v161 = array_get v7, index u32 13 -> u8
-    v162 = eq v161, u8 129
-    v163 = not v162
-    v164 = mul v159, v163
-    v165 = lt v161, u8 129
-    enable_side_effects v164
-    v166 = mul v165, v164
-    constrain v166 == v164
-    v167 = not v164
-    v168 = mul v167, v158
-    v169 = unchecked_add v164, v168
-    enable_side_effects u1 1
-    v170 = not v169
-    enable_side_effects v170
-    v172 = array_get v7, index u32 14 -> u8
-    v174 = eq v172, u8 88
-    v175 = not v174
-    v176 = mul v170, v175
-    v177 = lt v172, u8 88
-    enable_side_effects v176
-    v178 = mul v177, v176
-    constrain v178 == v176
-    v179 = not v176
-    v180 = mul v179, v169
-    v181 = unchecked_add v176, v180
-    enable_side_effects u1 1
-    v182 = not v181
-    enable_side_effects v182
-    v184 = array_get v7, index u32 15 -> u8
-    v186 = eq v184, u8 93
-    v187 = not v186
-    v188 = mul v182, v187
-    v189 = lt v184, u8 93
-    enable_side_effects v188
-    v190 = mul v189, v188
-    constrain v190 == v188
-    v191 = not v188
-    v192 = mul v191, v181
-    v193 = unchecked_add v188, v192
-    enable_side_effects u1 1
-    v194 = not v193
-    enable_side_effects v194
-    v196 = array_get v7, index u32 16 -> u8
-    v198 = eq v196, u8 40
-    v199 = not v198
-    v200 = mul v194, v199
-    v201 = lt v196, u8 40
-    enable_side_effects v200
-    v202 = mul v201, v200
-    constrain v202 == v200
-    v203 = not v200
-    v204 = mul v203, v193
-    v205 = unchecked_add v200, v204
-    enable_side_effects u1 1
-    v206 = not v205
-    enable_side_effects v206
-    v208 = array_get v7, index u32 17 -> u8
-    v210 = eq v208, u8 51
-    v211 = not v210
-    v212 = mul v206, v211
-    v213 = lt v208, u8 51
-    enable_side_effects v212
-    v214 = mul v213, v212
-    constrain v214 == v212
-    v215 = not v212
-    v216 = mul v215, v205
-    v217 = unchecked_add v212, v216
-    enable_side_effects u1 1
-    v218 = not v217
-    enable_side_effects v218
-    v220 = array_get v7, index u32 18 -> u8
-    v222 = eq v220, u8 232
-    v223 = not v222
-    v224 = mul v218, v223
-    v225 = lt v220, u8 232
-    enable_side_effects v224
-    v226 = mul v225, v224
-    constrain v226 == v224
-    v227 = not v224
-    v228 = mul v227, v217
-    v229 = unchecked_add v224, v228
-    enable_side_effects u1 1
-    v230 = not v229
-    enable_side_effects v230
-    v232 = array_get v7, index u32 19 -> u8
-    v234 = eq v232, u8 72
-    v235 = not v234
-    v236 = mul v230, v235
-    v237 = lt v232, u8 72
-    enable_side_effects v236
-    v238 = mul v237, v236
-    constrain v238 == v236
-    v239 = not v236
-    v240 = mul v239, v229
-    v241 = unchecked_add v236, v240
-    enable_side_effects u1 1
-    v242 = not v241
-    enable_side_effects v242
-    v244 = array_get v7, index u32 20 -> u8
-    v246 = eq v244, u8 121
-    v247 = not v246
-    v248 = mul v242, v247
-    v249 = lt v244, u8 121
-    enable_side_effects v248
-    v250 = mul v249, v248
-    constrain v250 == v248
-    v251 = not v248
-    v252 = mul v251, v241
-    v253 = unchecked_add v248, v252
-    enable_side_effects u1 1
-    v254 = not v253
-    enable_side_effects v254
-    v256 = array_get v7, index u32 21 -> u8
-    v258 = eq v256, u8 185
-    v259 = not v258
-    v260 = mul v254, v259
-    v261 = lt v256, u8 185
-    enable_side_effects v260
-    v262 = mul v261, v260
-    constrain v262 == v260
-    v263 = not v260
-    v264 = mul v263, v253
-    v265 = unchecked_add v260, v264
-    enable_side_effects u1 1
-    v266 = not v265
-    enable_side_effects v266
-    v268 = array_get v7, index u32 22 -> u8
-    v270 = eq v268, u8 112
-    v271 = not v270
-    v272 = mul v266, v271
-    v273 = lt v268, u8 112
-    enable_side_effects v272
-    v274 = mul v273, v272
-    constrain v274 == v272
-    v275 = not v272
-    v276 = mul v275, v265
-    v277 = unchecked_add v272, v276
-    enable_side_effects u1 1
-    v278 = not v277
-    enable_side_effects v278
-    v280 = array_get v7, index u32 23 -> u8
-    v282 = eq v280, u8 145
-    v283 = not v282
-    v284 = mul v278, v283
-    v285 = lt v280, u8 145
-    enable_side_effects v284
-    v286 = mul v285, v284
-    constrain v286 == v284
-    v287 = not v284
-    v288 = mul v287, v277
-    v289 = unchecked_add v284, v288
-    enable_side_effects u1 1
-    v290 = not v289
-    enable_side_effects v290
-    v292 = array_get v7, index u32 24 -> u8
-    v294 = eq v292, u8 67
-    v295 = not v294
-    v296 = mul v290, v295
-    v297 = lt v292, u8 67
-    enable_side_effects v296
-    v298 = mul v297, v296
-    constrain v298 == v296
-    v299 = not v296
-    v300 = mul v299, v289
-    v301 = unchecked_add v296, v300
-    enable_side_effects u1 1
-    v302 = not v301
-    enable_side_effects v302
-    v304 = array_get v7, index u32 25 -> u8
-    v305 = eq v304, u8 225
-    v306 = not v305
-    v307 = mul v302, v306
-    v308 = lt v304, u8 225
-    enable_side_effects v307
-    v309 = mul v308, v307
-    constrain v309 == v307
-    v310 = not v307
-    v311 = mul v310, v301
-    v312 = unchecked_add v307, v311
-    enable_side_effects u1 1
-    v313 = not v312
-    enable_side_effects v313
-    v315 = array_get v7, index u32 26 -> u8
-    v317 = eq v315, u8 245
-    v318 = not v317
-    v319 = mul v313, v318
-    v320 = lt v315, u8 245
-    enable_side_effects v319
-    v321 = mul v320, v319
-    constrain v321 == v319
-    v322 = not v319
-    v323 = mul v322, v312
-    v324 = unchecked_add v319, v323
-    enable_side_effects u1 1
-    v325 = not v324
-    enable_side_effects v325
-    v327 = array_get v7, index u32 27 -> u8
-    v329 = eq v327, u8 147
-    v330 = not v329
-    v331 = mul v325, v330
-    v332 = lt v327, u8 147
-    enable_side_effects v331
-    v333 = mul v332, v331
-    constrain v333 == v331
-    v334 = not v331
-    v335 = mul v334, v324
-    v336 = unchecked_add v331, v335
-    enable_side_effects u1 1
-    v337 = not v336
-    enable_side_effects v337
-    v339 = array_get v7, index u32 28 -> u8
-    v341 = eq v339, u8 240
-    v342 = not v341
-    v343 = mul v337, v342
-    v344 = lt v339, u8 240
-    enable_side_effects v343
-    v345 = mul v344, v343
-    constrain v345 == v343
-    v346 = not v343
-    v347 = mul v346, v336
-    v348 = unchecked_add v343, v347
-    enable_side_effects u1 1
-    v349 = not v348
-    enable_side_effects v349
-    v351 = array_get v7, index u32 29 -> u8
-    v353 = eq v351, u8 0
-    v354 = not v353
-    v355 = mul v349, v354
-    constrain u1 0 == v355
-    enable_side_effects u1 0
-    v357 = unchecked_add v355, v348
-    enable_side_effects u1 1
-    v358 = not v357
-    enable_side_effects v358
-    v360 = array_get v7, index u32 30 -> u8
-    v361 = eq v360, u8 0
-    v362 = not v361
-    v363 = mul v358, v362
-    constrain u1 0 == v363
-    enable_side_effects u1 0
-    v364 = unchecked_add v363, v357
-    enable_side_effects u1 1
-    v365 = not v364
-    enable_side_effects v365
-    v367 = array_get v7, index u32 31 -> u8
-    v369 = eq v367, u8 1
-    v370 = not v369
-    v371 = mul v365, v370
-    v372 = cast v371 as u8
-    enable_side_effects v371
-    v373 = unchecked_mul v367, v372
-    constrain v373 == u8 0
-    v374 = not v371
-    v375 = mul v374, v364
-    v376 = unchecked_add v371, v375
-    enable_side_effects u1 1
-    constrain v376 == u1 1
-    v377 = cast v184 as Field
-    v378 = cast v367 as Field
-    v379 = cast v172 as Field
-    v381 = mul v379, Field 256
-    v382 = add v377, v381
-    v383 = cast v360 as Field
-    v384 = mul v383, Field 256
-    v385 = add v378, v384
-    v386 = cast v161 as Field
-    v388 = mul v386, Field 65536
-    v389 = add v382, v388
-    v390 = cast v351 as Field
-    v391 = mul v390, Field 65536
-    v392 = add v385, v391
-    v393 = cast v149 as Field
-    v395 = mul v393, Field 16777216
-    v396 = add v389, v395
-    v397 = cast v339 as Field
-    v398 = mul v397, Field 16777216
-    v399 = add v392, v398
-    v400 = cast v137 as Field
-    v402 = mul v400, Field 4294967296
-    v403 = add v396, v402
-    v404 = cast v327 as Field
-    v405 = mul v404, Field 4294967296
-    v406 = add v399, v405
-    v407 = cast v125 as Field
-    v409 = mul v407, Field 1099511627776
-    v410 = add v403, v409
-    v411 = cast v315 as Field
-    v412 = mul v411, Field 1099511627776
-    v413 = add v406, v412
-    v414 = cast v113 as Field
-    v416 = mul v414, Field 281474976710656
-    v417 = add v410, v416
-    v418 = cast v304 as Field
-    v419 = mul v418, Field 281474976710656
-    v420 = add v413, v419
-    v421 = cast v101 as Field
-    v423 = mul v421, Field 72057594037927936
-    v424 = add v417, v423
-    v425 = cast v292 as Field
-    v426 = mul v425, Field 72057594037927936
-    v427 = add v420, v426
-    v428 = cast v89 as Field
-    v430 = mul v428, Field 18446744073709551616
-    v431 = add v424, v430
-    v432 = cast v280 as Field
-    v433 = mul v432, Field 18446744073709551616
-    v434 = add v427, v433
-    v435 = cast v77 as Field
-    v437 = mul v435, Field 4722366482869645213696
-    v438 = add v431, v437
-    v439 = cast v268 as Field
-    v440 = mul v439, Field 4722366482869645213696
-    v441 = add v434, v440
-    v442 = cast v65 as Field
-    v444 = mul v442, Field 1208925819614629174706176
-    v445 = add v438, v444
-    v446 = cast v256 as Field
-    v447 = mul v446, Field 1208925819614629174706176
-    v448 = add v441, v447
-    v449 = cast v53 as Field
-    v451 = mul v449, Field 309485009821345068724781056
-    v452 = add v445, v451
-    v453 = cast v244 as Field
-    v454 = mul v453, Field 309485009821345068724781056
-    v455 = add v448, v454
-    v456 = cast v41 as Field
-    v458 = mul v456, Field 79228162514264337593543950336
-    v459 = add v452, v458
-    v460 = cast v232 as Field
-    v461 = mul v460, Field 79228162514264337593543950336
-    v462 = add v455, v461
-    v463 = cast v29 as Field
-    v465 = mul v463, Field 20282409603651670423947251286016
-    v466 = add v459, v465
-    v467 = cast v220 as Field
-    v468 = mul v467, Field 20282409603651670423947251286016
-    v469 = add v462, v468
-    v470 = cast v16 as Field
-    v472 = mul v470, Field 5192296858534827628530496329220096
-    v473 = add v466, v472
-    v474 = cast v208 as Field
-    v475 = mul v474, Field 5192296858534827628530496329220096
-    v476 = add v469, v475
-    v477 = cast v9 as Field
-    v479 = mul v477, Field 1329227995784915872903807060280344576
-    v480 = add v473, v479
-    v481 = cast v196 as Field
-    v482 = mul v481, Field 1329227995784915872903807060280344576
-    v483 = add v476, v482
-    v485 = mul v480, Field 340282366920938463463374607431768211456
-    v486 = add v483, v485
-    v488 = eq v4, Field 0
-    v489 = not v488
-    enable_side_effects v489
-    v491 = call f1(v4, Field 0) -> u1
-    v492 = mul v489, v491
-    enable_side_effects v492
-    v493 = cast v492 as Field
-    v495 = mul Field 53438638232309528389504892708671455232, v493
-    range_check v495 to 128 bits
-    v497 = mul Field 64323764613183177041862057485226039389, v493
-    range_check v497 to 128 bits
-    v499, v500 = call f3(v4) -> (Field, Field)
-    v501 = mul v499, v493
-    range_check v501 to 128 bits
-    v502 = mul v500, v493
-    range_check v502 to 128 bits
-    v503 = mul Field 340282366920938463463374607431768211456, v500
-    v504 = add v499, v503
-    v505 = mul v4, v493
-    v506 = mul v504, v493
-    constrain v505 == v506
-    v509 = call f2(Field 53438638232309528389504892708671455233, v499) -> u1
-    v510 = sub Field 53438638232309528389504892708671455233, v499
-    v512 = sub v510, Field 1
-    v513 = cast v509 as Field
-    v514 = mul v513, Field 340282366920938463463374607431768211456
-    v515 = add v512, v514
-    v516 = sub Field 64323764613183177041862057485226039389, v500
-    v517 = sub v516, v513
-    v518 = mul v515, v493
-    range_check v518 to 128 bits
-    v519 = mul v517, v493
-    range_check v519 to 128 bits
-    v521 = call f2(Field 0, v499) -> u1
-    v522 = sub Field 0, v499
-    v523 = sub v522, Field 1
-    v524 = cast v521 as Field
-    v525 = mul v524, Field 340282366920938463463374607431768211456
-    v526 = add v523, v525
-    v527 = sub Field 0, v500
-    v528 = sub v527, v524
-    v529 = mul v526, v493
-    range_check v529 to 128 bits
-    v530 = mul v528, v493
-    range_check v530 to 128 bits
-    v531 = not v491
-    v532 = mul v489, v531
-    enable_side_effects v532
-    v534, v535 = call f3(v4) -> (Field, Field)
-    v536 = cast v532 as Field
-    v537 = mul v534, v536
-    range_check v537 to 128 bits
-    v538 = mul v535, v536
-    range_check v538 to 128 bits
-    v539 = mul Field 340282366920938463463374607431768211456, v535
-    v540 = add v534, v539
-    v541 = mul v4, v536
-    v542 = mul v540, v536
-    constrain v541 == v542
-    v544 = call f2(Field 53438638232309528389504892708671455233, v534) -> u1
-    v545 = sub Field 53438638232309528389504892708671455233, v534
-    v546 = sub v545, Field 1
-    v547 = cast v544 as Field
-    v548 = mul v547, Field 340282366920938463463374607431768211456
-    v549 = add v546, v548
-    v550 = sub Field 64323764613183177041862057485226039389, v535
-    v551 = sub v550, v547
-    v552 = mul v549, v536
-    range_check v552 to 128 bits
-    v553 = mul v551, v536
-    range_check v553 to 128 bits
-    v554 = mul Field 53438638232309528389504892708671455232, v536
-    range_check v554 to 128 bits
-    v555 = mul Field 64323764613183177041862057485226039389, v536
-    range_check v555 to 128 bits
-    v557 = call f2(v534, Field 0) -> u1
-    v558 = sub v534, Field 1
-    v559 = cast v557 as Field
-    v560 = mul v559, Field 340282366920938463463374607431768211456
-    v561 = add v558, v560
-    v562 = sub v535, v559
-    v563 = mul v561, v536
-    range_check v563 to 128 bits
-    v564 = mul v562, v536
-    range_check v564 to 128 bits
-    enable_side_effects u1 1
-    v565 = sub v536, v486
-    return v565
-}
-brillig(inline) fn field_less_than f1 {
-  b0(v4: Field, v5: Field):
-    v7 = call field_less_than(v4, v5) -> u1
-    return v7
-}
-brillig(inline) fn lte_hint f2 {
-  b0(v4: Field, v5: Field):
-    v7 = eq v4, v5
-    jmpif v7 then: b2, else: b1
-  b1():
-    v9 = call f1(v4, v5) -> u1
-    jmp b3(v9)
-  b2():
-    jmp b3(u1 1)
-  b3(v6: u1):
-    return v6
-}
-brillig(inline) fn decompose_hint f3 {
-  b0(v4: Field):
-    v5 = truncate v4 to 64 bits, max_bit_size: 254
-    v6 = sub v4, v5
-    v7 = div v6, Field 18446744073709551616
-    v8 = truncate v7 to 64 bits, max_bit_size: 254
-    v9 = sub v7, v8
-    v10 = div v9, Field 18446744073709551616
-    v11 = mul v8, Field 18446744073709551616
-    v12 = add v11, v5
-    return v12, v10
-}
-
-[regression_7128] Circuit witness successfully solved
-[regression_7128] Circuit output: Field(0)
-[regression_7128] Witness saved to /mnt/user-data/maxim/noir/test_programs/execution_success/regression_7128/target/regression_7128.gz

From adec5bf0015d82b1628b81909fcffa934b01eeeb Mon Sep 17 00:00:00 2001
From: Maxim Vezenov <mvezenov@gmail.com>
Date: Tue, 21 Jan 2025 21:57:30 +0000
Subject: [PATCH 3/4] nargo fmt

---
 .../regression_7128/src/main.nr               | 19 ++++++++++---------
 .../regression_7128/src/main.nr               | 17 +++++++++--------
 2 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/test_programs/execution_failure/regression_7128/src/main.nr b/test_programs/execution_failure/regression_7128/src/main.nr
index 291f6498a66..35aaec0df2a 100644
--- a/test_programs/execution_failure/regression_7128/src/main.nr
+++ b/test_programs/execution_failure/regression_7128/src/main.nr
@@ -1,26 +1,27 @@
 fn main(in0: Field) -> pub Field {
-    let mut out0 : Field = 0;
-    let mut tmp1 : Field = 0;
+    let mut out0: Field = 0;
+    let mut tmp1: Field = 0;
 
     if ((out0 == out0) & true) // <== changing out0 to in0 or removing
-    {                          //     the comparison changes the result
-        let in0_as_bytes : [u8; 32] = in0.to_be_bytes();
-        let mut result : [u8; 32] = 0.to_be_bytes();
+    {
+        //     the comparison changes the result
+        let in0_as_bytes: [u8; 32] = in0.to_be_bytes();
+        let mut result: [u8; 32] = 0.to_be_bytes();
         for i in 0..32 {
             result[i] = (in0_as_bytes[i] ^ result[i]);
         }
         tmp1 = std::field::bytes32_to_field(result);
     }
 
-    let mut tmp2 : Field = 0; // <== moving this to the top of main,
-    if (0.lt(in0))            //     changes the result
+    let mut tmp2: Field = 0; // <== moving this to the top of main,
+    if (0.lt(in0)) //     changes the result
     {
         tmp2 = 1;
     }
 
     out0 = (tmp2 - tmp1);
 
-    assert(out0 != 0, "soundness violation"); 
+    assert(out0 != 0, "soundness violation");
 
     out0
-}
\ No newline at end of file
+}
diff --git a/test_programs/execution_success/regression_7128/src/main.nr b/test_programs/execution_success/regression_7128/src/main.nr
index 4c2a9e62a7f..ed004dd2642 100644
--- a/test_programs/execution_success/regression_7128/src/main.nr
+++ b/test_programs/execution_success/regression_7128/src/main.nr
@@ -1,19 +1,20 @@
 fn main(in0: Field) -> pub Field {
-    let mut out0 : Field = 0;
-    let mut tmp1 : Field = 0;
+    let mut out0: Field = 0;
+    let mut tmp1: Field = 0;
 
     if ((out0 == out0) & true) // <== changing out0 to in0 or removing
-    {                          //     the comparison changes the result
-        let in0_as_bytes : [u8; 32] = in0.to_be_bytes();
-        let mut result : [u8; 32] = 0.to_be_bytes();
+    {
+        //     the comparison changes the result
+        let in0_as_bytes: [u8; 32] = in0.to_be_bytes();
+        let mut result: [u8; 32] = 0.to_be_bytes();
         for i in 0..32 {
             result[i] = (in0_as_bytes[i] ^ result[i]);
         }
         tmp1 = std::field::bytes32_to_field(result);
     }
 
-    let mut tmp2 : Field = 0; // <== moving this to the top of main,
-    if (0.lt(in0))            //     changes the result
+    let mut tmp2: Field = 0; // <== moving this to the top of main,
+    if (0.lt(in0)) //     changes the result
     {
         tmp2 = 1;
     }
@@ -23,4 +24,4 @@ fn main(in0: Field) -> pub Field {
     assert(out0 == 0, "completeness violation");
 
     out0
-}
\ No newline at end of file
+}

From 47b2a594be945683a5289593bac28849d27f8493 Mon Sep 17 00:00:00 2001
From: Tom French <tom@tomfren.ch>
Date: Wed, 22 Jan 2025 10:34:32 +0000
Subject: [PATCH 4/4] chore: simplify regression tests

---
 .../execution_failure/regression_7128/src/main.nr        | 9 ++++-----
 .../execution_success/regression_7128/src/main.nr        | 9 ++++-----
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/test_programs/execution_failure/regression_7128/src/main.nr b/test_programs/execution_failure/regression_7128/src/main.nr
index 35aaec0df2a..46759fe90a2 100644
--- a/test_programs/execution_failure/regression_7128/src/main.nr
+++ b/test_programs/execution_failure/regression_7128/src/main.nr
@@ -1,16 +1,15 @@
 fn main(in0: Field) -> pub Field {
     let mut out0: Field = 0;
-    let mut tmp1: Field = 0;
+    let tmp1: Field = in0;
 
-    if ((out0 == out0) & true) // <== changing out0 to in0 or removing
+    if (out0 == out0) // <== changing out0 to in0 or removing
     {
         //     the comparison changes the result
         let in0_as_bytes: [u8; 32] = in0.to_be_bytes();
-        let mut result: [u8; 32] = 0.to_be_bytes();
+        let mut result: [u8; 32] = [0; 32];
         for i in 0..32 {
-            result[i] = (in0_as_bytes[i] ^ result[i]);
+            result[i] = in0_as_bytes[i];
         }
-        tmp1 = std::field::bytes32_to_field(result);
     }
 
     let mut tmp2: Field = 0; // <== moving this to the top of main,
diff --git a/test_programs/execution_success/regression_7128/src/main.nr b/test_programs/execution_success/regression_7128/src/main.nr
index ed004dd2642..454c2220b88 100644
--- a/test_programs/execution_success/regression_7128/src/main.nr
+++ b/test_programs/execution_success/regression_7128/src/main.nr
@@ -1,16 +1,15 @@
 fn main(in0: Field) -> pub Field {
     let mut out0: Field = 0;
-    let mut tmp1: Field = 0;
+    let tmp1: Field = in0;
 
-    if ((out0 == out0) & true) // <== changing out0 to in0 or removing
+    if (out0 == out0) // <== changing out0 to in0 or removing
     {
         //     the comparison changes the result
         let in0_as_bytes: [u8; 32] = in0.to_be_bytes();
-        let mut result: [u8; 32] = 0.to_be_bytes();
+        let mut result: [u8; 32] = [0; 32];
         for i in 0..32 {
-            result[i] = (in0_as_bytes[i] ^ result[i]);
+            result[i] = in0_as_bytes[i];
         }
-        tmp1 = std::field::bytes32_to_field(result);
     }
 
     let mut tmp2: Field = 0; // <== moving this to the top of main,