From e1028a30f108041c81780c28600d60fb29036514 Mon Sep 17 00:00:00 2001 From: jgbhatia Date: Fri, 17 Jun 2022 12:13:48 +0530 Subject: [PATCH 1/6] Update spyglass.py The run_main runs the spyglass tool. There are two targets in the make file. args = ["-i"] option is required to ignore the error code from the first design read target and run the lint target. --- edalize/spyglass.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/edalize/spyglass.py b/edalize/spyglass.py index 2166ca7f2..7afd6854a 100644 --- a/edalize/spyglass.py +++ b/edalize/spyglass.py @@ -145,3 +145,15 @@ def _vhdl_source(f): _s = "{} has unknown file type '{}'" logger.warning(_s.format(f.name, f.file_type)) return "" + + def run_main(self): + args = ["-i"] + + # Set plusargs + if self.plusarg: + plusargs = [] + for key, value in self.plusarg.items(): + plusargs += ["+{}={}".format(key, self._param_value_str(value))] + args.append("EXTRA_OPTIONS=" + " ".join(plusargs)) + + self._run_tool("make", args) From b933b5ac9de5d6d9941d111f53ef49f978bbc8aa Mon Sep 17 00:00:00 2001 From: Jaideep Bhatia Date: Mon, 17 Apr 2023 14:50:18 +0530 Subject: [PATCH 2/6] Create dc_shell.py --- edalize/dc_shell.py | 111 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 edalize/dc_shell.py diff --git a/edalize/dc_shell.py b/edalize/dc_shell.py new file mode 100644 index 000000000..86f40a201 --- /dev/null +++ b/edalize/dc_shell.py @@ -0,0 +1,111 @@ +# Copyright edalize contributors +# Licensed under the 2-Clause BSD License, see LICENSE for details. +# SPDX-License-Identifier: BSD-2-Clause + +import logging +import re +from collections import OrderedDict + +from edalize.edatool import Edatool + +logger = logging.getLogger(__name__) + + +class Dc_shell(Edatool): + + _description = """ Synopsys (formerly Atrenta) DC_shell Backend + +This module generates the file list for dc_shell. +""" + + tool_options = { + "lists": { + "dc_options": "String", + }, + } + + argtypes = ["vlogdefine", "vlogparam"] + + tool_options_defaults = { + "dc_options": [], + } + + def _set_tool_options_defaults(self): + for key, default_value in self.tool_options_defaults.items(): + if not key in self.tool_options: + logger.info( + "Set Spyglass tool option %s to default value %s" + % (key, str(default_value)) + ) + self.tool_options[key] = default_value + + def configure_main(self): + """ + Configuration is the first phase of the build. + + This writes the project TCL files and Makefile. It first collects all + sources, IPs and constraints and then writes them to the TCL file along + with the build steps. + """ + self._set_tool_options_defaults() + + (src_files, incdirs) = self._get_fileset_files(force_slash=True) + + self.jinja_env.filters["src_file_filter"] = self.src_file_filter + + has_systemVerilog = False + for src_file in src_files: + if src_file.file_type.startswith("systemVerilogSource"): + has_systemVerilog = True + break + + # Spyglass expects all parameters in the form module.parameter + # Always prepend the toplevel module name to be consistent with all other + # backends, which do not require this syntax. + vlogparam_spyglass = OrderedDict( + (self.toplevel + "." + p, v) for (p, v) in self.vlogparam.items() + ) + + template_vars = { + "name": self.name, + "src_files": src_files, + "incdirs": incdirs, + "tool_options": self.tool_options, + "toplevel": self.toplevel, + "vlogparam": vlogparam_spyglass, + "vlogdefine": self.vlogdefine, + "has_systemVerilog": has_systemVerilog, + "sanitized_goals": [], + } + + self.render_template( + "dc_shell.tcl.j2", self.name + ".tcl", template_vars + ) + + def src_file_filter(self, f): + + file_types = { + "verilogSource": "analyze -format sverilog", + "systemVerilogSource": "analyze -format sverilog", + } + _file_type = f.file_type.split("-")[0] + if _file_type in file_types: + return file_types[_file_type] + " " + f.name + elif _file_type == "user": + return "" + else: + _s = "{} has unknown file type '{}'" + logger.warning(_s.format(f.name, f.file_type)) + return "" + + def run_main(self): + args = ["-i"] + + # Set plusargs + if self.plusarg: + plusargs = [] + for key, value in self.plusarg.items(): + plusargs += ["+{}={}".format(key, self._param_value_str(value))] + args.append("EXTRA_OPTIONS=" + " ".join(plusargs)) + + self._run_tool("make", args) From 511424e2efd0ed6e2becdb01d213f3889cb66693 Mon Sep 17 00:00:00 2001 From: Jaideep Bhatia Date: Mon, 17 Apr 2023 14:53:20 +0530 Subject: [PATCH 3/6] Create Makefile.j2 --- edalize/templates/dc_shell/Makefile.j2 | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 edalize/templates/dc_shell/Makefile.j2 diff --git a/edalize/templates/dc_shell/Makefile.j2 b/edalize/templates/dc_shell/Makefile.j2 new file mode 100644 index 000000000..ca7b9ff43 --- /dev/null +++ b/edalize/templates/dc_shell/Makefile.j2 @@ -0,0 +1,10 @@ +all: {{ name }} + +{{ name }}: {{ name }}.scr + vcs -full64 -top {{ toplevel }} -f {{ name }}.scr -o $@ {% for option in vcs_options %} {{ option }}{% endfor %} + +run: {{ name }} + ./{{ name }} -l vcs.log {% for plusarg in plusargs %} {{ plusarg }} {% endfor %}{% for option in run_options %} {{ option }}{% endfor %} + +clean: + $(RM) {{ name }} From 63d3bceee6128f60f0273dcec78e3887e1bc68b3 Mon Sep 17 00:00:00 2001 From: Jaideep Bhatia Date: Mon, 17 Apr 2023 14:54:13 +0530 Subject: [PATCH 4/6] Create dc_shell.tcl.j2 --- edalize/templates/dc_shell/dc_shell.tcl.j2 | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 edalize/templates/dc_shell/dc_shell.tcl.j2 diff --git a/edalize/templates/dc_shell/dc_shell.tcl.j2 b/edalize/templates/dc_shell/dc_shell.tcl.j2 new file mode 100644 index 000000000..6a42e1f91 --- /dev/null +++ b/edalize/templates/dc_shell/dc_shell.tcl.j2 @@ -0,0 +1,33 @@ +################################################################################# +## RTL Read +## General read script for Design Compiler Reference Methodology +################################################################################# + +define_design_lib WORK -path ./WORK + +# The following variable helps verification when there are differences between DC and FM while inferring logical hierarchies +set_app_var hdlin_enable_hier_map true + +# By default, the tool uses simple names for elements inferred from +# unions in SystemVerilog. Setting this variable to true enables the tool +# to use the name of the first union member as a reference for the port, +# net, and cell names associated with the union data type. +set_app_var hdlin_sv_union_member_naming true + +{% if incdirs -%} +set_app_var search_path "$search_path {{ incdirs|join(' ') }}" +{%- endif %} + +{% for src_file in src_files if src_file|src_file_filter%} +{{ src_file|src_file_filter }} +{% endfor %} + +{% if toplevel -%} +elaborate {{ toplevel }} +{%- endif %} + +set_verification_top + +####################### +## end +####################### From a268befd863aedc2298356ecdf982a9bd567d149 Mon Sep 17 00:00:00 2001 From: Jaideep Bhatia Date: Wed, 23 Aug 2023 11:08:37 +0530 Subject: [PATCH 5/6] Update dc_shell.py Change the name of the output file list. --- edalize/dc_shell.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/edalize/dc_shell.py b/edalize/dc_shell.py index 86f40a201..366644dc9 100644 --- a/edalize/dc_shell.py +++ b/edalize/dc_shell.py @@ -79,7 +79,7 @@ def configure_main(self): } self.render_template( - "dc_shell.tcl.j2", self.name + ".tcl", template_vars + "dc_shell.tcl.j2", "dc.read_design.tcl", template_vars ) def src_file_filter(self, f): From 3cc9616874c09570c49c27bd4e944548fc2a5995 Mon Sep 17 00:00:00 2001 From: Jaideep Bhatia Date: Wed, 23 Aug 2023 11:10:31 +0530 Subject: [PATCH 6/6] Update dc_shell.tcl.j2 Only search path and the file list. --- edalize/templates/dc_shell/dc_shell.tcl.j2 | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/edalize/templates/dc_shell/dc_shell.tcl.j2 b/edalize/templates/dc_shell/dc_shell.tcl.j2 index 6a42e1f91..5d88c7b37 100644 --- a/edalize/templates/dc_shell/dc_shell.tcl.j2 +++ b/edalize/templates/dc_shell/dc_shell.tcl.j2 @@ -3,17 +3,6 @@ ## General read script for Design Compiler Reference Methodology ################################################################################# -define_design_lib WORK -path ./WORK - -# The following variable helps verification when there are differences between DC and FM while inferring logical hierarchies -set_app_var hdlin_enable_hier_map true - -# By default, the tool uses simple names for elements inferred from -# unions in SystemVerilog. Setting this variable to true enables the tool -# to use the name of the first union member as a reference for the port, -# net, and cell names associated with the union data type. -set_app_var hdlin_sv_union_member_naming true - {% if incdirs -%} set_app_var search_path "$search_path {{ incdirs|join(' ') }}" {%- endif %} @@ -22,12 +11,6 @@ set_app_var search_path "$search_path {{ incdirs|join(' ') }}" {{ src_file|src_file_filter }} {% endfor %} -{% if toplevel -%} -elaborate {{ toplevel }} -{%- endif %} - -set_verification_top - ####################### ## end #######################