diff --git a/core.json b/core.json index ba7fb9c..a8e1917 100644 --- a/core.json +++ b/core.json @@ -7,8 +7,8 @@ "description": "APF core template. Displays gray test screen.", "author": "Developer", "url": "https://github.com/open-fpga/core-template", - "version": "1.2.0", - "date_release": "2022-11-05" + "version": "1.3.0", + "date_release": "2023-03-08" }, "framework": { "target_product": "Analogue Pocket", diff --git a/output/bitstream.rbf_r b/output/bitstream.rbf_r index f46d60a..bbd33f0 100644 Binary files a/output/bitstream.rbf_r and b/output/bitstream.rbf_r differ diff --git a/src/fpga/apf/build_id.mif b/src/fpga/apf/build_id.mif index 2fca0aa..a0841bc 100644 --- a/src/fpga/apf/build_id.mif +++ b/src/fpga/apf/build_id.mif @@ -9,8 +9,8 @@ DATA_RADIX = HEX; CONTENT BEGIN - 0E0 : 20221025; - 0E1 : 00195120; - 0E2 : 3c157f76; + 0E0 : 20230308; + 0E1 : 00210243; + 0E2 : 35e2f538; END; diff --git a/src/fpga/core/core_bridge_cmd.v b/src/fpga/core/core_bridge_cmd.v index 8729a0a..7858a62 100644 --- a/src/fpga/core/core_bridge_cmd.v +++ b/src/fpga/core/core_bridge_cmd.v @@ -76,6 +76,8 @@ input wire savestate_load_err, input wire target_dataslot_read, // rising edge triggered input wire target_dataslot_write, +input wire target_dataslot_getfile, +input wire target_dataslot_openfile, output reg target_dataslot_ack, // asserted upon command start until completion output reg target_dataslot_done, // asserted upon command finish until next command is issued @@ -86,6 +88,10 @@ input wire [31:0] target_dataslot_slotoffset, input wire [31:0] target_dataslot_bridgeaddr, input wire [31:0] target_dataslot_length, +input wire [31:0] target_buffer_param_struct, // bus address of the memory region APF will fetch additional parameter struct from +input wire [31:0] target_buffer_resp_struct, // bus address of the memory region APF will write its response struct to + // this should be mapped by the developer, the buffer is not implemented in this file + input wire [9:0] datatable_addr, input wire datatable_wren, input wire [31:0] datatable_data, @@ -153,8 +159,8 @@ localparam [3:0] ST_DONE_ERR = 'd15; // target reg [31:0] target_0; - reg [31:0] target_4 = 'h20; - reg [31:0] target_8 = 'h40; + reg [31:0] target_4 = 'h20; // target cmd parameter data at 0x20 + reg [31:0] target_8 = 'h40; // target cmd response data at 0x40 reg [31:0] target_20; // parameter data reg [31:0] target_24; @@ -176,6 +182,8 @@ localparam [3:0] TARG_ST_WAITRESULT_DSO = 'd15; reg status_setup_done_1, status_setup_done_queue; reg target_dataslot_read_1, target_dataslot_read_queue; reg target_dataslot_write_1, target_dataslot_write_queue; + reg target_dataslot_getfile_1, target_dataslot_getfile_queue; + reg target_dataslot_openfile_1, target_dataslot_openfile_queue; initial begin @@ -192,6 +200,8 @@ initial begin status_setup_done_queue <= 0; target_dataslot_read_queue <= 0; target_dataslot_write_queue <= 0; + target_dataslot_getfile_queue <= 0; + target_dataslot_openfile_queue <= 0; target_dataslot_ack <= 0; target_dataslot_done <= 0; target_dataslot_err <= 0; @@ -204,6 +214,8 @@ always @(posedge clk) begin status_setup_done_1 <= status_setup_done; target_dataslot_read_1 <= target_dataslot_read; target_dataslot_write_1 <= target_dataslot_write; + target_dataslot_getfile_1 <= target_dataslot_getfile; + target_dataslot_openfile_1 <= target_dataslot_openfile; if(status_setup_done & ~status_setup_done_1) begin status_setup_done_queue <= 1; @@ -214,6 +226,12 @@ always @(posedge clk) begin if(target_dataslot_write & ~target_dataslot_write_1) begin target_dataslot_write_queue <= 1; end + if(target_dataslot_getfile & ~target_dataslot_getfile_1) begin + target_dataslot_getfile_queue <= 1; + end + if(target_dataslot_openfile & ~target_dataslot_openfile_1) begin + target_dataslot_openfile_queue <= 1; + end b_datatable_wren <= 0; @@ -484,6 +502,24 @@ always @(posedge clk) begin target_2C <= target_dataslot_length; tstate <= TARG_ST_DATASLOTOP; + + end else if(target_dataslot_getfile_queue) begin + target_dataslot_getfile_queue <= 0; + target_0[15:0] <= 16'h0190; + + target_20 <= target_dataslot_id; + target_24 <= target_buffer_resp_struct; // pointer to the bram that will hold the response struct + // which will contain the requested filename before command completion + tstate <= TARG_ST_DATASLOTOP; + + end else if(target_dataslot_openfile_queue) begin + target_dataslot_openfile_queue <= 0; + target_0[15:0] <= 16'h0192; + + target_20 <= target_dataslot_id; + target_24 <= target_buffer_param_struct; // pointer to the bram that will hold the parameter struct + // which must contain the desired filename and flag/size before command execution + tstate <= TARG_ST_DATASLOTOP; end end TARG_ST_READYTORUN: begin @@ -494,6 +530,7 @@ always @(posedge clk) begin target_0[31:16] <= 16'h636D; target_dataslot_done <= 0; + target_dataslot_err <= 0; tstate <= TARG_ST_WAITRESULT_DSO; end TARG_ST_WAITRESULT_DSO: begin diff --git a/src/fpga/core/core_top.v b/src/fpga/core/core_top.v index 03f3cc2..0018956 100644 --- a/src/fpga/core/core_top.v +++ b/src/fpga/core/core_top.v @@ -336,8 +336,8 @@ end // bridge host commands // synchronous to clk_74a - wire status_boot_done = pll_core_locked; - wire status_setup_done = pll_core_locked; // rising edge triggers a target command + wire status_boot_done = pll_core_locked_s; + wire status_setup_done = pll_core_locked_s; // rising edge triggers a target command wire status_running = reset_n; // we are running as soon as reset_n goes high wire dataslot_requestread; @@ -386,7 +386,9 @@ end reg target_dataslot_read; reg target_dataslot_write; - + reg target_dataslot_getfile; // require additional param/resp structs to be mapped + reg target_dataslot_openfile; // require additional param/resp structs to be mapped + wire target_dataslot_ack; wire target_dataslot_done; wire [2:0] target_dataslot_err; @@ -396,6 +398,9 @@ end reg [31:0] target_dataslot_bridgeaddr; reg [31:0] target_dataslot_length; + wire [31:0] target_buffer_param_struct; // to be mapped/implemented when using some Target commands + wire [31:0] target_buffer_resp_struct; // to be mapped/implemented when using some Target commands + // bridge data slot access // synchronous to clk_74a @@ -463,7 +468,9 @@ core_bridge_cmd icb ( .target_dataslot_read ( target_dataslot_read ), .target_dataslot_write ( target_dataslot_write ), - + .target_dataslot_getfile ( target_dataslot_getfile ), + .target_dataslot_openfile ( target_dataslot_openfile ), + .target_dataslot_ack ( target_dataslot_ack ), .target_dataslot_done ( target_dataslot_done ), .target_dataslot_err ( target_dataslot_err ), @@ -473,6 +480,9 @@ core_bridge_cmd icb ( .target_dataslot_bridgeaddr ( target_dataslot_bridgeaddr ), .target_dataslot_length ( target_dataslot_length ), + .target_buffer_param_struct ( target_buffer_param_struct ), + .target_buffer_resp_struct ( target_buffer_resp_struct ), + .datatable_addr ( datatable_addr ), .datatable_wren ( datatable_wren ), .datatable_data ( datatable_data ), @@ -647,7 +657,9 @@ end wire clk_core_12288_90deg; wire pll_core_locked; - + wire pll_core_locked_s; +synch_3 s01(pll_core_locked, pll_core_locked_s, clk_74a); + mf_pllbase mp1 ( .refclk ( clk_74a ), .rst ( 0 ), diff --git a/src/fpga/output_files/ap_core.rbf b/src/fpga/output_files/ap_core.rbf index afbb77a..ece45b2 100644 Binary files a/src/fpga/output_files/ap_core.rbf and b/src/fpga/output_files/ap_core.rbf differ diff --git a/src/fpga/output_files/ap_core.sof b/src/fpga/output_files/ap_core.sof index e29c175..0483e73 100644 Binary files a/src/fpga/output_files/ap_core.sof and b/src/fpga/output_files/ap_core.sof differ