Changelog

All notable changes to this project will be documented in this file.

The format is based on Keep a Changelog and this project adheres to Semantic Versioning.

Unreleased

0.2.1 - 2023-03-27

Fixed

LSR.THRE flag now shows empty instead of not full status of transmit holding register.

0.2.0 - 2022-11-09

Added

SystemVerilog implementation as default codebase
reg_uart_wrap: register-interface wrapper for apb_uart

Fixed

Baudrate generation

0.1.0 - 2018-09-12

Changed

Open source release.

Added

Initial commit.