From bc4c1a4c931067b3d7bfd36e745da81930759337 Mon Sep 17 00:00:00 2001 From: Hayate Okuhara Date: Tue, 30 Jun 2020 17:42:10 +0200 Subject: [PATCH 1/4] test bench modification & hyperbus module integration --- generate-scripts | 6 + rtl/pulpissimo/pad_frame.sv | 42 ++++ rtl/pulpissimo/pulpissimo.sv | 62 +++++ rtl/pulpissimo/soc_domain.sv | 15 +- rtl/tb/tb_pulp.sv | 194 ++++++++++----- rtl/vip/hyper_model/README.txt | 1 + rtl/vip/src_files.yml | 12 + sim/boot/boot_code.cde | 424 ++++++++++++++++----------------- 8 files changed, 489 insertions(+), 267 deletions(-) create mode 100644 rtl/vip/hyper_model/README.txt diff --git a/generate-scripts b/generate-scripts index 3c9da1a3..e958affc 100755 --- a/generate-scripts +++ b/generate-scripts @@ -24,6 +24,9 @@ parser.add_argument('--flash-vip', action='store_true', parser.add_argument('--i2s-vip', action='store_true', help="""Use the i2s model (24FC1025). Needs to be installed.""") +parser.add_argument('--hyper-vip', action='store_true', + help="""Use the hyperbus models (S27KS0641 and S26KS512S). + Needs to be installed.""") parser.add_argument('--verbose', action='store_true', help='Show more information about commands') @@ -62,6 +65,9 @@ if not args.i2c_vip: if not args.flash_vip: del (ipdb.rtl_dic['vip'].sub_ips['S25FS256_model']) +if not args.hyper_vip: + del (ipdb.rtl_dic['vip'].sub_ips['HYPER_model']) + if not args.i2s_vip: del (ipdb.rtl_dic['vip'].sub_ips['i2s_model']) diff --git a/rtl/pulpissimo/pad_frame.sv b/rtl/pulpissimo/pad_frame.sv index c606ca89..8871fbb7 100644 --- a/rtl/pulpissimo/pad_frame.sv +++ b/rtl/pulpissimo/pad_frame.sv @@ -59,6 +59,9 @@ module pad_frame input logic oe_i2c0_scl_i , input logic oe_uart_rx_i , input logic oe_uart_tx_i , + input logic oe_hyper_rwds_i , + input logic oe_hyper_dq_i , + // INPUTS SIGNALS TO THE PADS input logic out_sdio_clk_i , @@ -93,6 +96,13 @@ module pad_frame input logic out_i2c0_scl_i , input logic out_uart_rx_i , input logic out_uart_tx_i , + input logic [1:0] out_hyper_csn_i , + input logic out_hyper_ck_i , + input logic out_hyper_ckn_i , + input logic out_hyper_rwds_i , + input logic [7:0] out_hyper_dq_i , + input logic out_hyper_resetn_i , + // OUTPUT SIGNALS FROM THE PADS output logic in_sdio_clk_o , @@ -127,6 +137,9 @@ module pad_frame output logic in_i2c0_scl_o , output logic in_uart_rx_o , output logic in_uart_tx_o , + output logic in_hyper_rwds_o, + output logic [7:0] in_hyper_dq_o, + output logic bootsel_o , @@ -171,6 +184,20 @@ module pad_frame inout wire pad_jtag_tdo , inout wire pad_jtag_tms , inout wire pad_jtag_trst , + inout wire pad_hyper_cs_no0 , + inout wire pad_hyper_cs_no1 , + inout wire pad_hyper_cko , + inout wire pad_hyper_ckno , + inout wire pad_hyper_rwds , + inout wire pad_hyper_dqio0 , + inout wire pad_hyper_dqio1 , + inout wire pad_hyper_dqio2 , + inout wire pad_hyper_dqio3 , + inout wire pad_hyper_dqio4 , + inout wire pad_hyper_dqio5 , + inout wire pad_hyper_dqio6 , + inout wire pad_hyper_dqio7 , + inout wire pad_hyper_resetn , inout wire pad_xtal_in @@ -216,6 +243,21 @@ module pad_frame pad_functional_pu padinst_bootsel (.OEN(1'b1 ), .I( ), .O(bootsel_o ), .PAD(pad_bootsel ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_csno0 (.OEN( 1'b0 ), .I( out_hyper_csn_i[0] ), .O( ), .PAD( pad_hyper_cs_no0 ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_csno1 (.OEN( 1'b0 ), .I( out_hyper_csn_i[1] ), .O( ), .PAD( pad_hyper_cs_no1 ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_ck (.OEN( 1'b0 ), .I( out_hyper_ck_i ), .O( ), .PAD( pad_hyper_cko ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_ckno (.OEN( 1'b0 ), .I( out_hyper_ckn_i ), .O( ), .PAD( pad_hyper_ckno ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_dqio0 (.OEN( !oe_hyper_dq_i ), .I( out_hyper_dq_i[0] ), .O( in_hyper_dq_o[0] ), .PAD( pad_hyper_dqio0 ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_dqio1 (.OEN( !oe_hyper_dq_i ), .I( out_hyper_dq_i[1] ), .O( in_hyper_dq_o[1] ), .PAD( pad_hyper_dqio1 ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_dqio2 (.OEN( !oe_hyper_dq_i ), .I( out_hyper_dq_i[2] ), .O( in_hyper_dq_o[2] ), .PAD( pad_hyper_dqio2 ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_dqio3 (.OEN( !oe_hyper_dq_i ), .I( out_hyper_dq_i[3] ), .O( in_hyper_dq_o[3] ), .PAD( pad_hyper_dqio3 ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_dqio4 (.OEN( !oe_hyper_dq_i ), .I( out_hyper_dq_i[4] ), .O( in_hyper_dq_o[4] ), .PAD( pad_hyper_dqio4 ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_dqio5 (.OEN( !oe_hyper_dq_i ), .I( out_hyper_dq_i[5] ), .O( in_hyper_dq_o[5] ), .PAD( pad_hyper_dqio5 ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_dqio6 (.OEN( !oe_hyper_dq_i ), .I( out_hyper_dq_i[6] ), .O( in_hyper_dq_o[6] ), .PAD( pad_hyper_dqio6 ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_dqio7 (.OEN( !oe_hyper_dq_i ), .I( out_hyper_dq_i[7] ), .O( in_hyper_dq_o[7] ), .PAD( pad_hyper_dqio7 ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_rwds (.OEN( !oe_hyper_rwds_i ), .I( out_hyper_rwds_i ), .O( in_hyper_rwds_o ), .PAD( pad_hyper_rwds ), .PEN(1'b1 ) ); + pad_functional_pu padinst_hyper_resetn (.OEN( 1'b0 ), .I( out_hyper_resetn_i ), .O( ), .PAD( pad_hyper_resetn ), .PEN(1'b1 ) ); + `ifndef PULP_FPGA_EMUL pad_functional_pu padinst_ref_clk (.OEN(1'b1 ), .I( ), .O(ref_clk_o ), .PAD(pad_xtal_in ), .PEN(1'b1 ) ); diff --git a/rtl/pulpissimo/pulpissimo.sv b/rtl/pulpissimo/pulpissimo.sv index 6d85fdd6..f32ca4a9 100644 --- a/rtl/pulpissimo/pulpissimo.sv +++ b/rtl/pulpissimo/pulpissimo.sv @@ -54,6 +54,21 @@ module pulpissimo #( inout wire pad_i2s0_sdi, inout wire pad_i2s1_sdi, + inout wire pad_hyper_cs_no0 , + inout wire pad_hyper_cs_no1 , + inout wire pad_hyper_cko , + inout wire pad_hyper_ckno , + inout wire pad_hyper_rwds , + inout wire pad_hyper_dqio0 , + inout wire pad_hyper_dqio1 , + inout wire pad_hyper_dqio2 , + inout wire pad_hyper_dqio3 , + inout wire pad_hyper_dqio4 , + inout wire pad_hyper_dqio5 , + inout wire pad_hyper_dqio6 , + inout wire pad_hyper_dqio7 , + inout wire pad_hyper_resetn , + inout wire pad_reset_n, inout wire pad_bootsel, @@ -327,6 +342,18 @@ module pulpissimo #( logic [127:0] s_pad_mux_soc; logic [383:0] s_pad_cfg_soc; + logic [1:0] s_out_hyper_csn; + logic s_out_hyper_ck; + logic s_out_hyper_ckn; + logic s_out_hyper_rwds; + logic s_in_hyper_rwds; + logic s_oe_hyper_rwds; + logic [7:0] s_out_hyper_dq; + logic [7:0] s_in_hyper_dq; + logic s_oe_hyper_dq; + logic s_out_hyper_resetn; + + //*********************************************************** //********** SOC TO CLUSTER DOMAINS SIGNALS ***************** //*********************************************************** @@ -395,6 +422,8 @@ module pulpissimo #( .oe_i2c0_scl_i ( s_oe_i2c0_scl ), .oe_uart_rx_i ( s_oe_uart_rx ), .oe_uart_tx_i ( s_oe_uart_tx ), + .oe_hyper_rwds_i ( s_oe_hyper_rwds ), + .oe_hyper_dq_i ( s_oe_hyper_dq ), .out_spim_sdio0_i ( s_out_spim_sdio0 ), .out_spim_sdio1_i ( s_out_spim_sdio1 ), @@ -428,6 +457,12 @@ module pulpissimo #( .out_i2c0_scl_i ( s_out_i2c0_scl ), .out_uart_rx_i ( s_out_uart_rx ), .out_uart_tx_i ( s_out_uart_tx ), + .out_hyper_csn_i ( s_out_hyper_csn ), + .out_hyper_ck_i ( s_out_hyper_ck ), + .out_hyper_ckn_i ( s_out_hyper_ckn ), + .out_hyper_rwds_i ( s_out_hyper_rwds ), + .out_hyper_dq_i ( s_out_hyper_dq ), + .out_hyper_resetn_i ( s_out_hyper_resetn ), .in_spim_sdio0_o ( s_in_spim_sdio0 ), .in_spim_sdio1_o ( s_in_spim_sdio1 ), @@ -461,6 +496,8 @@ module pulpissimo #( .in_i2c0_scl_o ( s_in_i2c0_scl ), .in_uart_rx_o ( s_in_uart_rx ), .in_uart_tx_o ( s_in_uart_tx ), + .in_hyper_rwds_o ( s_in_hyper_rwds ), + .in_hyper_dq_o ( s_in_hyper_dq ), .bootsel_o ( s_bootsel ), //EXT CHIP to PAD @@ -496,6 +533,20 @@ module pulpissimo #( .pad_i2c0_scl ( pad_i2c0_scl ), .pad_uart_rx ( pad_uart_rx ), .pad_uart_tx ( pad_uart_tx ), + .pad_hyper_cs_no0 ( pad_hyper_cs_no0 ), + .pad_hyper_cs_no1 ( pad_hyper_cs_no1 ), + .pad_hyper_cko ( pad_hyper_cko ), + .pad_hyper_ckno ( pad_hyper_ckno ), + .pad_hyper_rwds ( pad_hyper_rwds ), + .pad_hyper_dqio0 ( pad_hyper_dqio0 ), + .pad_hyper_dqio1 ( pad_hyper_dqio1 ), + .pad_hyper_dqio2 ( pad_hyper_dqio2 ), + .pad_hyper_dqio3 ( pad_hyper_dqio3 ), + .pad_hyper_dqio4 ( pad_hyper_dqio4 ), + .pad_hyper_dqio5 ( pad_hyper_dqio5 ), + .pad_hyper_dqio6 ( pad_hyper_dqio6 ), + .pad_hyper_dqio7 ( pad_hyper_dqio7 ), + .pad_hyper_resetn ( pad_hyper_resetn ), .pad_bootsel ( pad_bootsel ), .pad_reset_n ( pad_reset_n ), @@ -817,6 +868,17 @@ module pulpissimo #( .sdio_data_i ( s_sdio_datai ), .sdio_data_oen_o ( s_sdio_data_oen ), + .hyper_cs_no ( s_out_hyper_csn ), + .hyper_ck_o ( s_out_hyper_ck ), + .hyper_ck_no ( s_out_hyper_ckn ), + .hyper_rwds_o ( s_out_hyper_rwds ), + .hyper_rwds_i ( s_in_hyper_rwds ), + .hyper_rwds_oe_o ( s_oe_hyper_rwds ), + .hyper_dq_i ( s_in_hyper_dq ), + .hyper_dq_o ( s_out_hyper_dq ), + .hyper_dq_oe_o ( s_oe_hyper_dq ), + .hyper_reset_no ( s_out_hyper_resetn ), + .cluster_busy_i ( s_cluster_busy ), .cluster_events_wt_o ( s_event_writetoken ), diff --git a/rtl/pulpissimo/soc_domain.sv b/rtl/pulpissimo/soc_domain.sv index aeb69ea2..a6e4016e 100644 --- a/rtl/pulpissimo/soc_domain.sv +++ b/rtl/pulpissimo/soc_domain.sv @@ -115,9 +115,20 @@ module soc_domain #( output logic sdio_cmd_oen_o, output logic [3:0] sdio_data_o, input logic [3:0] sdio_data_i, - output logic [3:0] sdio_data_oen_o + output logic [3:0] sdio_data_oen_o , + + output logic [1:0] hyper_cs_no, + output logic hyper_ck_o, + output logic hyper_ck_no, + output logic hyper_rwds_o, + input logic hyper_rwds_i, + output logic hyper_rwds_oe_o, + input logic [7:0] hyper_dq_i, + output logic [7:0] hyper_dq_o, + output logic hyper_dq_oe_o, + output logic hyper_reset_no, + - , // CLUSTER output logic cluster_clk_o, output logic cluster_rstn_o, diff --git a/rtl/tb/tb_pulp.sv b/rtl/tb/tb_pulp.sv index c70b949b..ab00f050 100644 --- a/rtl/tb/tb_pulp.sv +++ b/rtl/tb/tb_pulp.sv @@ -36,9 +36,10 @@ module tb_pulp; // if RISCY is instantiated (CORE_TYPE == 0), RISCY_FPU enables the FPU parameter RISCY_FPU = 1; - // the following parameters can activate instantiation of the verification IPs for SPI, I2C and I2s + // the following parameters can activate instantiation of the verification IPs for Hyperflash, Hyperram, SPI, I2C and I2s // see the instructions in rtl/vip/{i2c_eeprom,i2s,spi_flash} to download the verification IPs - parameter USE_S25FS256S_MODEL = 0; + parameter USE_HYPER_MODELS = 0; + parameter USE_S25FS256S_MODEL = 1; parameter USE_24FC1025_MODEL = 0; parameter USE_I2S_MODEL = 0; @@ -46,7 +47,11 @@ module tb_pulp; parameter REF_CLK_PERIOD = 30517ns; // how L2 is loaded. valid values are "JTAG" or "STANDALONE", the latter works only when USE_S25FS256S_MODEL is 1 + // STIM_FROM is available when LOAD_L2 is "JTAG". Valid values are "JTAG", "SPI_FLASH", and "HYPER_FLASH". + // In case any values are given, the debug module takes over the boot process. + //parameter LOAD_L2 = "STANDALONE"; parameter LOAD_L2 = "JTAG"; + parameter STIM_FROM = "SPI_FLASH"; // enable DPI-based JTAG parameter ENABLE_DPI = 0; @@ -58,13 +63,13 @@ module tb_pulp; parameter ENABLE_EXTERNAL_DRIVER = 0; // enable DPI-based openocd debug bridge - parameter ENABLE_OPENOCD = 0; + parameter ENABLE_OPENOCD = 0; // enable Debug Module Tests - parameter ENABLE_DM_TESTS = 0; + parameter ENABLE_DM_TESTS = 0; // use the pulp tap to access the bus - parameter USE_PULP_BUS_ACCESS = 1; + parameter USE_PULP_BUS_ACCESS = 1; // UART baud rate in bps parameter BAUDRATE = 625000; @@ -206,6 +211,13 @@ module tb_pulp; logic tmp_tdo; logic tmp_bridge_tdo; + // wire for HYPER BUS + wire wire_rwds; + wire [7:0 ] wire_dq_io; + wire [1:0] wire_cs_no; + wire wire_ck_o; + wire wire_ck_no; + wire wire_reset_no; wire w_master_i2s_sck; @@ -356,7 +368,6 @@ module tb_pulp; assign w_uart_tx = w_uart_rx; end - // TODO: this should be set depending on the desired boot mode (JTAG, FLASH) assign w_bootsel = s_bootsel; /* JTAG DPI-based verification IP */ @@ -376,6 +387,48 @@ module tb_pulp; end endgenerate + /* Hyperflash and Hyperram (not open-source, from Cypress) */ + generate + if(USE_HYPER_MODELS == 1) begin + s27ks0641 #( + .TimingModel ("S27KS0641DPBHI020") + ) hyperram_model ( + .DQ7 ( wire_dq_io[7] ), + .DQ6 ( wire_dq_io[6] ), + .DQ5 ( wire_dq_io[5] ), + .DQ4 ( wire_dq_io[4] ), + .DQ3 ( wire_dq_io[3] ), + .DQ2 ( wire_dq_io[2] ), + .DQ1 ( wire_dq_io[1] ), + .DQ0 ( wire_dq_io[0] ), + .RWDS ( wire_rwds ), + .CSNeg ( wire_cs_no[1] ), + .CK ( wire_ck_o ), + .CKNeg ( wire_ck_no ), + .RESETNeg ( wire_reset_no ) + ); + s26ks512s #( + .TimingModel ( "S26KS512SDPBHI000"), + .mem_file_name ( "slm_files/flash_stim_hyper.slm" ) + ) hyperflash_model ( + .DQ7 ( wire_dq_io[7] ), + .DQ6 ( wire_dq_io[6] ), + .DQ5 ( wire_dq_io[5] ), + .DQ4 ( wire_dq_io[4] ), + .DQ3 ( wire_dq_io[3] ), + .DQ2 ( wire_dq_io[2] ), + .DQ1 ( wire_dq_io[1] ), + .DQ0 ( wire_dq_io[0] ), + .RWDS ( wire_rwds ), + .CSNeg ( wire_cs_no[0] ), + .CK ( wire_ck_o ), + .CKNeg ( wire_ck_no ), + .RESETNeg ( wire_reset_no ) + ); + end + endgenerate + + /* SPI flash model (not open-source, from Spansion) */ generate if(USE_S25FS256S_MODEL == 1) begin @@ -577,6 +630,21 @@ module tb_pulp; .pad_i2s0_sdi ( w_i2s0_sdi ), .pad_i2s1_sdi ( w_i2s1_sdi ), + .pad_hyper_cs_no0 ( wire_cs_no[0] ), + .pad_hyper_cs_no1 ( wire_cs_no[1] ), + .pad_hyper_cko ( wire_ck_o ), + .pad_hyper_ckno ( wire_ck_no ), + .pad_hyper_rwds ( wire_rwds ), + .pad_hyper_dqio0 ( wire_dq_io[0] ), + .pad_hyper_dqio1 ( wire_dq_io[1] ), + .pad_hyper_dqio2 ( wire_dq_io[2] ), + .pad_hyper_dqio3 ( wire_dq_io[3] ), + .pad_hyper_dqio4 ( wire_dq_io[4] ), + .pad_hyper_dqio5 ( wire_dq_io[5] ), + .pad_hyper_dqio6 ( wire_dq_io[6] ), + .pad_hyper_dqio7 ( wire_dq_io[7] ), + .pad_hyper_resetn ( wire_reset_no ), + .pad_reset_n ( w_rst_n ), .pad_bootsel ( w_bootsel ), @@ -628,6 +696,7 @@ module tb_pulp; if (ENABLE_OPENOCD == 1) begin // Use openocd to interact with the simulation + s_bootsel = 1'b1; $display("[TB] %t - Releasing hard reset", $realtime); s_rst_n = 1'b1; @@ -640,10 +709,13 @@ module tb_pulp; end else begin // Use only the testbench to do the loading and running - // determine if we want to load the binary with jtag or from flash - if (LOAD_L2 == "STANDALONE") + // determine if we want to simulate the stand-alone mode + // If JTAG is selected, the boot process will be selected according to the value of jtag_conf_reg + if (LOAD_L2 == "STANDALONE") begin + $display("[TB] %t - Releasing hard reset", $realtime); + s_rst_n = 1'b1; s_bootsel = 1'b0; - else if (LOAD_L2 == "JTAG") begin + end else if (LOAD_L2 == "JTAG") begin s_bootsel = 1'b1; end @@ -683,19 +755,14 @@ module tb_pulp; $display("[TB] %t - Enabling clock out via jtag", $realtime); - // we are using a bootsel based booting method: - // bootsel = 1'b1 means booting from jtag => bootrom makes us wait in a wfi/busy loop - // bootsel = 1'b1 means booting from flash => start loading image from flash - // This logic is handled in the bootrom which will read the bootsel signal value. - // - // This also means we are currently not relying on the jtag confreg to configure the booting behavior but it is still possible to use it. - // When the confreg is not set then we will boot according to bootsel. - // TODO: regression: we can't propgate our FLL settings like this. Needs sw changes (?) - // - // jtag_conf_reg = {USE_FLL ? 1'b0 : 1'b1, 6'b0, LOAD_L2 == "JTAG" ? 2'b10 : 2'b00}; - // test_mode_if.set_confreg(jtag_conf_reg, jtag_conf_rego, - // s_tck, s_tms, s_trstn, s_tdi, s_tdo); - // $display("[TB] %t - jtag_conf_reg set to %x", $realtime, jtag_conf_reg); + // The boot code installed in the ROM checks the JTAG register value. + // If jtag_conf_reg is set to 0, the debug module will take over the boot process + jtag_conf_reg = (STIM_FROM == "JTAG") ? {1'b0, 4'b0, 3'b001, 1'b0}: + (STIM_FROM == "SPI_FLASH") ? {1'b0, 4'b0, 3'b111, 1'b0}: + (STIM_FROM == "HYPER_FLASH") ? {1'b0, 4'b0, 3'b101, 1'b0}: '0; + test_mode_if.set_confreg(jtag_conf_reg, jtag_conf_rego, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + + $display("[TB] %t - jtag_conf_reg set to %x", $realtime, jtag_conf_reg); $display("[TB] %t - Releasing hard reset", $realtime); s_rst_n = 1'b1; @@ -719,60 +786,81 @@ module tb_pulp; else $display("[JTAG] R/W test of L2 succeeded"); - // From here on starts the actual jtag booting // Setup debug module and hart, halt hart and set dpc (return point // for boot). // Halting the fc hart transfers control of the program execution to - // the debug module. This might take a bit until the debug request - // signal is propagated so meanwhile the core is executing stuff - // from the bootrom. For jtag booting (what we are doing right now), - // bootsel is low so the code that is being executed in said bootrom - // is only a busy wait or wfi until the debug unit grabs control. + // the debug module. + debug_mode_if.init_dmi_access(s_tck, s_tms, s_trstn, s_tdi); debug_mode_if.set_dmactive(1'b1, s_tck, s_tms, s_trstn, s_tdi, s_tdo); debug_mode_if.set_hartsel(FC_CORE_ID, s_tck, s_tms, s_trstn, s_tdi, s_tdo); - - $display("[TB] %t - Halting the Core", $realtime); - debug_mode_if.halt_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo); - - $display("[TB] %t - Writing the boot address into dpc", $realtime); - debug_mode_if.write_reg_abstract_cmd(riscv::CSR_DPC, begin_l2_instr, - s_tck, s_tms, s_trstn, s_tdi, s_tdo); + + if(jtag_conf_reg == 0) begin + $display("Jtag register is not set. The debug module takes over the boot process"); + $display("[TB] %t - Halting the Core", $realtime); + debug_mode_if.halt_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo); + + $display("[TB] %t - Writing the boot address into dpc", $realtime); + debug_mode_if.write_reg_abstract_cmd(riscv::CSR_DPC, begin_l2_instr, + s_tck, s_tms, s_trstn, s_tdi, s_tdo); + end // long debug module + jtag tests if(ENABLE_DM_TESTS == 1) begin - debug_mode_if.run_dm_tests(FC_CORE_ID, begin_l2_instr, - error, num_err, s_tck, s_tms, s_trstn, s_tdi, s_tdo); - // we don't have any program to load so we finish the testing - if (num_err == 0) begin - exit_status = `EXIT_SUCCESS; - end else begin - exit_status = `EXIT_FAIL; - $error("Debug Module: %d tests failed", num_err); - end - $stop; - end + debug_mode_if.run_dm_tests(FC_CORE_ID, begin_l2_instr, + error, num_err, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + // we don't have any program to load so we finish the testing + if (num_err == 0) begin + exit_status = `EXIT_SUCCESS; + end else begin + exit_status = `EXIT_FAIL; + $error("Debug Module: %d tests failed", num_err); + end + $stop; + end $display("[TB] %t - Loading L2", $realtime); if (USE_PULP_BUS_ACCESS) begin - // use pulp tap to load binary, put debug module in bypass - pulp_tap_pkg::load_L2(num_stim, stimuli, s_tck, s_tms, s_trstn, s_tdi, s_tdo); - + // use pulp tap to load binary + if (jtag_conf_reg ==0) begin + pulp_tap_pkg::load_L2(num_stim, stimuli, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + end else + if ( STIM_FROM == "JTAG") begin + // JTAG boot requires handshaking between the boot code and test bench + // The while loop corresponds to the handshake. + pulp_tap.init(s_tck, s_tms, s_trstn, s_tdi); + + pulp_tap.read32(32'h1a104074, 1, jtag_data,s_tck, s_tms, s_trstn, s_tdi, s_tdo); + + while(!jtag_data[0][0]) begin + pulp_tap.read32(32'h1a104074, 1, jtag_data,s_tck, s_tms, s_trstn, s_tdi, s_tdo); + end + + $display("[JTAG] synchronizing at the boot code %t",$realtime); + jtag_conf_reg = {USE_FLL ? 1'b0 : 1'b1, 6'b0, LOAD_L2 == "JTAG" ? 2'b11 : 2'b00}; + pulp_tap_pkg::load_L2(num_stim, stimuli, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + #5us; + test_mode_if.init(s_tck, s_tms, s_trstn, s_tdi); + #5us; + test_mode_if.set_confreg(jtag_conf_reg, jtag_conf_rego, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + #50us; + + end end else begin // use debug module to load binary - debug_mode_if.load_L2(num_stim, stimuli, s_tck, s_tms, s_trstn, s_tdi, s_tdo); - end + if (jtag_conf_reg == 0) debug_mode_if.load_L2(num_stim, stimuli, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + end // configure for debug module dmi access again debug_mode_if.init_dmi_access(s_tck, s_tms, s_trstn, s_tdi); // we have set dpc and loaded the binary, we can go now $display("[TB] %t - Resuming the CORE", $realtime); - debug_mode_if.resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo); - end + if(jtag_conf_reg ==0) debug_mode_if.resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo); + end if (ENABLE_DPI == 1) begin jtag_mux = JTAG_DPI; diff --git a/rtl/vip/hyper_model/README.txt b/rtl/vip/hyper_model/README.txt new file mode 100644 index 00000000..4a0e5a2c --- /dev/null +++ b/rtl/vip/hyper_model/README.txt @@ -0,0 +1 @@ +The hyperflash and hyperram models should be placed in this direcotry. diff --git a/rtl/vip/src_files.yml b/rtl/vip/src_files.yml index 640238cb..62f16f7c 100644 --- a/rtl/vip/src_files.yml +++ b/rtl/vip/src_files.yml @@ -1,3 +1,15 @@ +HYPER_model: + defines: [ + SPEEDSIM, + ] + files: [ + hyper_model/hyperram_model/s27ks0641.v, + hyper_model/hyperflash_model/s26ks512s.v, + ] + flags: [ + skip_synthesis, + ] + S25FS256_model: defines: [ SPEEDSIM, diff --git a/sim/boot/boot_code.cde b/sim/boot/boot_code.cde index 22d9d26d..508d59d0 100644 --- a/sim/boot/boot_code.cde +++ b/sim/boot/boot_code.cde @@ -30,13 +30,9 @@ 00000001010000000000000001101111 00000001000000000000000001101111 00000000110000000000000001101111 -00000000110000000000000001101111 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-00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 +01000001110001111000011110010011 +00100000111110010111110110000011 +10000111100100110110011110000101 +01111101000000110100001000000111 +00001011001101110010000011111001 +10001010100100111110010000000000 +10011011011011100100001001001001 +10011010110010100100110010000001 +00000000000010101010011010000011 +00000000110111001110010101100011 +00001001010000010000110000000101 +01000111101100101011111110110001 +10010010000001111010010000000011 +00000000100011010111011001100011 +00000000001111010000010000010011 +11000010000001000011010000110011 +00000001000000000000011110110111 +01111100011000111000011010100010 +10000110011011100000000011111011 +10000101001001101000010111010010 +10011101101000100011011001000001 +00001101001100111001101000100010 +00001100100001010100000010001101 +10000110001001101011011111010001 +10000101001001101000010111010010 +10000110001000100011011010110101 +10000101011011101000010110100110 +10110111110101010011110111100001 +00000010000000000001000100010111 +01111100100000010000000100010011 +00000000100000000000000001101111 +10000101100000101000000100110010 +11000110000001100001000101000001 +00000000000000000011010110011001 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 From 9568dea68aef915bcfd452c0b4ce8243331471fd Mon Sep 17 00:00:00 2001 From: Hayate Okuhara Date: Tue, 30 Jun 2020 17:52:48 +0200 Subject: [PATCH 2/4] tb parameter is fixed --- rtl/tb/tb_pulp.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rtl/tb/tb_pulp.sv b/rtl/tb/tb_pulp.sv index ab00f050..279b63f3 100644 --- a/rtl/tb/tb_pulp.sv +++ b/rtl/tb/tb_pulp.sv @@ -39,7 +39,7 @@ module tb_pulp; // the following parameters can activate instantiation of the verification IPs for Hyperflash, Hyperram, SPI, I2C and I2s // see the instructions in rtl/vip/{i2c_eeprom,i2s,spi_flash} to download the verification IPs parameter USE_HYPER_MODELS = 0; - parameter USE_S25FS256S_MODEL = 1; + parameter USE_S25FS256S_MODEL = 0; parameter USE_24FC1025_MODEL = 0; parameter USE_I2S_MODEL = 0; @@ -51,7 +51,7 @@ module tb_pulp; // In case any values are given, the debug module takes over the boot process. //parameter LOAD_L2 = "STANDALONE"; parameter LOAD_L2 = "JTAG"; - parameter STIM_FROM = "SPI_FLASH"; + parameter STIM_FROM = ""; // enable DPI-based JTAG parameter ENABLE_DPI = 0; From 6e4cd9a568c15f33d83e10252a46313a70fb5eb4 Mon Sep 17 00:00:00 2001 From: Hayate Okuhara Date: Mon, 6 Jul 2020 18:44:01 +0200 Subject: [PATCH 3/4] To extend the stand-alone boot capability --- rtl/pulpissimo/pad_frame.sv | 8 +++-- rtl/pulpissimo/pulpissimo.sv | 12 ++++--- rtl/pulpissimo/soc_domain.sv | 2 +- rtl/tb/tb_pulp.sv | 39 +++++++++++++-------- sim/boot/boot_code.cde | 68 ++++++++++++++++++------------------ 5 files changed, 72 insertions(+), 57 deletions(-) diff --git a/rtl/pulpissimo/pad_frame.sv b/rtl/pulpissimo/pad_frame.sv index 8871fbb7..72e69b91 100644 --- a/rtl/pulpissimo/pad_frame.sv +++ b/rtl/pulpissimo/pad_frame.sv @@ -141,7 +141,7 @@ module pad_frame output logic [7:0] in_hyper_dq_o, - output logic bootsel_o , + output logic [1:0] bootsel_o , // EXT CHIP TP PADS inout wire pad_sdio_clk , @@ -178,7 +178,8 @@ module pad_frame inout wire pad_uart_tx , inout wire pad_reset_n , - inout wire pad_bootsel , + inout wire pad_bootsel0 , + inout wire pad_bootsel1 , inout wire pad_jtag_tck , inout wire pad_jtag_tdi , inout wire pad_jtag_tdo , @@ -241,7 +242,8 @@ module pad_frame pad_functional_pu padinst_i2c0_scl (.OEN(~oe_i2c0_scl_i ), .I(out_i2c0_scl_i ), .O(in_i2c0_scl_o ), .PAD(pad_i2c0_scl ), .PEN(~pad_cfg_i[8][0] ) ); - pad_functional_pu padinst_bootsel (.OEN(1'b1 ), .I( ), .O(bootsel_o ), .PAD(pad_bootsel ), .PEN(1'b1 ) ); + pad_functional_pu padinst_bootsel0 (.OEN(1'b1 ), .I( ), .O(bootsel_o[0] ), .PAD(pad_bootsel0 ), .PEN(1'b1 ) ); + pad_functional_pu padinst_bootsel1 (.OEN(1'b1 ), .I( ), .O(bootsel_o[1] ), .PAD(pad_bootsel1 ), .PEN(1'b1 ) ); pad_functional_pu padinst_hyper_csno0 (.OEN( 1'b0 ), .I( out_hyper_csn_i[0] ), .O( ), .PAD( pad_hyper_cs_no0 ), .PEN(1'b1 ) ); pad_functional_pu padinst_hyper_csno1 (.OEN( 1'b0 ), .I( out_hyper_csn_i[1] ), .O( ), .PAD( pad_hyper_cs_no1 ), .PEN(1'b1 ) ); diff --git a/rtl/pulpissimo/pulpissimo.sv b/rtl/pulpissimo/pulpissimo.sv index f32ca4a9..d74a2ed0 100644 --- a/rtl/pulpissimo/pulpissimo.sv +++ b/rtl/pulpissimo/pulpissimo.sv @@ -70,7 +70,8 @@ module pulpissimo #( inout wire pad_hyper_resetn , inout wire pad_reset_n, - inout wire pad_bootsel, + inout wire pad_bootsel0, + inout wire pad_bootsel1, inout wire pad_jtag_tck, inout wire pad_jtag_tdi, @@ -370,7 +371,7 @@ module pulpissimo #( logic [EVENT_WIDTH-1:0] s_event_dataasync; logic s_cluster_irq; - logic s_bootsel; + logic [1:0] s_bootsel; APB_BUS apb_debug(); XBAR_TCDM_BUS lint_debug(); @@ -533,8 +534,8 @@ module pulpissimo #( .pad_i2c0_scl ( pad_i2c0_scl ), .pad_uart_rx ( pad_uart_rx ), .pad_uart_tx ( pad_uart_tx ), - .pad_hyper_cs_no0 ( pad_hyper_cs_no0 ), - .pad_hyper_cs_no1 ( pad_hyper_cs_no1 ), + .pad_hyper_cs_no0 ( pad_hyper_cs_no0 ), + .pad_hyper_cs_no1 ( pad_hyper_cs_no1 ), .pad_hyper_cko ( pad_hyper_cko ), .pad_hyper_ckno ( pad_hyper_ckno ), .pad_hyper_rwds ( pad_hyper_rwds ), @@ -548,7 +549,8 @@ module pulpissimo #( .pad_hyper_dqio7 ( pad_hyper_dqio7 ), .pad_hyper_resetn ( pad_hyper_resetn ), - .pad_bootsel ( pad_bootsel ), + .pad_bootsel0 ( pad_bootsel0 ), + .pad_bootsel1 ( pad_bootsel1 ), .pad_reset_n ( pad_reset_n ), .pad_jtag_tck ( pad_jtag_tck ), .pad_jtag_tdi ( pad_jtag_tdi ), diff --git a/rtl/pulpissimo/soc_domain.sv b/rtl/pulpissimo/soc_domain.sv index a6e4016e..f7c1ac29 100644 --- a/rtl/pulpissimo/soc_domain.sv +++ b/rtl/pulpissimo/soc_domain.sv @@ -39,7 +39,7 @@ module soc_domain #( input logic mode_select_i, - input logic bootsel_i, + input logic [1:0] bootsel_i, input logic jtag_tck_i, input logic jtag_trst_ni, diff --git a/rtl/tb/tb_pulp.sv b/rtl/tb/tb_pulp.sv index 279b63f3..be38ad35 100644 --- a/rtl/tb/tb_pulp.sv +++ b/rtl/tb/tb_pulp.sv @@ -46,12 +46,12 @@ module tb_pulp; // period of the external reference clock (32.769kHz) parameter REF_CLK_PERIOD = 30517ns; - // how L2 is loaded. valid values are "JTAG" or "STANDALONE", the latter works only when USE_S25FS256S_MODEL is 1 - // STIM_FROM is available when LOAD_L2 is "JTAG". Valid values are "JTAG", "SPI_FLASH", and "HYPER_FLASH". - // In case any values are given, the debug module takes over the boot process. - //parameter LOAD_L2 = "STANDALONE"; - parameter LOAD_L2 = "JTAG"; - parameter STIM_FROM = ""; + // how L2 is loaded. valid values are "JTAG" or "STANDALONE", the latter works when USE_S25FS256S_MODEL/USE_HYPER_MODELS are 1 + parameter LOAD_L2 = "JTAG"; + + // STIM_FROM sets where is the image data. + // In case any values are not given, the debug module takes over the boot process. + parameter STIM_FROM = "JTAG"; // can be "JTAG" "SPI_FLASH", "HYPER_FLASH", or "" // enable DPI-based JTAG parameter ENABLE_DPI = 0; @@ -223,8 +223,8 @@ module tb_pulp; wire w_master_i2s_sck; wire w_master_i2s_ws ; - wire w_bootsel; - logic s_bootsel; + wire [1:0] w_bootsel; + logic [1:0] s_bootsel; logic [8:0] jtag_conf_reg, jtag_conf_rego; //22bits but actually only the last 9bits are used @@ -646,7 +646,8 @@ module tb_pulp; .pad_hyper_resetn ( wire_reset_no ), .pad_reset_n ( w_rst_n ), - .pad_bootsel ( w_bootsel ), + .pad_bootsel0 ( w_bootsel[0] ), + .pad_bootsel1 ( w_bootsel[1] ), .pad_jtag_tck ( w_tck ), .pad_jtag_tdi ( w_tdi ), @@ -697,7 +698,7 @@ module tb_pulp; if (ENABLE_OPENOCD == 1) begin // Use openocd to interact with the simulation - s_bootsel = 1'b1; + s_bootsel = 2'b11; $display("[TB] %t - Releasing hard reset", $realtime); s_rst_n = 1'b1; @@ -714,9 +715,11 @@ module tb_pulp; if (LOAD_L2 == "STANDALONE") begin $display("[TB] %t - Releasing hard reset", $realtime); s_rst_n = 1'b1; - s_bootsel = 1'b0; + s_bootsel = (STIM_FROM == "SPI_FLASH") ? 2'b00: + (STIM_FROM == "HYPER_FLASH") ? 2'b01: 2'b00; + end else if (LOAD_L2 == "JTAG") begin - s_bootsel = 1'b1; + s_bootsel = 2'b11; end if (LOAD_L2 == "JTAG") begin @@ -757,8 +760,11 @@ module tb_pulp; // The boot code installed in the ROM checks the JTAG register value. // If jtag_conf_reg is set to 0, the debug module will take over the boot process - jtag_conf_reg = (STIM_FROM == "JTAG") ? {1'b0, 4'b0, 3'b001, 1'b0}: - (STIM_FROM == "SPI_FLASH") ? {1'b0, 4'b0, 3'b111, 1'b0}: + // The image file can be loaded also from SPI flash and Hyper flash + // even though this is not the stand-alone boot + + jtag_conf_reg = (STIM_FROM == "JTAG") ? {1'b0, 4'b0, 3'b001, 1'b0}: + (STIM_FROM == "SPI_FLASH") ? {1'b0, 4'b0, 3'b111, 1'b0}: (STIM_FROM == "HYPER_FLASH") ? {1'b0, 4'b0, 3'b101, 1'b0}: '0; test_mode_if.set_confreg(jtag_conf_reg, jtag_conf_rego, s_tck, s_tms, s_trstn, s_tdi, s_tdo); @@ -829,6 +835,11 @@ module tb_pulp; pulp_tap_pkg::load_L2(num_stim, stimuli, s_tck, s_tms, s_trstn, s_tdi, s_tdo); end else if ( STIM_FROM == "JTAG") begin + // Set fc_boot_addr + pulp_tap.init(s_tck, s_tms, s_trstn, s_tdi); + pulp_tap.write32(32'h1a104004, 1, begin_l2_instr, s_tck, s_tms, s_trstn, s_tdi, s_tdo); + $display("[TB] %t - set fc_boot_addr:%h", $realtime, begin_l2_instr); + // JTAG boot requires handshaking between the boot code and test bench // The while loop corresponds to the handshake. pulp_tap.init(s_tck, s_tms, s_trstn, s_tdi); diff --git a/sim/boot/boot_code.cde b/sim/boot/boot_code.cde index 508d59d0..96013e13 100644 --- a/sim/boot/boot_code.cde +++ b/sim/boot/boot_code.cde @@ -30,7 +30,7 @@ 00000001010000000000000001101111 00000001000000000000000001101111 00000000110000000000000001101111 -01001110000000000000000001101111 +01001110010000000000000001101111 00000000000000000000000001101111 00110000001000000000000001110011 00011010000100001010011110110111 @@ -224,8 +224,8 @@ 10010001001001111010111000100011 10010011001101111010001000100011 01000000000001100000011000010011 -01000100100001011000010110010011 -11110111000000110010001011000101 +01000100110001011000010110010011 +11110111000000110010001011010101 01101010011000110010000111010111 11111000100000110000000011100101 10011000101110100010000011010111 @@ -236,34 +236,35 @@ 11110101000000111111111100010111 10010101001110100010000011010111 10001101011100011001010101110010 -01000110101101111011011111100101 -10000111000100110001101000010000 -01000011000111000000011101000110 +01000111001101111011011111100101 +00000110100100110001101000010000 +01000010100111000000011101000111 11000110000001100001000101000001 -11000100001000101000001110100001 -10110111101100111100001000100110 -11000111101110011111011001000111 -10100001011000111000001110000101 -01000110100101010000010001010111 -00000000111101101110011001100011 -10101011011000111100111110011101 -10100000000000010000000000010111 -00000000011001111010010101100011 -00000010011101111010010001100011 -01000101100000011011111111011101 -00111101001001010100010100000001 -10000100001110101100001100011100 -01000101000001010100000000000100 -11110100100100110011010100001001 -11011000111111010001000000000100 -00011100000000001000011110110111 -00001000000001111000011110010011 +11000010001001101100010000100010 +00001100010001110010011100000011 +00000100000101110010001001100011 +00000000001101110010011001100011 +01000101100001011110101100101001 +00111101100000010100010100000001 +10110111101100111000001110100001 +11001011100111011111011001000111 +10101000011000111000001110000101 +11000111100101010000000000010111 +00000010010101111010001001100011 +11111110011101111010001111100011 +11000010100111001010000000000001 +01000000000001001000010000110110 +00110101000000010100010100000101 +00010000000001001111010010010011 +01000111101101111101100011111101 +01000011110111000001101000010000 10100000000000011001011110000010 -10111111111110010100010110000101 01000101000001010100010110000001 -00111111011100011011111111101001 -00001100010001101010011010000011 -10100111101101111101101011100101 +00110111010001011011011111011001 +00011010000100001010011110110111 +10000000000001111010000000100011 +00010000010100000000000001110011 +10100111101101111011111111110101 10100000001000110001101000010000 00000000011100111000000000000111 10111111111101010001000001010000 @@ -281,7 +282,7 @@ 11011010010101101100010010100010 11010010011001101101100001011010 11001110011011101101000001101010 -00110011101010011000100100100110 +00110011100110011000100100100110 10001011101100110100110000000001 11000110010100100000000100110100 01000000110010111010011110000011 @@ -334,21 +335,20 @@ 01111100011000111000011010100010 10000110011011100000000011111011 10000101001001101000010111010010 -10011101101000100011011001000001 +10011101101000100011111010110101 00001101001100111001101000100010 00001100100001010100000010001101 10000110001001101011011111010001 10000101001001101000010111010010 -10000110001000100011011010110101 +10000110001000100011011010100101 10000101011011101000010110100110 10110111110101010011110111100001 00000010000000000001000100010111 -01111100100000010000000100010011 +01111100010000010000000100010011 00000000100000000000000001101111 10000101100000101000000100110010 11000110000001100001000101000001 -00000000000000000011010110011001 -00000000000000000000000000000000 +00000000000000000011010110001001 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 From bb6513a15c968507eb45b78dcecc813730ea0450 Mon Sep 17 00:00:00 2001 From: Hayate Okuhara Date: Tue, 7 Jul 2020 04:01:50 +0200 Subject: [PATCH 4/4] the digit assignment for bootsel is modified --- rtl/tb/tb_pulp.sv | 6 +-- sim/boot/boot_code.cde | 84 +++++++++++++++++++++--------------------- 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/rtl/tb/tb_pulp.sv b/rtl/tb/tb_pulp.sv index be38ad35..6c969243 100644 --- a/rtl/tb/tb_pulp.sv +++ b/rtl/tb/tb_pulp.sv @@ -698,7 +698,7 @@ module tb_pulp; if (ENABLE_OPENOCD == 1) begin // Use openocd to interact with the simulation - s_bootsel = 2'b11; + s_bootsel = 2'b01; $display("[TB] %t - Releasing hard reset", $realtime); s_rst_n = 1'b1; @@ -716,10 +716,10 @@ module tb_pulp; $display("[TB] %t - Releasing hard reset", $realtime); s_rst_n = 1'b1; s_bootsel = (STIM_FROM == "SPI_FLASH") ? 2'b00: - (STIM_FROM == "HYPER_FLASH") ? 2'b01: 2'b00; + (STIM_FROM == "HYPER_FLASH") ? 2'b10: 2'b00; end else if (LOAD_L2 == "JTAG") begin - s_bootsel = 2'b11; + s_bootsel = 2'b01; end if (LOAD_L2 == "JTAG") begin diff --git a/sim/boot/boot_code.cde b/sim/boot/boot_code.cde index 96013e13..5147819c 100644 --- a/sim/boot/boot_code.cde +++ b/sim/boot/boot_code.cde @@ -30,7 +30,7 @@ 00000001010000000000000001101111 00000001000000000000000001101111 00000000110000000000000001101111 -01001110010000000000000001101111 +01010000100000000000000001101111 00000000000000000000000001101111 00110000001000000000000001110011 00011010000100001010011110110111 @@ -224,8 +224,8 @@ 10010001001001111010111000100011 10010011001101111010001000100011 01000000000001100000011000010011 -01000100110001011000010110010011 -11110111000000110010001011010101 +01000111000001011000010110010011 +11110111000000110010010000100001 01101010011000110010000111010111 11111000100000110000000011100101 10011000101110100010000011010111 @@ -236,38 +236,47 @@ 11110101000000111111111100010111 10010101001110100010000011010111 10001101011100011001010101110010 -01000111001101111011011111100101 -00000110100100110001101000010000 -01000010100111000000011101000111 +01000111101101111011011111100101 +10000111000100110001101000010000 +01000011000010000000011101000111 11000110000001100001000101000001 -11000010001001101100010000100010 -00001100010001110010011100000011 -00000100000101110010001001100011 -00000000001101110010011001100011 -01000101100001011110101100101001 -00111101100000010100010100000001 -10110111101100111000001110100001 -11001011100111011111011001000111 -10101000011000111000001110000101 -11000111100101010000000000010111 -00000010010101111010001001100011 -11111110011101111010001111100011 -11000010100111001010000000000001 -01000000000001001000010000110110 -00110101000000010100010100000101 -00010000000001001111010010010011 -01000111101101111101100011111101 -01000011110111000001101000010000 -10100000000000011001011110000010 -01000101000001010100010110000001 -00110111010001011011011111011001 +00110101001100111000000100100001 +10100111100000111111011001000101 +10101000011000110000110001000111 +10100000011000110000000000010111 +11100011100011010000001000100111 +01000101000000010100010110000101 +11000001000110010011010110111001 +00100000000111011000000100000101 00011010000100001010011110110111 10000000000001111010000000100011 00010000010100000000000001110011 -10100111101101111011111111110101 +01000101100000011011111111110101 +10110111110111010100010100000101 +10100111101101111111010101100101 10100000001000110001101000010000 00000000011100111000000000000111 10111111111101010001000001010000 +11000110000001100001000101000001 +11000010001001101100010000100010 +00000000000101010010110001100011 +11000100011000110100011110000101 +11001101000101010000000010100111 +00101001011000111010000000000001 +00100100011000110000001001010101 +10111111110111010000001001110101 +00011010000100000100011110110111 +00000111010001111000011110010011 +10000100001111101100001110001000 +01000101000001010100000000000100 +11110100100100110011001111011001 +11011000111111010001000000000100 +00011010000100000100011110110111 +10010111100000100100001111011100 +01000101100001011010000000000001 +00111011111100010100010100000001 +01000101000001010100010110000001 +00110111100001011011111111101101 10010110001011101000011110101010 00000000110001011001001101100011 11000111000010111000000010000010 @@ -282,7 +291,7 @@ 11011010010101101100010010100010 11010010011001101101100001011010 11001110011011101101000001101010 -00110011100110011000100100100110 +00110011000011011000100100100110 10001011101100110100110000000001 11000110010100100000000100110100 01000000110010111010011110000011 @@ -335,29 +344,20 @@ 01111100011000111000011010100010 10000110011011100000000011111011 10000101001001101000010111010010 -10011101101000100011111010110101 +10011101101000100011111010100001 00001101001100111001101000100010 00001100100001010100000010001101 10000110001001101011011111010001 10000101001001101000010111010010 -10000110001000100011011010100101 +10000110001000100011011010010001 10000101011011101000010110100110 10110111110101010011110111100001 00000010000000000001000100010111 -01111100010000010000000100010011 +01111010000000010000000100010011 00000000100000000000000001101111 10000101100000101000000100110010 11000110000001100001000101000001 -00000000000000000011010110001001 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 +00000000000000000011110100111001 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000